luton_pcb090.dts 4.1 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2018 Microsemi Corporation
  4. */
  5. /dts-v1/;
  6. #include "mscc,luton.dtsi"
  7. #include <dt-bindings/mscc/luton_data.h>
  8. / {
  9. model = "Luton26 PCB090 Reference Board";
  10. compatible = "mscc,luton-pcb090", "mscc,luton";
  11. aliases {
  12. serial0 = &uart0;
  13. spi0 = &spi0;
  14. };
  15. chosen {
  16. stdout-path = "serial0:115200n8";
  17. };
  18. gpio-leds {
  19. compatible = "gpio-leds";
  20. status_green {
  21. label = "pcb090:green:status";
  22. gpios = <&sgpio 64 GPIO_ACTIVE_HIGH>; /* p0.2 */
  23. default-state = "on";
  24. };
  25. status_red {
  26. label = "pcb090:red:status";
  27. gpios = <&sgpio 65 GPIO_ACTIVE_HIGH>; /* p1.2 */
  28. default-state = "off";
  29. };
  30. };
  31. };
  32. &sgpio {
  33. status = "okay";
  34. gpio-ranges = <&sgpio 0 0 96>;
  35. };
  36. &uart0 {
  37. status = "okay";
  38. };
  39. &spi0 {
  40. status = "okay";
  41. spi-flash@0 {
  42. compatible = "jedec,spi-nor";
  43. spi-max-frequency = <18000000>; /* input clock */
  44. reg = <0>; /* CS0 */
  45. spi-cs-high;
  46. };
  47. };
  48. &mdio0 {
  49. status = "okay";
  50. phy0: ethernet-phy@0 {
  51. reg = <0>;
  52. };
  53. phy1: ethernet-phy@1 {
  54. reg = <1>;
  55. };
  56. phy2: ethernet-phy@2 {
  57. reg = <2>;
  58. };
  59. phy3: ethernet-phy@3 {
  60. reg = <3>;
  61. };
  62. phy4: ethernet-phy@4 {
  63. reg = <4>;
  64. };
  65. phy5: ethernet-phy@5 {
  66. reg = <5>;
  67. };
  68. phy6: ethernet-phy@6 {
  69. reg = <6>;
  70. };
  71. phy7: ethernet-phy@7 {
  72. reg = <7>;
  73. };
  74. phy8: ethernet-phy@8 {
  75. reg = <8>;
  76. };
  77. phy9: ethernet-phy@9 {
  78. reg = <9>;
  79. };
  80. phy10: ethernet-phy@10 {
  81. reg = <10>;
  82. };
  83. phy11: ethernet-phy@11 {
  84. reg = <11>;
  85. };
  86. };
  87. &mdio1 {
  88. status = "okay";
  89. phy12: ethernet-phy@12 {
  90. reg = <0>;
  91. };
  92. phy13: ethernet-phy@13 {
  93. reg = <1>;
  94. };
  95. phy14: ethernet-phy@14 {
  96. reg = <2>;
  97. };
  98. phy15: ethernet-phy@15 {
  99. reg = <3>;
  100. };
  101. phy16: ethernet-phy@16 {
  102. reg = <4>;
  103. };
  104. phy17: ethernet-phy@17 {
  105. reg = <5>;
  106. };
  107. phy18: ethernet-phy@18 {
  108. reg = <6>;
  109. };
  110. phy19: ethernet-phy@19 {
  111. reg = <7>;
  112. };
  113. phy20: ethernet-phy@20 {
  114. reg = <8>;
  115. };
  116. phy21: ethernet-phy@21 {
  117. reg = <9>;
  118. };
  119. phy22: ethernet-phy@22 {
  120. reg = <10>;
  121. };
  122. phy23: ethernet-phy@23 {
  123. reg = <11>;
  124. };
  125. };
  126. &switch {
  127. ethernet-ports {
  128. port0: port@0 {
  129. reg = <0>;
  130. phy-handle = <&phy0>;
  131. };
  132. port1: port@1 {
  133. reg = <1>;
  134. phy-handle = <&phy1>;
  135. };
  136. port2: port@2 {
  137. reg = <2>;
  138. phy-handle = <&phy2>;
  139. };
  140. port3: port@3 {
  141. reg = <3>;
  142. phy-handle = <&phy3>;
  143. };
  144. port4: port@4 {
  145. reg = <4>;
  146. phy-handle = <&phy4>;
  147. };
  148. port5: port@5 {
  149. reg = <5>;
  150. phy-handle = <&phy5>;
  151. };
  152. port6: port@6 {
  153. reg = <6>;
  154. phy-handle = <&phy6>;
  155. };
  156. port7: port@7 {
  157. reg = <7>;
  158. phy-handle = <&phy7>;
  159. };
  160. port8: port@8 {
  161. reg = <8>;
  162. phy-handle = <&phy8>;
  163. };
  164. port9: port@9 {
  165. reg = <9>;
  166. phy-handle = <&phy9>;
  167. };
  168. port10: port@10 {
  169. reg = <10>;
  170. phy-handle = <&phy10>;
  171. };
  172. port11: port@11 {
  173. reg = <11>;
  174. phy-handle = <&phy11>;
  175. };
  176. port12: port@12 {
  177. reg = <12>;
  178. phy-handle = <&phy12>;
  179. phys = <&serdes_hsio 12 SERDES6G(1) PHY_MODE_QSGMII>;
  180. };
  181. port13: port@13 {
  182. reg = <13>;
  183. phy-handle = <&phy13>;
  184. phys = <&serdes_hsio 13 0xff PHY_MODE_QSGMII>;
  185. };
  186. port14: port@14 {
  187. reg = <14>;
  188. phy-handle = <&phy14>;
  189. phys = <&serdes_hsio 14 0xff PHY_MODE_QSGMII>;
  190. };
  191. port15: port@15 {
  192. reg = <15>;
  193. phy-handle = <&phy15>;
  194. phys = <&serdes_hsio 15 0xff PHY_MODE_QSGMII>;
  195. };
  196. port16: port@16 {
  197. reg = <16>;
  198. phy-handle = <&phy16>;
  199. phys = <&serdes_hsio 16 SERDES6G(2) PHY_MODE_QSGMII>;
  200. };
  201. port17: port@17 {
  202. reg = <17>;
  203. phy-handle = <&phy17>;
  204. phys = <&serdes_hsio 17 0xff PHY_MODE_QSGMII>;
  205. };
  206. port18: port@18 {
  207. reg = <18>;
  208. phy-handle = <&phy18>;
  209. phys = <&serdes_hsio 18 0xff PHY_MODE_QSGMII>;
  210. };
  211. port19: port@19 {
  212. reg = <19>;
  213. phy-handle = <&phy19>;
  214. phys = <&serdes_hsio 19 0xff PHY_MODE_QSGMII>;
  215. };
  216. port20: port@20 {
  217. reg = <20>;
  218. phy-handle = <&phy20>;
  219. phys = <&serdes_hsio 20 SERDES6G(3) PHY_MODE_QSGMII>;
  220. };
  221. port21: port@21 {
  222. reg = <21>;
  223. phy-handle = <&phy21>;
  224. phys = <&serdes_hsio 21 0xff PHY_MODE_QSGMII>;
  225. };
  226. port22: port@22 {
  227. reg = <22>;
  228. phy-handle = <&phy22>;
  229. phys = <&serdes_hsio 22 0xff PHY_MODE_QSGMII>;
  230. };
  231. port23: port@23 {
  232. reg = <23>;
  233. phy-handle = <&phy23>;
  234. phys = <&serdes_hsio 23 0xff PHY_MODE_QSGMII>;
  235. };
  236. };
  237. };