MIP405.h 13 KB

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  1. /*
  2. * (C) Copyright 2001, 2002
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. /*
  8. * board/config.h - configuration options, board specific
  9. */
  10. #ifndef __CONFIG_H
  11. #define __CONFIG_H
  12. /***********************************************************
  13. * High Level Configuration Options
  14. * (easy to change)
  15. ***********************************************************/
  16. #define CONFIG_405GP 1 /* This is a PPC405 CPU */
  17. #define CONFIG_SYS_TEXT_BASE 0xFFF80000
  18. /***********************************************************
  19. * Note that it may also be a MIP405T board which is a subset of the
  20. * MIP405
  21. ***********************************************************/
  22. /***********************************************************
  23. * WARNING:
  24. * CONFIG_BOOT_PCI is only used for first boot-up and should
  25. * NOT be enabled for production bootloader
  26. ***********************************************************/
  27. /*#define CONFIG_BOOT_PCI 1*/
  28. /***********************************************************
  29. * Clock
  30. ***********************************************************/
  31. #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
  32. /*
  33. * BOOTP options
  34. */
  35. #define CONFIG_BOOTP_BOOTFILESIZE
  36. #define CONFIG_BOOTP_BOOTPATH
  37. #define CONFIG_BOOTP_GATEWAY
  38. #define CONFIG_BOOTP_HOSTNAME
  39. /*
  40. * Command line configuration.
  41. */
  42. #define CONFIG_CMD_PCI
  43. #define CONFIG_CMD_REGINFO
  44. #define CONFIG_CMD_SAVES
  45. /**************************************************************
  46. * I2C Stuff:
  47. * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
  48. * 0x53.
  49. * The Atmel EEPROM uses 16Bit addressing.
  50. ***************************************************************/
  51. #define CONFIG_SYS_I2C
  52. #define CONFIG_SYS_I2C_PPC4XX
  53. #define CONFIG_SYS_I2C_PPC4XX_CH0
  54. #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 50000
  55. #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
  56. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */
  57. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
  58. /* mask of address bits that overflow into the "EEPROM chip address" */
  59. #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
  60. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
  61. /* 64 byte page write mode using*/
  62. /* last 6 bits of the address */
  63. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
  64. #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
  65. #define CONFIG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */
  66. #define CONFIG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */
  67. /***************************************************************
  68. * Definitions for Serial Presence Detect EEPROM address
  69. * (to get SDRAM settings)
  70. ***************************************************************/
  71. /*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0
  72. #define SDRAM_EEPROM_READ_ADDRESS 0xA1
  73. */
  74. /**************************************************************
  75. * Environment definitions
  76. **************************************************************/
  77. /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
  78. /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
  79. #define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
  80. #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
  81. #define CONFIG_IPADDR 10.0.0.100
  82. #define CONFIG_SERVERIP 10.0.0.1
  83. #define CONFIG_PREBOOT
  84. /***************************************************************
  85. * defines if an overwrite_console function exists
  86. *************************************************************/
  87. /***************************************************************
  88. * defines if the overwrite_console should be stored in the
  89. * environment
  90. **************************************************************/
  91. /**************************************************************
  92. * loads config
  93. *************************************************************/
  94. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  95. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  96. #define CONFIG_MISC_INIT_R
  97. /***********************************************************
  98. * Miscellaneous configurable options
  99. **********************************************************/
  100. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  101. #if defined(CONFIG_CMD_KGDB)
  102. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  103. #else
  104. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  105. #endif
  106. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  107. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  108. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  109. #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
  110. #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
  111. #define CONFIG_CONS_INDEX 1 /* Use UART0 */
  112. #define CONFIG_SYS_NS16550_SERIAL
  113. #define CONFIG_SYS_NS16550_REG_SIZE 1
  114. #define CONFIG_SYS_NS16550_CLK get_serial_clock()
  115. #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
  116. #define CONFIG_SYS_BASE_BAUD 916667
  117. /* The following table includes the supported baudrates */
  118. #define CONFIG_SYS_BAUDRATE_TABLE \
  119. { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
  120. 57600, 115200, 230400, 460800, 921600 }
  121. #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
  122. #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
  123. /*-----------------------------------------------------------------------
  124. * PCI stuff
  125. *-----------------------------------------------------------------------
  126. */
  127. #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
  128. #define PCI_HOST_FORCE 1 /* configure as pci host */
  129. #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
  130. #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
  131. #define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
  132. /* resource configuration */
  133. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
  134. #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
  135. #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
  136. #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
  137. #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
  138. #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
  139. #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
  140. #define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
  141. /*-----------------------------------------------------------------------
  142. * Start addresses for the final memory configuration
  143. * (Set up by the startup code)
  144. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  145. */
  146. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  147. #define CONFIG_SYS_FLASH_BASE 0xFFF80000
  148. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  149. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
  150. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
  151. /*
  152. * For booting Linux, the board info and command line data
  153. * have to be in the first 8 MB of memory, since this is
  154. * the maximum mapped by the Linux kernel during initialization.
  155. */
  156. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  157. /*-----------------------------------------------------------------------
  158. * FLASH organization
  159. */
  160. #define CONFIG_SYS_UPDATE_FLASH_SIZE
  161. #define CONFIG_SYS_FLASH_PROTECTION
  162. #define CONFIG_SYS_FLASH_EMPTY_INFO
  163. #define CONFIG_SYS_FLASH_CFI
  164. #define CONFIG_FLASH_CFI_DRIVER
  165. #define CONFIG_FLASH_SHOW_PROGRESS 45
  166. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  167. #define CONFIG_SYS_MAX_FLASH_SECT 256
  168. /*
  169. * JFFS2 partitions
  170. *
  171. */
  172. /* No command line, one static partition, whole device */
  173. #undef CONFIG_CMD_MTDPARTS
  174. #define CONFIG_JFFS2_DEV "nor0"
  175. #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
  176. #define CONFIG_JFFS2_PART_OFFSET 0x00000000
  177. /* mtdparts command line support */
  178. /* Note: fake mtd_id used, no linux mtd map file */
  179. /*
  180. #define CONFIG_CMD_MTDPARTS
  181. #define MTDIDS_DEFAULT "nor0=mip405-0"
  182. #define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)"
  183. */
  184. /*-----------------------------------------------------------------------
  185. * Logbuffer Configuration
  186. */
  187. #undef CONFIG_LOGBUFFER /* supported but not enabled */
  188. /*-----------------------------------------------------------------------
  189. * Bootcountlimit Configuration
  190. */
  191. #undef CONFIG_BOOTCOUNT_LIMIT /* supported but not enabled */
  192. /*-----------------------------------------------------------------------
  193. * POST Configuration
  194. */
  195. #if 0 /* enable this if POST is desired (is supported but not enabled) */
  196. #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
  197. CONFIG_SYS_POST_CPU | \
  198. CONFIG_SYS_POST_RTC | \
  199. CONFIG_SYS_POST_I2C)
  200. #endif
  201. /*
  202. * Init Memory Controller:
  203. */
  204. #define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
  205. #define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
  206. /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
  207. #define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
  208. #define CONFIG_BOARD_EARLY_INIT_R
  209. /* Peripheral Bus Mapping */
  210. #define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/
  211. #define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/
  212. #define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/
  213. #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
  214. #define CONFIG_PORT_ADDR PER_PLD_ADDR + 5
  215. /*-----------------------------------------------------------------------
  216. * Definitions for initial stack pointer and data area (in On Chip SRAM)
  217. */
  218. #define CONFIG_SYS_TEMP_STACK_OCM 1
  219. #define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
  220. #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
  221. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
  222. #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
  223. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  224. /* reserve some memory for POST and BOOT limit info */
  225. #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
  226. #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
  227. #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
  228. #endif
  229. /***********************************************************************
  230. * External peripheral base address
  231. ***********************************************************************/
  232. #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
  233. /***********************************************************************
  234. * Last Stage Init
  235. ***********************************************************************/
  236. #define CONFIG_LAST_STAGE_INIT
  237. /************************************************************
  238. * Ethernet Stuff
  239. ***********************************************************/
  240. #define CONFIG_PPC4xx_EMAC
  241. #define CONFIG_MII 1 /* MII PHY management */
  242. #define CONFIG_PHY_ADDR 1 /* PHY address */
  243. #define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */
  244. #define CONFIG_PHY_CMD_DELAY 40 /* Intel LXT971A needs this */
  245. /************************************************************
  246. * RTC
  247. ***********************************************************/
  248. #define CONFIG_RTC_MC146818
  249. #undef CONFIG_WATCHDOG /* watchdog disabled */
  250. /************************************************************
  251. * IDE/ATA stuff
  252. ************************************************************/
  253. #if defined(CONFIG_TARGET_MIP405T)
  254. #define CONFIG_SYS_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */
  255. #else
  256. #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
  257. #endif
  258. #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
  259. #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
  260. #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
  261. #define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
  262. #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
  263. #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
  264. #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
  265. #undef CONFIG_IDE_LED /* no led for ide supported */
  266. #define CONFIG_IDE_RESET /* reset for ide supported... */
  267. #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
  268. #define CONFIG_SUPPORT_VFAT
  269. /************************************************************
  270. * ATAPI support (experimental)
  271. ************************************************************/
  272. #define CONFIG_ATAPI /* enable ATAPI Support */
  273. /************************************************************
  274. * DISK Partition support
  275. ************************************************************/
  276. /************************************************************
  277. * Video support
  278. ************************************************************/
  279. #define CONFIG_VIDEO_LOGO
  280. #undef CONFIG_VIDEO_ONBOARD
  281. /************************************************************
  282. * USB support EXPERIMENTAL
  283. ************************************************************/
  284. #if !defined(CONFIG_TARGET_MIP405T)
  285. #define CONFIG_USB_UHCI
  286. /* Enable needed helper functions */
  287. #endif
  288. /************************************************************
  289. * Debug support
  290. ************************************************************/
  291. #if defined(CONFIG_CMD_KGDB)
  292. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  293. #endif
  294. /************************************************************
  295. * support BZIP2 compression
  296. ************************************************************/
  297. #define CONFIG_BZIP2 1
  298. #endif /* __CONFIG_H */