uic.c 4.1 KB

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  1. /*
  2. * (C) Copyright 2000-2002
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * (C) Copyright 2002 (440 port)
  6. * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
  7. *
  8. * (C) Copyright 2003 (440GX port)
  9. * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
  10. *
  11. * (C) Copyright 2008 (PPC440X05 port for Virtex 5 FX)
  12. * Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
  13. * Work supported by Qtechnology (htpp://qtec.com)
  14. *
  15. * SPDX-License-Identifier: GPL-2.0+
  16. */
  17. #include <common.h>
  18. #include <watchdog.h>
  19. #include <command.h>
  20. #include <asm/processor.h>
  21. #include <asm/interrupt.h>
  22. #include <asm/ppc4xx.h>
  23. #include <ppc_asm.tmpl>
  24. #if (UIC_MAX > 3)
  25. #define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
  26. UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI) | \
  27. UIC_MASK(VECNUM_UIC3CI) | UIC_MASK(VECNUM_UIC3NCI))
  28. #elif (UIC_MAX > 2)
  29. #define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
  30. UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI))
  31. #elif (UIC_MAX > 1)
  32. #define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI))
  33. #else
  34. #define UICB0_ALL 0
  35. #endif
  36. u32 get_dcr(u16);
  37. DECLARE_GLOBAL_DATA_PTR;
  38. void pic_enable(void)
  39. {
  40. #if (UIC_MAX > 1)
  41. /* Install the UIC1 handlers */
  42. irq_install_handler(VECNUM_UIC1NCI, (void *)(void *)external_interrupt, 0);
  43. irq_install_handler(VECNUM_UIC1CI, (void *)(void *)external_interrupt, 0);
  44. #endif
  45. #if (UIC_MAX > 2)
  46. irq_install_handler(VECNUM_UIC2NCI, (void *)(void *)external_interrupt, 0);
  47. irq_install_handler(VECNUM_UIC2CI, (void *)(void *)external_interrupt, 0);
  48. #endif
  49. #if (UIC_MAX > 3)
  50. irq_install_handler(VECNUM_UIC3NCI, (void *)(void *)external_interrupt, 0);
  51. irq_install_handler(VECNUM_UIC3CI, (void *)(void *)external_interrupt, 0);
  52. #endif
  53. }
  54. /* Handler for UIC interrupt */
  55. static void uic_interrupt(u32 uic_base, int vec_base)
  56. {
  57. u32 uic_msr;
  58. u32 msr_shift;
  59. int vec;
  60. /*
  61. * Read masked interrupt status register to determine interrupt source
  62. */
  63. uic_msr = get_dcr(uic_base + UIC_MSR);
  64. msr_shift = uic_msr;
  65. vec = vec_base;
  66. while (msr_shift != 0) {
  67. if (msr_shift & 0x80000000)
  68. interrupt_run_handler(vec);
  69. /*
  70. * Shift msr to next position and increment vector
  71. */
  72. msr_shift <<= 1;
  73. vec++;
  74. }
  75. }
  76. /*
  77. * Handle external interrupts
  78. */
  79. void external_interrupt(struct pt_regs *regs)
  80. {
  81. u32 uic_msr;
  82. /*
  83. * Read masked interrupt status register to determine interrupt source
  84. */
  85. uic_msr = mfdcr(UIC0MSR);
  86. #if (UIC_MAX > 1)
  87. if ((UIC_MASK(VECNUM_UIC1CI) & uic_msr) ||
  88. (UIC_MASK(VECNUM_UIC1NCI) & uic_msr))
  89. uic_interrupt(UIC1_DCR_BASE, 32);
  90. #endif
  91. #if (UIC_MAX > 2)
  92. if ((UIC_MASK(VECNUM_UIC2CI) & uic_msr) ||
  93. (UIC_MASK(VECNUM_UIC2NCI) & uic_msr))
  94. uic_interrupt(UIC2_DCR_BASE, 64);
  95. #endif
  96. #if (UIC_MAX > 3)
  97. if ((UIC_MASK(VECNUM_UIC3CI) & uic_msr) ||
  98. (UIC_MASK(VECNUM_UIC3NCI) & uic_msr))
  99. uic_interrupt(UIC3_DCR_BASE, 96);
  100. #endif
  101. mtdcr(UIC0SR, (uic_msr & UICB0_ALL));
  102. if (uic_msr & ~(UICB0_ALL))
  103. uic_interrupt(UIC0_DCR_BASE, 0);
  104. return;
  105. }
  106. void pic_irq_ack(unsigned int vec)
  107. {
  108. if ((vec >= 0) && (vec < 32))
  109. mtdcr(UIC0SR, UIC_MASK(vec));
  110. else if ((vec >= 32) && (vec < 64))
  111. mtdcr(UIC1SR, UIC_MASK(vec));
  112. else if ((vec >= 64) && (vec < 96))
  113. mtdcr(UIC2SR, UIC_MASK(vec));
  114. else if (vec >= 96)
  115. mtdcr(UIC3SR, UIC_MASK(vec));
  116. }
  117. /*
  118. * Install and free a interrupt handler.
  119. */
  120. void pic_irq_enable(unsigned int vec)
  121. {
  122. if ((vec >= 0) && (vec < 32))
  123. mtdcr(UIC0ER, mfdcr(UIC0ER) | UIC_MASK(vec));
  124. else if ((vec >= 32) && (vec < 64))
  125. mtdcr(UIC1ER, mfdcr(UIC1ER) | UIC_MASK(vec));
  126. else if ((vec >= 64) && (vec < 96))
  127. mtdcr(UIC2ER, mfdcr(UIC2ER) | UIC_MASK(vec));
  128. else if (vec >= 96)
  129. mtdcr(UIC3ER, mfdcr(UIC3ER) | UIC_MASK(vec));
  130. debug("Install interrupt vector %d\n", vec);
  131. }
  132. void pic_irq_disable(unsigned int vec)
  133. {
  134. if ((vec >= 0) && (vec < 32))
  135. mtdcr(UIC0ER, mfdcr(UIC0ER) & ~UIC_MASK(vec));
  136. else if ((vec >= 32) && (vec < 64))
  137. mtdcr(UIC1ER, mfdcr(UIC1ER) & ~UIC_MASK(vec));
  138. else if ((vec >= 64) && (vec < 96))
  139. mtdcr(UIC2ER, mfdcr(UIC2ER) & ~UIC_MASK(vec));
  140. else if (vec >= 96)
  141. mtdcr(UIC3ER, mfdcr(UIC3ER) & ~UIC_MASK(vec));
  142. }