imx6ull-somlabs-visionsom.dts 5.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017-2019 SoMLabs
  4. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  5. */
  6. /dts-v1/;
  7. #include <dt-bindings/input/input.h>
  8. #include "imx6ull.dtsi"
  9. / {
  10. model = "SoMLabs VisionSOM-6ULL";
  11. compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
  12. chosen {
  13. stdout-path = &uart1;
  14. };
  15. memory {
  16. reg = <0x80000000 0x20000000>;
  17. };
  18. leds {
  19. compatible = "gpio-leds";
  20. usr0 {
  21. label = "usr0";
  22. gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
  23. linux,default-trigger = "heartbeat";
  24. };
  25. usr1 {
  26. label = "usr1";
  27. gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
  28. linux,default-trigger = "mmc0";
  29. };
  30. usr2 {
  31. label = "usr2";
  32. gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
  33. linux,default-trigger = "mmc1";
  34. };
  35. usr3 {
  36. label = "usr3";
  37. gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
  38. };
  39. };
  40. regulators {
  41. compatible = "simple-bus";
  42. #address-cells = <1>;
  43. #size-cells = <0>;
  44. reg_usb_otg1_vbus: regulator@2 {
  45. compatible = "regulator-fixed";
  46. reg = <2>;
  47. pinctrl-names = "default";
  48. pinctrl-0 = <&pinctrl_usb_otg1>;
  49. regulator-name = "usb_otg1_vbus";
  50. regulator-min-microvolt = <5000000>;
  51. regulator-max-microvolt = <5000000>;
  52. gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
  53. enable-active-high;
  54. };
  55. reg_usb_otg2_vbus: regulator@3 {
  56. compatible = "regulator-fixed";
  57. reg = <3>;
  58. pinctrl-names = "default";
  59. pinctrl-0 = <&pinctrl_usb_otg2>;
  60. regulator-name = "usb_otg2_vbus";
  61. regulator-min-microvolt = <5000000>;
  62. regulator-max-microvolt = <5000000>;
  63. gpio = <&gpio2 8 GPIO_ACTIVE_HIGH>;
  64. enable-active-high;
  65. };
  66. };
  67. };
  68. &cpu0 {
  69. arm-supply = <&reg_arm>;
  70. soc-supply = <&reg_soc>;
  71. };
  72. &clks {
  73. assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
  74. assigned-clock-rates = <786432000>;
  75. };
  76. &fec1 {
  77. pinctrl-names = "default";
  78. pinctrl-0 = <&pinctrl_enet1>;
  79. phy-mode = "rmii";
  80. phy-handle = <&ethphy0>;
  81. status = "okay";
  82. mdio {
  83. #address-cells = <1>;
  84. #size-cells = <0>;
  85. ethphy0: ethernet-phy@1 {
  86. compatible = "ethernet-phy-ieee802.3-c22";
  87. reg = <1>;
  88. };
  89. };
  90. };
  91. &gpc {
  92. fsl,cpu_pupscr_sw2iso = <0x1>;
  93. fsl,cpu_pupscr_sw = <0x0>;
  94. fsl,cpu_pdnscr_iso2sw = <0x1>;
  95. fsl,cpu_pdnscr_iso = <0x1>;
  96. fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
  97. };
  98. &i2c1 {
  99. clock-frequency = <100000>;
  100. pinctrl-names = "default";
  101. pinctrl-0 = <&pinctrl_i2c1>;
  102. };
  103. &i2c2 {
  104. clock_frequency = <100000>;
  105. pinctrl-names = "default";
  106. pinctrl-0 = <&pinctrl_i2c2>;
  107. };
  108. &iomuxc {
  109. pinctrl-names = "default";
  110. pinctrl-0 = <&pinctrl_hog_1>;
  111. pinctrl_hog_1: hoggrp-1 {
  112. fsl,pins = <
  113. /* 32kHz low power reference clock for WiFi */
  114. MX6UL_PAD_JTAG_TCK__OSC32K_32K_OUT 0x17099
  115. /* LED 0..3 */
  116. MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x17099
  117. MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x17099
  118. MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x17099
  119. MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x17099
  120. >;
  121. };
  122. pinctrl_enet1: enet1grp {
  123. fsl,pins = <
  124. MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
  125. MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1F829
  126. MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
  127. MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
  128. MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
  129. MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
  130. MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
  131. MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
  132. MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
  133. MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400010a9
  134. >;
  135. };
  136. pinctrl_i2c1: i2c1grp {
  137. fsl,pins = <
  138. MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
  139. MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
  140. >;
  141. };
  142. pinctrl_i2c2: i2c2grp {
  143. fsl,pins = <
  144. MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
  145. MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
  146. >;
  147. };
  148. pinctrl_tsc: tscgrp {
  149. fsl,pins = <
  150. MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
  151. MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
  152. MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
  153. MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
  154. >;
  155. };
  156. pinctrl_uart1: uart1grp {
  157. fsl,pins = <
  158. MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
  159. MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
  160. >;
  161. };
  162. pinctrl_usdhc2: usdhc2grp {
  163. fsl,pins = <
  164. MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
  165. MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
  166. MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
  167. MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
  168. MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
  169. MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
  170. >;
  171. };
  172. pinctrl_wdog: wdoggrp {
  173. fsl,pins = <
  174. MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY 0x30b0
  175. >;
  176. };
  177. pinctrl_usb_otg1: usbotg1grp {
  178. fsl,pins = <
  179. MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
  180. MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x10b0
  181. >;
  182. };
  183. pinctrl_usb_otg2: usbotg2grp {
  184. fsl,pins = <
  185. MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x10b0
  186. >;
  187. };
  188. };
  189. &tsc {
  190. pinctrl-names = "default";
  191. pinctrl-0 = <&pinctrl_tsc>;
  192. xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
  193. measure-delay-time = <0xffff>;
  194. pre-charge-time = <0xfff>;
  195. status = "okay";
  196. };
  197. &uart1 {
  198. pinctrl-names = "default";
  199. pinctrl-0 = <&pinctrl_uart1>;
  200. status = "okay";
  201. };
  202. &usbotg1 {
  203. vbus-supply = <&reg_usb_otg1_vbus>;
  204. pinctrl-names = "default";
  205. pinctrl-0 = <&pinctrl_usb_otg1>;
  206. dr_mode = "otg";
  207. srp-disable;
  208. hnp-disable;
  209. adp-disable;
  210. status = "okay";
  211. };
  212. &usbotg2 {
  213. vbus-supply = <&reg_usb_otg2_vbus>;
  214. dr_mode = "host";
  215. status = "okay";
  216. };
  217. &usbphy1 {
  218. tx-d-cal = <0x5>;
  219. };
  220. &usbphy2 {
  221. tx-d-cal = <0x5>;
  222. };
  223. &usdhc2 {
  224. non-removable;
  225. disable-wp;
  226. status = "okay";
  227. };
  228. &wdog1 {
  229. pinctrl-names = "default";
  230. pinctrl-0 = <&pinctrl_wdog>;
  231. fsl,wdog_b;
  232. };