spmi-msm.c 4.7 KB

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  1. /*
  2. * Qualcomm SPMI bus driver
  3. *
  4. * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
  5. *
  6. * Loosely based on Little Kernel driver
  7. *
  8. * SPDX-License-Identifier: BSD-3-Clause
  9. */
  10. #include <common.h>
  11. #include <dm.h>
  12. #include <errno.h>
  13. #include <fdtdec.h>
  14. #include <asm/io.h>
  15. #include <spmi/spmi.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. #define ARB_CHANNEL_OFFSET(n) (0x4 * (n))
  18. #define SPMI_CH_OFFSET(chnl) ((chnl) * 0x8000)
  19. #define SPMI_REG_CMD0 0x0
  20. #define SPMI_REG_CONFIG 0x4
  21. #define SPMI_REG_STATUS 0x8
  22. #define SPMI_REG_WDATA 0x10
  23. #define SPMI_REG_RDATA 0x18
  24. #define SPMI_CMD_OPCODE_SHIFT 27
  25. #define SPMI_CMD_SLAVE_ID_SHIFT 20
  26. #define SPMI_CMD_ADDR_SHIFT 12
  27. #define SPMI_CMD_ADDR_OFFSET_SHIFT 4
  28. #define SPMI_CMD_BYTE_CNT_SHIFT 0
  29. #define SPMI_CMD_EXT_REG_WRITE_LONG 0x00
  30. #define SPMI_CMD_EXT_REG_READ_LONG 0x01
  31. #define SPMI_STATUS_DONE 0x1
  32. #define SPMI_MAX_CHANNELS 128
  33. #define SPMI_MAX_SLAVES 16
  34. #define SPMI_MAX_PERIPH 256
  35. struct msm_spmi_priv {
  36. phys_addr_t arb_chnl; /* ARB channel mapping base */
  37. phys_addr_t spmi_core; /* SPMI core */
  38. phys_addr_t spmi_obs; /* SPMI observer */
  39. /* SPMI channel map */
  40. uint8_t channel_map[SPMI_MAX_SLAVES][SPMI_MAX_PERIPH];
  41. };
  42. static int msm_spmi_write(struct udevice *dev, int usid, int pid, int off,
  43. uint8_t val)
  44. {
  45. struct msm_spmi_priv *priv = dev_get_priv(dev);
  46. unsigned channel;
  47. uint32_t reg = 0;
  48. if (usid >= SPMI_MAX_SLAVES)
  49. return -EIO;
  50. if (pid >= SPMI_MAX_PERIPH)
  51. return -EIO;
  52. channel = priv->channel_map[usid][pid];
  53. /* Disable IRQ mode for the current channel*/
  54. writel(0x0, priv->spmi_core + SPMI_CH_OFFSET(channel) +
  55. SPMI_REG_CONFIG);
  56. /* Write single byte */
  57. writel(val, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_WDATA);
  58. /* Prepare write command */
  59. reg |= SPMI_CMD_EXT_REG_WRITE_LONG << SPMI_CMD_OPCODE_SHIFT;
  60. reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT);
  61. reg |= (pid << SPMI_CMD_ADDR_SHIFT);
  62. reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
  63. reg |= 1; /* byte count */
  64. /* Send write command */
  65. writel(reg, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
  66. /* Wait till CMD DONE status */
  67. reg = 0;
  68. while (!reg) {
  69. reg = readl(priv->spmi_core + SPMI_CH_OFFSET(channel) +
  70. SPMI_REG_STATUS);
  71. }
  72. if (reg ^ SPMI_STATUS_DONE) {
  73. printf("SPMI write failure.\n");
  74. return -EIO;
  75. }
  76. return 0;
  77. }
  78. static int msm_spmi_read(struct udevice *dev, int usid, int pid, int off)
  79. {
  80. struct msm_spmi_priv *priv = dev_get_priv(dev);
  81. unsigned channel;
  82. uint32_t reg = 0;
  83. if (usid >= SPMI_MAX_SLAVES)
  84. return -EIO;
  85. if (pid >= SPMI_MAX_PERIPH)
  86. return -EIO;
  87. channel = priv->channel_map[usid][pid];
  88. /* Disable IRQ mode for the current channel*/
  89. writel(0x0, priv->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG);
  90. /* Prepare read command */
  91. reg |= SPMI_CMD_EXT_REG_READ_LONG << SPMI_CMD_OPCODE_SHIFT;
  92. reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT);
  93. reg |= (pid << SPMI_CMD_ADDR_SHIFT);
  94. reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
  95. reg |= 1; /* byte count */
  96. /* Request read */
  97. writel(reg, priv->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
  98. /* Wait till CMD DONE status */
  99. reg = 0;
  100. while (!reg) {
  101. reg = readl(priv->spmi_obs + SPMI_CH_OFFSET(channel) +
  102. SPMI_REG_STATUS);
  103. }
  104. if (reg ^ SPMI_STATUS_DONE) {
  105. printf("SPMI read failure.\n");
  106. return -EIO;
  107. }
  108. /* Read the data */
  109. return readl(priv->spmi_obs + SPMI_CH_OFFSET(channel) +
  110. SPMI_REG_RDATA) & 0xFF;
  111. }
  112. static struct dm_spmi_ops msm_spmi_ops = {
  113. .read = msm_spmi_read,
  114. .write = msm_spmi_write,
  115. };
  116. static int msm_spmi_probe(struct udevice *dev)
  117. {
  118. struct udevice *parent = dev->parent;
  119. struct msm_spmi_priv *priv = dev_get_priv(dev);
  120. int i;
  121. priv->arb_chnl = dev_get_addr(dev);
  122. priv->spmi_core = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
  123. parent->of_offset,
  124. dev->of_offset,
  125. "reg", 1, NULL);
  126. priv->spmi_obs = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
  127. parent->of_offset,
  128. dev->of_offset, "reg",
  129. 2, NULL);
  130. if (priv->arb_chnl == FDT_ADDR_T_NONE ||
  131. priv->spmi_core == FDT_ADDR_T_NONE ||
  132. priv->spmi_obs == FDT_ADDR_T_NONE)
  133. return -EINVAL;
  134. /* Scan peripherals connected to each SPMI channel */
  135. for (i = 0; i < SPMI_MAX_CHANNELS ; i++) {
  136. uint32_t periph = readl(priv->arb_chnl + ARB_CHANNEL_OFFSET(i));
  137. uint8_t slave_id = (periph & 0xf0000) >> 16;
  138. uint8_t pid = (periph & 0xff00) >> 8;
  139. priv->channel_map[slave_id][pid] = i;
  140. }
  141. return 0;
  142. }
  143. static const struct udevice_id msm_spmi_ids[] = {
  144. { .compatible = "qcom,spmi-pmic-arb" },
  145. { }
  146. };
  147. U_BOOT_DRIVER(msm_spmi) = {
  148. .name = "msm_spmi",
  149. .id = UCLASS_SPMI,
  150. .of_match = msm_spmi_ids,
  151. .ops = &msm_spmi_ops,
  152. .probe = msm_spmi_probe,
  153. .priv_auto_alloc_size = sizeof(struct msm_spmi_priv),
  154. };