clearfog.c 7.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <env.h>
  7. #include <i2c.h>
  8. #include <init.h>
  9. #include <miiphy.h>
  10. #include <net.h>
  11. #include <netdev.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/cpu.h>
  14. #include <asm/arch/soc.h>
  15. #include <linux/bitops.h>
  16. #include <linux/delay.h>
  17. #include "../common/tlv_data.h"
  18. #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
  19. #include <../serdes/a38x/high_speed_env_spec.h>
  20. DECLARE_GLOBAL_DATA_PTR;
  21. /*
  22. * Those values and defines are taken from the Marvell U-Boot version
  23. * "u-boot-2013.01-15t1-clearfog"
  24. */
  25. #define BOARD_GPP_OUT_ENA_LOW 0xffffffff
  26. #define BOARD_GPP_OUT_ENA_MID 0xffffffff
  27. #define BOARD_GPP_OUT_VAL_LOW 0x0
  28. #define BOARD_GPP_OUT_VAL_MID 0x0
  29. #define BOARD_GPP_POL_LOW 0x0
  30. #define BOARD_GPP_POL_MID 0x0
  31. static struct tlv_data cf_tlv_data;
  32. static void cf_read_tlv_data(void)
  33. {
  34. static bool read_once;
  35. if (read_once)
  36. return;
  37. read_once = true;
  38. read_tlv_data(&cf_tlv_data);
  39. }
  40. /* The starting board_serdes_map reflects original Clearfog Pro usage */
  41. static struct serdes_map board_serdes_map[] = {
  42. {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  43. {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  44. {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  45. {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  46. {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  47. {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  48. };
  49. void config_cfbase_serdes_map(void)
  50. {
  51. board_serdes_map[4].serdes_type = USB3_HOST0;
  52. board_serdes_map[4].serdes_speed = SERDES_SPEED_5_GBPS;
  53. board_serdes_map[4].serdes_mode = SERDES_DEFAULT_MODE;
  54. }
  55. int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
  56. {
  57. cf_read_tlv_data();
  58. /* Apply build configuration options before runtime configuration */
  59. if (IS_ENABLED(CONFIG_CLEARFOG_SFP_25GB))
  60. board_serdes_map[5].serdes_speed = SERDES_SPEED_3_125_GBPS;
  61. if (IS_ENABLED(CONFIG_CLEARFOG_CON2_SATA)) {
  62. board_serdes_map[4].serdes_type = SATA2;
  63. board_serdes_map[4].serdes_speed = SERDES_SPEED_3_GBPS;
  64. board_serdes_map[4].serdes_mode = SERDES_DEFAULT_MODE;
  65. board_serdes_map[4].swap_rx = 1;
  66. }
  67. if (IS_ENABLED(CONFIG_CLEARFOG_CON3_SATA)) {
  68. board_serdes_map[2].serdes_type = SATA1;
  69. board_serdes_map[2].serdes_speed = SERDES_SPEED_3_GBPS;
  70. board_serdes_map[2].serdes_mode = SERDES_DEFAULT_MODE;
  71. board_serdes_map[2].swap_rx = 1;
  72. }
  73. /* Apply runtime detection changes */
  74. if (sr_product_is(&cf_tlv_data, "Clearfog GTR")) {
  75. board_serdes_map[0].serdes_type = PEX0;
  76. board_serdes_map[0].serdes_speed = SERDES_SPEED_5_GBPS;
  77. board_serdes_map[0].serdes_mode = PEX_ROOT_COMPLEX_X1;
  78. } else if (sr_product_is(&cf_tlv_data, "Clearfog Pro")) {
  79. /* handle recognized product as noop, no adjustment required */
  80. } else if (sr_product_is(&cf_tlv_data, "Clearfog Base")) {
  81. config_cfbase_serdes_map();
  82. } else {
  83. /*
  84. * Fallback to static default. EEPROM TLV support is not
  85. * enabled, runtime detection failed, hardware support is not
  86. * present, EEPROM is corrupt, or an unrecognized product name
  87. * is present.
  88. */
  89. if (IS_ENABLED(CONFIG_SPL_CMD_TLV_EEPROM))
  90. puts("EEPROM TLV detection failed: ");
  91. puts("Using static config for ");
  92. if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE)) {
  93. puts("Clearfog Base.\n");
  94. config_cfbase_serdes_map();
  95. } else {
  96. puts("Clearfog Pro.\n");
  97. }
  98. }
  99. *serdes_map_array = board_serdes_map;
  100. *count = ARRAY_SIZE(board_serdes_map);
  101. return 0;
  102. }
  103. /*
  104. * Define the DDR layout / topology here in the board file. This will
  105. * be used by the DDR3 init code in the SPL U-Boot version to configure
  106. * the DDR3 controller.
  107. */
  108. static struct mv_ddr_topology_map board_topology_map = {
  109. DEBUG_LEVEL_ERROR,
  110. 0x1, /* active interfaces */
  111. /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
  112. { { { {0x1, 0, 0, 0},
  113. {0x1, 0, 0, 0},
  114. {0x1, 0, 0, 0},
  115. {0x1, 0, 0, 0},
  116. {0x1, 0, 0, 0} },
  117. SPEED_BIN_DDR_1600K, /* speed_bin */
  118. MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
  119. MV_DDR_DIE_CAP_4GBIT, /* mem_size */
  120. MV_DDR_FREQ_800, /* frequency */
  121. 0, 0, /* cas_wl cas_l */
  122. MV_DDR_TEMP_LOW, /* temperature */
  123. MV_DDR_TIM_DEFAULT} }, /* timing */
  124. BUS_MASK_32BIT, /* Busses mask */
  125. MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
  126. { {0} }, /* raw spd data */
  127. {0}, /* timing parameters */
  128. { {0} }, /* electrical configuration */
  129. {0,}, /* electrical parameters */
  130. 0x3, /* clock enable mask */
  131. };
  132. struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
  133. {
  134. struct if_params *ifp = &board_topology_map.interface_params[0];
  135. cf_read_tlv_data();
  136. switch (cf_tlv_data.ram_size) {
  137. case 4:
  138. default:
  139. ifp->memory_size = MV_DDR_DIE_CAP_4GBIT;
  140. break;
  141. case 8:
  142. ifp->memory_size = MV_DDR_DIE_CAP_8GBIT;
  143. break;
  144. }
  145. /* Return the board topology as defined in the board code */
  146. return &board_topology_map;
  147. }
  148. int board_early_init_f(void)
  149. {
  150. /* Configure MPP */
  151. writel(0x11111111, MVEBU_MPP_BASE + 0x00);
  152. writel(0x11111111, MVEBU_MPP_BASE + 0x04);
  153. writel(0x10400011, MVEBU_MPP_BASE + 0x08);
  154. writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
  155. writel(0x44400002, MVEBU_MPP_BASE + 0x10);
  156. writel(0x41144004, MVEBU_MPP_BASE + 0x14);
  157. writel(0x40333333, MVEBU_MPP_BASE + 0x18);
  158. writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
  159. /* Set GPP Out value */
  160. writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
  161. writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
  162. /* Set GPP Polarity */
  163. writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
  164. writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
  165. /* Set GPP Out Enable */
  166. writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
  167. writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
  168. return 0;
  169. }
  170. int board_init(void)
  171. {
  172. /* Address of boot parameters */
  173. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  174. /* Toggle GPIO41 to reset onboard switch and phy */
  175. clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
  176. clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9));
  177. /* GPIO 19 on ClearFog rev 2.1 controls the uSOM onboard phy reset */
  178. clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
  179. clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19));
  180. mdelay(1);
  181. setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
  182. setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
  183. mdelay(10);
  184. return 0;
  185. }
  186. int checkboard(void)
  187. {
  188. char *board = "Clearfog Pro";
  189. if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE))
  190. board = "Clearfog Base";
  191. cf_read_tlv_data();
  192. if (strlen(cf_tlv_data.tlv_product_name[0]) > 0)
  193. board = cf_tlv_data.tlv_product_name[0];
  194. printf("Board: SolidRun %s", board);
  195. if (strlen(cf_tlv_data.tlv_product_name[1]) > 0)
  196. printf(", %s", cf_tlv_data.tlv_product_name[1]);
  197. puts("\n");
  198. return 0;
  199. }
  200. int board_eth_init(struct bd_info *bis)
  201. {
  202. cpu_eth_init(bis); /* Built in controller(s) come first */
  203. return pci_eth_init(bis);
  204. }
  205. int board_late_init(void)
  206. {
  207. if (env_get("fdtfile"))
  208. return 0;
  209. cf_read_tlv_data();
  210. if (sr_product_is(&cf_tlv_data, "Clearfog Base"))
  211. env_set("fdtfile", "armada-388-clearfog-base.dtb");
  212. else if (sr_product_is(&cf_tlv_data, "Clearfog GTR S4"))
  213. env_set("fdtfile", "armada-385-clearfog-gtr-s4.dtb");
  214. else if (sr_product_is(&cf_tlv_data, "Clearfog GTR L8"))
  215. env_set("fdtfile", "armada-385-clearfog-gtr-l8.dtb");
  216. else if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE))
  217. env_set("fdtfile", "armada-388-clearfog-base.dtb");
  218. else
  219. env_set("fdtfile", "armada-388-clearfog-pro.dtb");
  220. return 0;
  221. }