adp-ag101p.h 9.2 KB

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  1. /*
  2. * Copyright (C) 2011 Andes Technology Corporation
  3. * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
  4. * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #ifndef __CONFIG_H
  9. #define __CONFIG_H
  10. #include <asm/arch-ag101/ag101.h>
  11. /*
  12. * CPU and Board Configuration Options
  13. */
  14. #define CONFIG_USE_INTERRUPT
  15. #define CONFIG_SKIP_LOWLEVEL_INIT
  16. #define CONFIG_CMDLINE_EDITING
  17. #define CONFIG_ARCH_MAP_SYSMEM
  18. #define CONFIG_BOOTP_SEND_HOSTNAME
  19. #define CONFIG_BOOTP_SERVERIP
  20. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  21. #define CONFIG_MEM_REMAP
  22. #endif
  23. #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  24. #define CONFIG_SYS_TEXT_BASE 0x00500000
  25. #ifdef CONFIG_OF_CONTROL
  26. #undef CONFIG_OF_SEPARATE
  27. #define CONFIG_OF_EMBED
  28. #endif
  29. #else
  30. #ifdef CONFIG_MEM_REMAP
  31. #define CONFIG_SYS_TEXT_BASE 0x80000000
  32. #else
  33. #define CONFIG_SYS_TEXT_BASE 0x00000000
  34. #endif
  35. #endif
  36. /*
  37. * Timer
  38. */
  39. #define CONFIG_SYS_CLK_FREQ 39062500
  40. #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
  41. /*
  42. * Use Externel CLOCK or PCLK
  43. */
  44. #undef CONFIG_FTRTC010_EXTCLK
  45. #ifndef CONFIG_FTRTC010_EXTCLK
  46. #define CONFIG_FTRTC010_PCLK
  47. #endif
  48. #ifdef CONFIG_FTRTC010_EXTCLK
  49. #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
  50. #else
  51. #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
  52. #endif
  53. #define TIMER_LOAD_VAL 0xffffffff
  54. /*
  55. * Real Time Clock
  56. */
  57. #define CONFIG_RTC_FTRTC010
  58. /*
  59. * Real Time Clock Divider
  60. * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
  61. */
  62. #define OSC_5MHZ (5*1000000)
  63. #define OSC_CLK (4*OSC_5MHZ)
  64. #define RTC_DIV_COUNT (0.5) /* Why?? */
  65. /*
  66. * Serial console configuration
  67. */
  68. /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
  69. #define CONFIG_CONS_INDEX 1
  70. #define CONFIG_SYS_NS16550_SERIAL
  71. #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
  72. #ifndef CONFIG_DM_SERIAL
  73. #define CONFIG_SYS_NS16550_REG_SIZE -4
  74. #endif
  75. #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
  76. /*
  77. * SD (MMC) controller
  78. */
  79. #define CONFIG_FTSDC010_NUMBER 1
  80. #define CONFIG_FTSDC010_SDIO
  81. /*
  82. * Miscellaneous configurable options
  83. */
  84. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  85. /*
  86. * Size of malloc() pool
  87. */
  88. /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
  89. #define CONFIG_SYS_MALLOC_LEN (512 << 10)
  90. /*
  91. * AHB Controller configuration
  92. */
  93. #define CONFIG_FTAHBC020S
  94. #ifdef CONFIG_FTAHBC020S
  95. #include <faraday/ftahbc020s.h>
  96. /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
  97. #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
  98. /*
  99. * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
  100. * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
  101. * in C language.
  102. */
  103. #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
  104. (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
  105. FTAHBC020S_SLAVE_BSR_SIZE(0xb))
  106. #endif
  107. /*
  108. * Watchdog
  109. */
  110. #define CONFIG_FTWDT010_WATCHDOG
  111. /*
  112. * PMU Power controller configuration
  113. */
  114. #define CONFIG_PMU
  115. #define CONFIG_FTPMU010_POWER
  116. #ifdef CONFIG_FTPMU010_POWER
  117. #include <faraday/ftpmu010.h>
  118. #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E
  119. #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \
  120. FTPMU010_SDRAMHTC_EBIDATA_DCSR | \
  121. FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \
  122. FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
  123. FTPMU010_SDRAMHTC_CKE_DCSR | \
  124. FTPMU010_SDRAMHTC_DQM_DCSR | \
  125. FTPMU010_SDRAMHTC_SDCLK_DCSR)
  126. #endif
  127. /*
  128. * SDRAM controller configuration
  129. */
  130. #define CONFIG_FTSDMC021
  131. #ifdef CONFIG_FTSDMC021
  132. #include <faraday/ftsdmc021.h>
  133. #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \
  134. FTSDMC021_TP1_TRP(1) | \
  135. FTSDMC021_TP1_TRCD(1) | \
  136. FTSDMC021_TP1_TRF(3) | \
  137. FTSDMC021_TP1_TWR(1) | \
  138. FTSDMC021_TP1_TCL(2))
  139. #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \
  140. FTSDMC021_TP2_INI_REFT(8) | \
  141. FTSDMC021_TP2_REF_INTV(0x180))
  142. /*
  143. * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
  144. * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
  145. * C language.
  146. */
  147. #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \
  148. FTSDMC021_CR1_DSZ(3) | \
  149. FTSDMC021_CR1_MBW(2) | \
  150. FTSDMC021_CR1_BNKSIZE(6))
  151. #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \
  152. FTSDMC021_CR2_IREF | \
  153. FTSDMC021_CR2_ISMR)
  154. #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
  155. #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \
  156. CONFIG_SYS_FTSDMC021_BANK0_BASE)
  157. #define CONFIG_SYS_FTSDMC021_BANK1_BASE \
  158. (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
  159. #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \
  160. CONFIG_SYS_FTSDMC021_BANK1_BASE)
  161. #endif
  162. /*
  163. * Physical Memory Map
  164. */
  165. #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  166. #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
  167. #else
  168. #ifdef CONFIG_MEM_REMAP
  169. #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
  170. #else
  171. #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */
  172. #endif
  173. #endif
  174. #define PHYS_SDRAM_1 \
  175. (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
  176. #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */
  177. #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  178. #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
  179. #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
  180. #else
  181. #ifdef CONFIG_MEM_REMAP
  182. #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
  183. #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
  184. #else
  185. #define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */
  186. #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
  187. #endif
  188. #endif
  189. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
  190. #ifdef CONFIG_MEM_REMAP
  191. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
  192. GENERATED_GBL_DATA_SIZE)
  193. #else
  194. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
  195. GENERATED_GBL_DATA_SIZE)
  196. #endif /* CONFIG_MEM_REMAP */
  197. /*
  198. * Load address and memory test area should agree with
  199. * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
  200. */
  201. #define CONFIG_SYS_LOAD_ADDR 0x300000
  202. /* memtest works on 63 MB in DRAM */
  203. #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
  204. #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
  205. /*
  206. * Static memory controller configuration
  207. */
  208. #define CONFIG_FTSMC020
  209. #ifdef CONFIG_FTSMC020
  210. #include <faraday/ftsmc020.h>
  211. #define CONFIG_SYS_FTSMC020_CONFIGS { \
  212. { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
  213. { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
  214. }
  215. #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
  216. #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
  217. FTSMC020_BANK_SIZE_32M | \
  218. FTSMC020_BANK_MBW_32)
  219. #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
  220. FTSMC020_TPR_AST(1) | \
  221. FTSMC020_TPR_CTW(1) | \
  222. FTSMC020_TPR_ATI(1) | \
  223. FTSMC020_TPR_AT2(1) | \
  224. FTSMC020_TPR_WTC(1) | \
  225. FTSMC020_TPR_AHT(1) | \
  226. FTSMC020_TPR_TRNA(1))
  227. #endif
  228. /*
  229. * FLASH on ADP_AG101P is connected to BANK0
  230. * Just disalbe the other BANK to avoid detection error.
  231. */
  232. #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
  233. FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
  234. FTSMC020_BANK_SIZE_32M | \
  235. FTSMC020_BANK_MBW_32)
  236. #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
  237. FTSMC020_TPR_CTW(3) | \
  238. FTSMC020_TPR_ATI(0xf) | \
  239. FTSMC020_TPR_AT2(3) | \
  240. FTSMC020_TPR_WTC(3) | \
  241. FTSMC020_TPR_AHT(3) | \
  242. FTSMC020_TPR_TRNA(0xf))
  243. #define FTSMC020_BANK1_CONFIG (0x00)
  244. #define FTSMC020_BANK1_TIMING (0x00)
  245. #endif /* CONFIG_FTSMC020 */
  246. /*
  247. * FLASH and environment organization
  248. */
  249. /* use CFI framework */
  250. #define CONFIG_SYS_FLASH_CFI
  251. #define CONFIG_FLASH_CFI_DRIVER
  252. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  253. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  254. #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
  255. /* support JEDEC */
  256. /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
  257. #ifdef CONFIG_SKIP_LOWLEVEL_INIT
  258. #define PHYS_FLASH_1 0x80000000 /* BANK 0 */
  259. #else
  260. #ifdef CONFIG_MEM_REMAP
  261. #define PHYS_FLASH_1 0x80000000 /* BANK 0 */
  262. #else
  263. #define PHYS_FLASH_1 0x00000000 /* BANK 0 */
  264. #endif
  265. #endif /* CONFIG_MEM_REMAP */
  266. #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
  267. #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
  268. #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
  269. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
  270. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
  271. /* max number of memory banks */
  272. /*
  273. * There are 4 banks supported for this Controller,
  274. * but we have only 1 bank connected to flash on board
  275. */
  276. #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
  277. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  278. #endif
  279. #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
  280. /* max number of sectors on one chip */
  281. #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
  282. #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE
  283. #define CONFIG_SYS_MAX_FLASH_SECT 512
  284. /* environments */
  285. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000)
  286. #define CONFIG_ENV_SIZE 8192
  287. #define CONFIG_ENV_OVERWRITE
  288. /*
  289. * For booting Linux, the board info and command line data
  290. * have to be in the first 16 MB of memory, since this is
  291. * the maximum mapped by the Linux kernel during initialization.
  292. */
  293. /* Initial Memory map for Linux*/
  294. #define CONFIG_SYS_BOOTMAPSZ (64 << 20)
  295. /* Increase max gunzip size */
  296. #define CONFIG_SYS_BOOTM_LEN (64 << 20)
  297. #endif /* __CONFIG_H */