sun8i_emac.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016
  4. * Author: Amit Singh Tomar, amittomer25@gmail.com
  5. *
  6. * Ethernet driver for H3/A64/A83T based SoC's
  7. *
  8. * It is derived from the work done by
  9. * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
  10. *
  11. */
  12. #include <asm/io.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/gpio.h>
  15. #include <common.h>
  16. #include <dm.h>
  17. #include <fdt_support.h>
  18. #include <linux/err.h>
  19. #include <malloc.h>
  20. #include <miiphy.h>
  21. #include <net.h>
  22. #include <dt-bindings/pinctrl/sun4i-a10.h>
  23. #ifdef CONFIG_DM_GPIO
  24. #include <asm-generic/gpio.h>
  25. #endif
  26. #define MDIO_CMD_MII_BUSY BIT(0)
  27. #define MDIO_CMD_MII_WRITE BIT(1)
  28. #define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0
  29. #define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
  30. #define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000
  31. #define MDIO_CMD_MII_PHY_ADDR_SHIFT 12
  32. #define CONFIG_TX_DESCR_NUM 32
  33. #define CONFIG_RX_DESCR_NUM 32
  34. #define CONFIG_ETH_BUFSIZE 2048 /* Note must be dma aligned */
  35. /*
  36. * The datasheet says that each descriptor can transfers up to 4096 bytes
  37. * But later, the register documentation reduces that value to 2048,
  38. * using 2048 cause strange behaviours and even BSP driver use 2047
  39. */
  40. #define CONFIG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */
  41. #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
  42. #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
  43. #define H3_EPHY_DEFAULT_VALUE 0x58000
  44. #define H3_EPHY_DEFAULT_MASK GENMASK(31, 15)
  45. #define H3_EPHY_ADDR_SHIFT 20
  46. #define REG_PHY_ADDR_MASK GENMASK(4, 0)
  47. #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
  48. #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
  49. #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
  50. #define SC_RMII_EN BIT(13)
  51. #define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */
  52. #define SC_ETCS_MASK GENMASK(1, 0)
  53. #define SC_ETCS_EXT_GMII 0x1
  54. #define SC_ETCS_INT_GMII 0x2
  55. #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
  56. #define AHB_GATE_OFFSET_EPHY 0
  57. #if defined(CONFIG_MACH_SUNXI_H3_H5)
  58. #define SUN8I_GPD8_GMAC 2
  59. #else
  60. #define SUN8I_GPD8_GMAC 4
  61. #endif
  62. /* H3/A64 EMAC Register's offset */
  63. #define EMAC_CTL0 0x00
  64. #define EMAC_CTL1 0x04
  65. #define EMAC_INT_STA 0x08
  66. #define EMAC_INT_EN 0x0c
  67. #define EMAC_TX_CTL0 0x10
  68. #define EMAC_TX_CTL1 0x14
  69. #define EMAC_TX_FLOW_CTL 0x1c
  70. #define EMAC_TX_DMA_DESC 0x20
  71. #define EMAC_RX_CTL0 0x24
  72. #define EMAC_RX_CTL1 0x28
  73. #define EMAC_RX_DMA_DESC 0x34
  74. #define EMAC_MII_CMD 0x48
  75. #define EMAC_MII_DATA 0x4c
  76. #define EMAC_ADDR0_HIGH 0x50
  77. #define EMAC_ADDR0_LOW 0x54
  78. #define EMAC_TX_DMA_STA 0xb0
  79. #define EMAC_TX_CUR_DESC 0xb4
  80. #define EMAC_TX_CUR_BUF 0xb8
  81. #define EMAC_RX_DMA_STA 0xc0
  82. #define EMAC_RX_CUR_DESC 0xc4
  83. DECLARE_GLOBAL_DATA_PTR;
  84. enum emac_variant {
  85. A83T_EMAC = 1,
  86. H3_EMAC,
  87. A64_EMAC,
  88. };
  89. struct emac_dma_desc {
  90. u32 status;
  91. u32 st;
  92. u32 buf_addr;
  93. u32 next;
  94. } __aligned(ARCH_DMA_MINALIGN);
  95. struct emac_eth_dev {
  96. struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
  97. struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
  98. char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
  99. char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
  100. u32 interface;
  101. u32 phyaddr;
  102. u32 link;
  103. u32 speed;
  104. u32 duplex;
  105. u32 phy_configured;
  106. u32 tx_currdescnum;
  107. u32 rx_currdescnum;
  108. u32 addr;
  109. u32 tx_slot;
  110. bool use_internal_phy;
  111. enum emac_variant variant;
  112. void *mac_reg;
  113. phys_addr_t sysctl_reg;
  114. struct phy_device *phydev;
  115. struct mii_dev *bus;
  116. #ifdef CONFIG_DM_GPIO
  117. struct gpio_desc reset_gpio;
  118. #endif
  119. };
  120. struct sun8i_eth_pdata {
  121. struct eth_pdata eth_pdata;
  122. u32 reset_delays[3];
  123. };
  124. static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  125. {
  126. struct udevice *dev = bus->priv;
  127. struct emac_eth_dev *priv = dev_get_priv(dev);
  128. ulong start;
  129. u32 miiaddr = 0;
  130. int timeout = CONFIG_MDIO_TIMEOUT;
  131. miiaddr &= ~MDIO_CMD_MII_WRITE;
  132. miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
  133. miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
  134. MDIO_CMD_MII_PHY_REG_ADDR_MASK;
  135. miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
  136. miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
  137. MDIO_CMD_MII_PHY_ADDR_MASK;
  138. miiaddr |= MDIO_CMD_MII_BUSY;
  139. writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
  140. start = get_timer(0);
  141. while (get_timer(start) < timeout) {
  142. if (!(readl(priv->mac_reg + EMAC_MII_CMD) & MDIO_CMD_MII_BUSY))
  143. return readl(priv->mac_reg + EMAC_MII_DATA);
  144. udelay(10);
  145. };
  146. return -1;
  147. }
  148. static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  149. u16 val)
  150. {
  151. struct udevice *dev = bus->priv;
  152. struct emac_eth_dev *priv = dev_get_priv(dev);
  153. ulong start;
  154. u32 miiaddr = 0;
  155. int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
  156. miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
  157. miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
  158. MDIO_CMD_MII_PHY_REG_ADDR_MASK;
  159. miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
  160. miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
  161. MDIO_CMD_MII_PHY_ADDR_MASK;
  162. miiaddr |= MDIO_CMD_MII_WRITE;
  163. miiaddr |= MDIO_CMD_MII_BUSY;
  164. writel(val, priv->mac_reg + EMAC_MII_DATA);
  165. writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
  166. start = get_timer(0);
  167. while (get_timer(start) < timeout) {
  168. if (!(readl(priv->mac_reg + EMAC_MII_CMD) &
  169. MDIO_CMD_MII_BUSY)) {
  170. ret = 0;
  171. break;
  172. }
  173. udelay(10);
  174. };
  175. return ret;
  176. }
  177. static int _sun8i_write_hwaddr(struct emac_eth_dev *priv, u8 *mac_id)
  178. {
  179. u32 macid_lo, macid_hi;
  180. macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
  181. (mac_id[3] << 24);
  182. macid_hi = mac_id[4] + (mac_id[5] << 8);
  183. writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH);
  184. writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW);
  185. return 0;
  186. }
  187. static void sun8i_adjust_link(struct emac_eth_dev *priv,
  188. struct phy_device *phydev)
  189. {
  190. u32 v;
  191. v = readl(priv->mac_reg + EMAC_CTL0);
  192. if (phydev->duplex)
  193. v |= BIT(0);
  194. else
  195. v &= ~BIT(0);
  196. v &= ~0x0C;
  197. switch (phydev->speed) {
  198. case 1000:
  199. break;
  200. case 100:
  201. v |= BIT(2);
  202. v |= BIT(3);
  203. break;
  204. case 10:
  205. v |= BIT(3);
  206. break;
  207. }
  208. writel(v, priv->mac_reg + EMAC_CTL0);
  209. }
  210. static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg)
  211. {
  212. if (priv->use_internal_phy) {
  213. /* H3 based SoC's that has an Internal 100MBit PHY
  214. * needs to be configured and powered up before use
  215. */
  216. *reg &= ~H3_EPHY_DEFAULT_MASK;
  217. *reg |= H3_EPHY_DEFAULT_VALUE;
  218. *reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
  219. *reg &= ~H3_EPHY_SHUTDOWN;
  220. *reg |= H3_EPHY_SELECT;
  221. } else
  222. /* This is to select External Gigabit PHY on
  223. * the boards with H3 SoC.
  224. */
  225. *reg &= ~H3_EPHY_SELECT;
  226. return 0;
  227. }
  228. static int sun8i_emac_set_syscon(struct emac_eth_dev *priv)
  229. {
  230. int ret;
  231. u32 reg;
  232. reg = readl(priv->sysctl_reg + 0x30);
  233. if (priv->variant == H3_EMAC) {
  234. ret = sun8i_emac_set_syscon_ephy(priv, &reg);
  235. if (ret)
  236. return ret;
  237. }
  238. reg &= ~(SC_ETCS_MASK | SC_EPIT);
  239. if (priv->variant == H3_EMAC || priv->variant == A64_EMAC)
  240. reg &= ~SC_RMII_EN;
  241. switch (priv->interface) {
  242. case PHY_INTERFACE_MODE_MII:
  243. /* default */
  244. break;
  245. case PHY_INTERFACE_MODE_RGMII:
  246. reg |= SC_EPIT | SC_ETCS_INT_GMII;
  247. break;
  248. case PHY_INTERFACE_MODE_RMII:
  249. if (priv->variant == H3_EMAC ||
  250. priv->variant == A64_EMAC) {
  251. reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
  252. break;
  253. }
  254. /* RMII not supported on A83T */
  255. default:
  256. debug("%s: Invalid PHY interface\n", __func__);
  257. return -EINVAL;
  258. }
  259. writel(reg, priv->sysctl_reg + 0x30);
  260. return 0;
  261. }
  262. static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev)
  263. {
  264. struct phy_device *phydev;
  265. phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
  266. if (!phydev)
  267. return -ENODEV;
  268. phy_connect_dev(phydev, dev);
  269. priv->phydev = phydev;
  270. phy_config(priv->phydev);
  271. return 0;
  272. }
  273. static void rx_descs_init(struct emac_eth_dev *priv)
  274. {
  275. struct emac_dma_desc *desc_table_p = &priv->rx_chain[0];
  276. char *rxbuffs = &priv->rxbuffer[0];
  277. struct emac_dma_desc *desc_p;
  278. u32 idx;
  279. /* flush Rx buffers */
  280. flush_dcache_range((uintptr_t)rxbuffs, (ulong)rxbuffs +
  281. RX_TOTAL_BUFSIZE);
  282. for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
  283. desc_p = &desc_table_p[idx];
  284. desc_p->buf_addr = (uintptr_t)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]
  285. ;
  286. desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
  287. desc_p->st |= CONFIG_ETH_RXSIZE;
  288. desc_p->status = BIT(31);
  289. }
  290. /* Correcting the last pointer of the chain */
  291. desc_p->next = (uintptr_t)&desc_table_p[0];
  292. flush_dcache_range((uintptr_t)priv->rx_chain,
  293. (uintptr_t)priv->rx_chain +
  294. sizeof(priv->rx_chain));
  295. writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));
  296. priv->rx_currdescnum = 0;
  297. }
  298. static void tx_descs_init(struct emac_eth_dev *priv)
  299. {
  300. struct emac_dma_desc *desc_table_p = &priv->tx_chain[0];
  301. char *txbuffs = &priv->txbuffer[0];
  302. struct emac_dma_desc *desc_p;
  303. u32 idx;
  304. for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
  305. desc_p = &desc_table_p[idx];
  306. desc_p->buf_addr = (uintptr_t)&txbuffs[idx * CONFIG_ETH_BUFSIZE]
  307. ;
  308. desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
  309. desc_p->status = (1 << 31);
  310. desc_p->st = 0;
  311. }
  312. /* Correcting the last pointer of the chain */
  313. desc_p->next = (uintptr_t)&desc_table_p[0];
  314. /* Flush all Tx buffer descriptors */
  315. flush_dcache_range((uintptr_t)priv->tx_chain,
  316. (uintptr_t)priv->tx_chain +
  317. sizeof(priv->tx_chain));
  318. writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);
  319. priv->tx_currdescnum = 0;
  320. }
  321. static int _sun8i_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
  322. {
  323. u32 reg, v;
  324. int timeout = 100;
  325. reg = readl((priv->mac_reg + EMAC_CTL1));
  326. if (!(reg & 0x1)) {
  327. /* Soft reset MAC */
  328. setbits_le32((priv->mac_reg + EMAC_CTL1), 0x1);
  329. do {
  330. reg = readl(priv->mac_reg + EMAC_CTL1);
  331. } while ((reg & 0x01) != 0 && (--timeout));
  332. if (!timeout) {
  333. printf("%s: Timeout\n", __func__);
  334. return -1;
  335. }
  336. }
  337. /* Rewrite mac address after reset */
  338. _sun8i_write_hwaddr(priv, enetaddr);
  339. v = readl(priv->mac_reg + EMAC_TX_CTL1);
  340. /* TX_MD Transmission starts after a full frame located in TX DMA FIFO*/
  341. v |= BIT(1);
  342. writel(v, priv->mac_reg + EMAC_TX_CTL1);
  343. v = readl(priv->mac_reg + EMAC_RX_CTL1);
  344. /* RX_MD RX DMA reads data from RX DMA FIFO to host memory after a
  345. * complete frame has been written to RX DMA FIFO
  346. */
  347. v |= BIT(1);
  348. writel(v, priv->mac_reg + EMAC_RX_CTL1);
  349. /* DMA */
  350. writel(8 << 24, priv->mac_reg + EMAC_CTL1);
  351. /* Initialize rx/tx descriptors */
  352. rx_descs_init(priv);
  353. tx_descs_init(priv);
  354. /* PHY Start Up */
  355. phy_startup(priv->phydev);
  356. sun8i_adjust_link(priv, priv->phydev);
  357. /* Start RX DMA */
  358. v = readl(priv->mac_reg + EMAC_RX_CTL1);
  359. v |= BIT(30);
  360. writel(v, priv->mac_reg + EMAC_RX_CTL1);
  361. /* Start TX DMA */
  362. v = readl(priv->mac_reg + EMAC_TX_CTL1);
  363. v |= BIT(30);
  364. writel(v, priv->mac_reg + EMAC_TX_CTL1);
  365. /* Enable RX/TX */
  366. setbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
  367. setbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
  368. return 0;
  369. }
  370. static int parse_phy_pins(struct udevice *dev)
  371. {
  372. int offset;
  373. const char *pin_name;
  374. int drive, pull = SUN4I_PINCTRL_NO_PULL, i;
  375. offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
  376. "pinctrl-0");
  377. if (offset < 0) {
  378. printf("WARNING: emac: cannot find pinctrl-0 node\n");
  379. return offset;
  380. }
  381. drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
  382. "drive-strength", ~0);
  383. if (drive != ~0) {
  384. if (drive <= 10)
  385. drive = SUN4I_PINCTRL_10_MA;
  386. else if (drive <= 20)
  387. drive = SUN4I_PINCTRL_20_MA;
  388. else if (drive <= 30)
  389. drive = SUN4I_PINCTRL_30_MA;
  390. else
  391. drive = SUN4I_PINCTRL_40_MA;
  392. }
  393. if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL))
  394. pull = SUN4I_PINCTRL_PULL_UP;
  395. else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL))
  396. pull = SUN4I_PINCTRL_PULL_DOWN;
  397. for (i = 0; ; i++) {
  398. int pin;
  399. pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
  400. "pins", i, NULL);
  401. if (!pin_name)
  402. break;
  403. pin = sunxi_name_to_gpio(pin_name);
  404. if (pin < 0)
  405. continue;
  406. sunxi_gpio_set_cfgpin(pin, SUN8I_GPD8_GMAC);
  407. if (drive != ~0)
  408. sunxi_gpio_set_drv(pin, drive);
  409. if (pull != ~0)
  410. sunxi_gpio_set_pull(pin, pull);
  411. }
  412. if (!i) {
  413. printf("WARNING: emac: cannot find pins property\n");
  414. return -2;
  415. }
  416. return 0;
  417. }
  418. static int _sun8i_eth_recv(struct emac_eth_dev *priv, uchar **packetp)
  419. {
  420. u32 status, desc_num = priv->rx_currdescnum;
  421. struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
  422. int length = -EAGAIN;
  423. int good_packet = 1;
  424. uintptr_t desc_start = (uintptr_t)desc_p;
  425. uintptr_t desc_end = desc_start +
  426. roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
  427. ulong data_start = (uintptr_t)desc_p->buf_addr;
  428. ulong data_end;
  429. /* Invalidate entire buffer descriptor */
  430. invalidate_dcache_range(desc_start, desc_end);
  431. status = desc_p->status;
  432. /* Check for DMA own bit */
  433. if (!(status & BIT(31))) {
  434. length = (desc_p->status >> 16) & 0x3FFF;
  435. if (length < 0x40) {
  436. good_packet = 0;
  437. debug("RX: Bad Packet (runt)\n");
  438. }
  439. data_end = data_start + length;
  440. /* Invalidate received data */
  441. invalidate_dcache_range(rounddown(data_start,
  442. ARCH_DMA_MINALIGN),
  443. roundup(data_end,
  444. ARCH_DMA_MINALIGN));
  445. if (good_packet) {
  446. if (length > CONFIG_ETH_RXSIZE) {
  447. printf("Received packet is too big (len=%d)\n",
  448. length);
  449. return -EMSGSIZE;
  450. }
  451. *packetp = (uchar *)(ulong)desc_p->buf_addr;
  452. return length;
  453. }
  454. }
  455. return length;
  456. }
  457. static int _sun8i_emac_eth_send(struct emac_eth_dev *priv, void *packet,
  458. int len)
  459. {
  460. u32 v, desc_num = priv->tx_currdescnum;
  461. struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
  462. uintptr_t desc_start = (uintptr_t)desc_p;
  463. uintptr_t desc_end = desc_start +
  464. roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
  465. uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
  466. uintptr_t data_end = data_start +
  467. roundup(len, ARCH_DMA_MINALIGN);
  468. /* Invalidate entire buffer descriptor */
  469. invalidate_dcache_range(desc_start, desc_end);
  470. desc_p->st = len;
  471. /* Mandatory undocumented bit */
  472. desc_p->st |= BIT(24);
  473. memcpy((void *)data_start, packet, len);
  474. /* Flush data to be sent */
  475. flush_dcache_range(data_start, data_end);
  476. /* frame end */
  477. desc_p->st |= BIT(30);
  478. desc_p->st |= BIT(31);
  479. /*frame begin */
  480. desc_p->st |= BIT(29);
  481. desc_p->status = BIT(31);
  482. /*Descriptors st and status field has changed, so FLUSH it */
  483. flush_dcache_range(desc_start, desc_end);
  484. /* Move to next Descriptor and wrap around */
  485. if (++desc_num >= CONFIG_TX_DESCR_NUM)
  486. desc_num = 0;
  487. priv->tx_currdescnum = desc_num;
  488. /* Start the DMA */
  489. v = readl(priv->mac_reg + EMAC_TX_CTL1);
  490. v |= BIT(31);/* mandatory */
  491. v |= BIT(30);/* mandatory */
  492. writel(v, priv->mac_reg + EMAC_TX_CTL1);
  493. return 0;
  494. }
  495. static int sun8i_eth_write_hwaddr(struct udevice *dev)
  496. {
  497. struct eth_pdata *pdata = dev_get_platdata(dev);
  498. struct emac_eth_dev *priv = dev_get_priv(dev);
  499. return _sun8i_write_hwaddr(priv, pdata->enetaddr);
  500. }
  501. static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
  502. {
  503. struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  504. #ifdef CONFIG_MACH_SUNXI_H3_H5
  505. /* Only H3/H5 have clock controls for internal EPHY */
  506. if (priv->use_internal_phy) {
  507. /* Set clock gating for ephy */
  508. setbits_le32(&ccm->bus_gate4, BIT(AHB_GATE_OFFSET_EPHY));
  509. /* Deassert EPHY */
  510. setbits_le32(&ccm->ahb_reset2_cfg, BIT(AHB_RESET_OFFSET_EPHY));
  511. }
  512. #endif
  513. /* Set clock gating for emac */
  514. setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
  515. /* De-assert EMAC */
  516. setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
  517. }
  518. #if defined(CONFIG_DM_GPIO)
  519. static int sun8i_mdio_reset(struct mii_dev *bus)
  520. {
  521. struct udevice *dev = bus->priv;
  522. struct emac_eth_dev *priv = dev_get_priv(dev);
  523. struct sun8i_eth_pdata *pdata = dev_get_platdata(dev);
  524. int ret;
  525. if (!dm_gpio_is_valid(&priv->reset_gpio))
  526. return 0;
  527. /* reset the phy */
  528. ret = dm_gpio_set_value(&priv->reset_gpio, 0);
  529. if (ret)
  530. return ret;
  531. udelay(pdata->reset_delays[0]);
  532. ret = dm_gpio_set_value(&priv->reset_gpio, 1);
  533. if (ret)
  534. return ret;
  535. udelay(pdata->reset_delays[1]);
  536. ret = dm_gpio_set_value(&priv->reset_gpio, 0);
  537. if (ret)
  538. return ret;
  539. udelay(pdata->reset_delays[2]);
  540. return 0;
  541. }
  542. #endif
  543. static int sun8i_mdio_init(const char *name, struct udevice *priv)
  544. {
  545. struct mii_dev *bus = mdio_alloc();
  546. if (!bus) {
  547. debug("Failed to allocate MDIO bus\n");
  548. return -ENOMEM;
  549. }
  550. bus->read = sun8i_mdio_read;
  551. bus->write = sun8i_mdio_write;
  552. snprintf(bus->name, sizeof(bus->name), name);
  553. bus->priv = (void *)priv;
  554. #if defined(CONFIG_DM_GPIO)
  555. bus->reset = sun8i_mdio_reset;
  556. #endif
  557. return mdio_register(bus);
  558. }
  559. static int sun8i_emac_eth_start(struct udevice *dev)
  560. {
  561. struct eth_pdata *pdata = dev_get_platdata(dev);
  562. return _sun8i_emac_eth_init(dev->priv, pdata->enetaddr);
  563. }
  564. static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
  565. {
  566. struct emac_eth_dev *priv = dev_get_priv(dev);
  567. return _sun8i_emac_eth_send(priv, packet, length);
  568. }
  569. static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  570. {
  571. struct emac_eth_dev *priv = dev_get_priv(dev);
  572. return _sun8i_eth_recv(priv, packetp);
  573. }
  574. static int _sun8i_free_pkt(struct emac_eth_dev *priv)
  575. {
  576. u32 desc_num = priv->rx_currdescnum;
  577. struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
  578. uintptr_t desc_start = (uintptr_t)desc_p;
  579. uintptr_t desc_end = desc_start +
  580. roundup(sizeof(u32), ARCH_DMA_MINALIGN);
  581. /* Make the current descriptor valid again */
  582. desc_p->status |= BIT(31);
  583. /* Flush Status field of descriptor */
  584. flush_dcache_range(desc_start, desc_end);
  585. /* Move to next desc and wrap-around condition. */
  586. if (++desc_num >= CONFIG_RX_DESCR_NUM)
  587. desc_num = 0;
  588. priv->rx_currdescnum = desc_num;
  589. return 0;
  590. }
  591. static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
  592. int length)
  593. {
  594. struct emac_eth_dev *priv = dev_get_priv(dev);
  595. return _sun8i_free_pkt(priv);
  596. }
  597. static void sun8i_emac_eth_stop(struct udevice *dev)
  598. {
  599. struct emac_eth_dev *priv = dev_get_priv(dev);
  600. /* Stop Rx/Tx transmitter */
  601. clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
  602. clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
  603. /* Stop TX DMA */
  604. clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, BIT(30));
  605. phy_shutdown(priv->phydev);
  606. }
  607. static int sun8i_emac_eth_probe(struct udevice *dev)
  608. {
  609. struct eth_pdata *pdata = dev_get_platdata(dev);
  610. struct emac_eth_dev *priv = dev_get_priv(dev);
  611. priv->mac_reg = (void *)pdata->iobase;
  612. sun8i_emac_board_setup(priv);
  613. sun8i_emac_set_syscon(priv);
  614. sun8i_mdio_init(dev->name, dev);
  615. priv->bus = miiphy_get_dev_by_name(dev->name);
  616. return sun8i_phy_init(priv, dev);
  617. }
  618. static const struct eth_ops sun8i_emac_eth_ops = {
  619. .start = sun8i_emac_eth_start,
  620. .write_hwaddr = sun8i_eth_write_hwaddr,
  621. .send = sun8i_emac_eth_send,
  622. .recv = sun8i_emac_eth_recv,
  623. .free_pkt = sun8i_eth_free_pkt,
  624. .stop = sun8i_emac_eth_stop,
  625. };
  626. static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
  627. {
  628. struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
  629. struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
  630. struct emac_eth_dev *priv = dev_get_priv(dev);
  631. const char *phy_mode;
  632. const fdt32_t *reg;
  633. int node = dev_of_offset(dev);
  634. int offset = 0;
  635. #ifdef CONFIG_DM_GPIO
  636. int reset_flags = GPIOD_IS_OUT;
  637. int ret = 0;
  638. #endif
  639. pdata->iobase = devfdt_get_addr(dev);
  640. if (pdata->iobase == FDT_ADDR_T_NONE) {
  641. debug("%s: Cannot find MAC base address\n", __func__);
  642. return -EINVAL;
  643. }
  644. offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
  645. if (offset < 0) {
  646. debug("%s: cannot find syscon node\n", __func__);
  647. return -EINVAL;
  648. }
  649. reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
  650. if (!reg) {
  651. debug("%s: cannot find reg property in syscon node\n",
  652. __func__);
  653. return -EINVAL;
  654. }
  655. priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
  656. offset, reg);
  657. if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
  658. debug("%s: Cannot find syscon base address\n", __func__);
  659. return -EINVAL;
  660. }
  661. pdata->phy_interface = -1;
  662. priv->phyaddr = -1;
  663. priv->use_internal_phy = false;
  664. offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
  665. if (offset < 0) {
  666. debug("%s: Cannot find PHY address\n", __func__);
  667. return -EINVAL;
  668. }
  669. priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
  670. phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
  671. if (phy_mode)
  672. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  673. printf("phy interface%d\n", pdata->phy_interface);
  674. if (pdata->phy_interface == -1) {
  675. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  676. return -EINVAL;
  677. }
  678. priv->variant = dev_get_driver_data(dev);
  679. if (!priv->variant) {
  680. printf("%s: Missing variant '%s'\n", __func__,
  681. (char *)priv->variant);
  682. return -EINVAL;
  683. }
  684. if (priv->variant == H3_EMAC) {
  685. int parent = fdt_parent_offset(gd->fdt_blob, offset);
  686. if (parent >= 0 &&
  687. !fdt_node_check_compatible(gd->fdt_blob, parent,
  688. "allwinner,sun8i-h3-mdio-internal"))
  689. priv->use_internal_phy = true;
  690. }
  691. priv->interface = pdata->phy_interface;
  692. if (!priv->use_internal_phy)
  693. parse_phy_pins(dev);
  694. #ifdef CONFIG_DM_GPIO
  695. if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
  696. "snps,reset-active-low"))
  697. reset_flags |= GPIOD_ACTIVE_LOW;
  698. ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
  699. &priv->reset_gpio, reset_flags);
  700. if (ret == 0) {
  701. ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
  702. "snps,reset-delays-us",
  703. sun8i_pdata->reset_delays, 3);
  704. } else if (ret == -ENOENT) {
  705. ret = 0;
  706. }
  707. #endif
  708. return 0;
  709. }
  710. static const struct udevice_id sun8i_emac_eth_ids[] = {
  711. {.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
  712. {.compatible = "allwinner,sun50i-a64-emac",
  713. .data = (uintptr_t)A64_EMAC },
  714. {.compatible = "allwinner,sun8i-a83t-emac",
  715. .data = (uintptr_t)A83T_EMAC },
  716. { }
  717. };
  718. U_BOOT_DRIVER(eth_sun8i_emac) = {
  719. .name = "eth_sun8i_emac",
  720. .id = UCLASS_ETH,
  721. .of_match = sun8i_emac_eth_ids,
  722. .ofdata_to_platdata = sun8i_emac_eth_ofdata_to_platdata,
  723. .probe = sun8i_emac_eth_probe,
  724. .ops = &sun8i_emac_eth_ops,
  725. .priv_auto_alloc_size = sizeof(struct emac_eth_dev),
  726. .platdata_auto_alloc_size = sizeof(struct sun8i_eth_pdata),
  727. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  728. };