sh_eth.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * sh_eth.h - Driver for Renesas SuperH ethernet controller.
  4. *
  5. * Copyright (C) 2008 - 2012 Renesas Solutions Corp.
  6. * Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu
  7. * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
  8. */
  9. #include <netdev.h>
  10. #include <asm/types.h>
  11. #define SHETHER_NAME "sh_eth"
  12. #if defined(CONFIG_SH)
  13. /* Malloc returns addresses in the P1 area (cacheable). However we need to
  14. use area P2 (non-cacheable) */
  15. #define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000))
  16. /* The ethernet controller needs to use physical addresses */
  17. #if defined(CONFIG_SH_32BIT)
  18. #define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) | 0x40000000))
  19. #else
  20. #define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000)
  21. #endif
  22. #elif defined(CONFIG_ARM)
  23. #ifndef inl
  24. #define inl readl
  25. #define outl writel
  26. #endif
  27. #define ADDR_TO_PHY(addr) ((int)(addr))
  28. #define ADDR_TO_P2(addr) (addr)
  29. #endif /* defined(CONFIG_SH) */
  30. /* base padding size is 16 */
  31. #ifndef CONFIG_SH_ETHER_ALIGNE_SIZE
  32. #define CONFIG_SH_ETHER_ALIGNE_SIZE 16
  33. #endif
  34. /* Number of supported ports */
  35. #define MAX_PORT_NUM 2
  36. /* Buffers must be big enough to hold the largest ethernet frame. Also, rx
  37. buffers must be a multiple of 32 bytes */
  38. #define MAX_BUF_SIZE (48 * 32)
  39. /* The number of tx descriptors must be large enough to point to 5 or more
  40. frames. If each frame uses 2 descriptors, at least 10 descriptors are needed.
  41. We use one descriptor per frame */
  42. #define NUM_TX_DESC 8
  43. /* The size of the tx descriptor is determined by how much padding is used.
  44. 4, 20, or 52 bytes of padding can be used */
  45. #define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
  46. /* Tx descriptor. We always use 3 bytes of padding */
  47. struct tx_desc_s {
  48. volatile u32 td0;
  49. u32 td1;
  50. u32 td2; /* Buffer start */
  51. u8 padding[TX_DESC_PADDING]; /* aligned cache line size */
  52. };
  53. /* There is no limitation in the number of rx descriptors */
  54. #define NUM_RX_DESC 8
  55. /* The size of the rx descriptor is determined by how much padding is used.
  56. 4, 20, or 52 bytes of padding can be used */
  57. #define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
  58. /* aligned cache line size */
  59. #define RX_BUF_ALIGNE_SIZE (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
  60. /* Rx descriptor. We always use 4 bytes of padding */
  61. struct rx_desc_s {
  62. volatile u32 rd0;
  63. volatile u32 rd1;
  64. u32 rd2; /* Buffer start */
  65. u8 padding[TX_DESC_PADDING]; /* aligned cache line size */
  66. };
  67. struct sh_eth_info {
  68. struct tx_desc_s *tx_desc_alloc;
  69. struct tx_desc_s *tx_desc_base;
  70. struct tx_desc_s *tx_desc_cur;
  71. struct rx_desc_s *rx_desc_alloc;
  72. struct rx_desc_s *rx_desc_base;
  73. struct rx_desc_s *rx_desc_cur;
  74. u8 *rx_buf_alloc;
  75. u8 *rx_buf_base;
  76. u8 mac_addr[6];
  77. u8 phy_addr;
  78. struct eth_device *dev;
  79. struct phy_device *phydev;
  80. void __iomem *iobase;
  81. };
  82. struct sh_eth_dev {
  83. int port;
  84. struct sh_eth_info port_info[MAX_PORT_NUM];
  85. };
  86. /* from linux/drivers/net/ethernet/renesas/sh_eth.h */
  87. enum {
  88. /* E-DMAC registers */
  89. EDSR = 0,
  90. EDMR,
  91. EDTRR,
  92. EDRRR,
  93. EESR,
  94. EESIPR,
  95. TDLAR,
  96. TDFAR,
  97. TDFXR,
  98. TDFFR,
  99. RDLAR,
  100. RDFAR,
  101. RDFXR,
  102. RDFFR,
  103. TRSCER,
  104. RMFCR,
  105. TFTR,
  106. FDR,
  107. RMCR,
  108. EDOCR,
  109. TFUCR,
  110. RFOCR,
  111. FCFTR,
  112. RPADIR,
  113. TRIMD,
  114. RBWAR,
  115. TBRAR,
  116. /* Ether registers */
  117. ECMR,
  118. ECSR,
  119. ECSIPR,
  120. PIR,
  121. PSR,
  122. RDMLR,
  123. PIPR,
  124. RFLR,
  125. IPGR,
  126. APR,
  127. MPR,
  128. PFTCR,
  129. PFRCR,
  130. RFCR,
  131. RFCF,
  132. TPAUSER,
  133. TPAUSECR,
  134. BCFR,
  135. BCFRR,
  136. GECMR,
  137. BCULR,
  138. MAHR,
  139. MALR,
  140. TROCR,
  141. CDCR,
  142. LCCR,
  143. CNDCR,
  144. CEFCR,
  145. FRECR,
  146. TSFRCR,
  147. TLFRCR,
  148. CERCR,
  149. CEECR,
  150. RMIIMR, /* R8A7790 */
  151. MAFCR,
  152. RTRATE,
  153. CSMR,
  154. RMII_MII,
  155. /* This value must be written at last. */
  156. SH_ETH_MAX_REGISTER_OFFSET,
  157. };
  158. static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  159. [EDSR] = 0x0000,
  160. [EDMR] = 0x0400,
  161. [EDTRR] = 0x0408,
  162. [EDRRR] = 0x0410,
  163. [EESR] = 0x0428,
  164. [EESIPR] = 0x0430,
  165. [TDLAR] = 0x0010,
  166. [TDFAR] = 0x0014,
  167. [TDFXR] = 0x0018,
  168. [TDFFR] = 0x001c,
  169. [RDLAR] = 0x0030,
  170. [RDFAR] = 0x0034,
  171. [RDFXR] = 0x0038,
  172. [RDFFR] = 0x003c,
  173. [TRSCER] = 0x0438,
  174. [RMFCR] = 0x0440,
  175. [TFTR] = 0x0448,
  176. [FDR] = 0x0450,
  177. [RMCR] = 0x0458,
  178. [RPADIR] = 0x0460,
  179. [FCFTR] = 0x0468,
  180. [CSMR] = 0x04E4,
  181. [ECMR] = 0x0500,
  182. [ECSR] = 0x0510,
  183. [ECSIPR] = 0x0518,
  184. [PIR] = 0x0520,
  185. [PSR] = 0x0528,
  186. [PIPR] = 0x052c,
  187. [RFLR] = 0x0508,
  188. [APR] = 0x0554,
  189. [MPR] = 0x0558,
  190. [PFTCR] = 0x055c,
  191. [PFRCR] = 0x0560,
  192. [TPAUSER] = 0x0564,
  193. [GECMR] = 0x05b0,
  194. [BCULR] = 0x05b4,
  195. [MAHR] = 0x05c0,
  196. [MALR] = 0x05c8,
  197. [TROCR] = 0x0700,
  198. [CDCR] = 0x0708,
  199. [LCCR] = 0x0710,
  200. [CEFCR] = 0x0740,
  201. [FRECR] = 0x0748,
  202. [TSFRCR] = 0x0750,
  203. [TLFRCR] = 0x0758,
  204. [RFCR] = 0x0760,
  205. [CERCR] = 0x0768,
  206. [CEECR] = 0x0770,
  207. [MAFCR] = 0x0778,
  208. [RMII_MII] = 0x0790,
  209. };
  210. static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
  211. [ECMR] = 0x0100,
  212. [RFLR] = 0x0108,
  213. [ECSR] = 0x0110,
  214. [ECSIPR] = 0x0118,
  215. [PIR] = 0x0120,
  216. [PSR] = 0x0128,
  217. [RDMLR] = 0x0140,
  218. [IPGR] = 0x0150,
  219. [APR] = 0x0154,
  220. [MPR] = 0x0158,
  221. [TPAUSER] = 0x0164,
  222. [RFCF] = 0x0160,
  223. [TPAUSECR] = 0x0168,
  224. [BCFRR] = 0x016c,
  225. [MAHR] = 0x01c0,
  226. [MALR] = 0x01c8,
  227. [TROCR] = 0x01d0,
  228. [CDCR] = 0x01d4,
  229. [LCCR] = 0x01d8,
  230. [CNDCR] = 0x01dc,
  231. [CEFCR] = 0x01e4,
  232. [FRECR] = 0x01e8,
  233. [TSFRCR] = 0x01ec,
  234. [TLFRCR] = 0x01f0,
  235. [RFCR] = 0x01f4,
  236. [MAFCR] = 0x01f8,
  237. [RTRATE] = 0x01fc,
  238. [EDMR] = 0x0000,
  239. [EDTRR] = 0x0008,
  240. [EDRRR] = 0x0010,
  241. [TDLAR] = 0x0018,
  242. [RDLAR] = 0x0020,
  243. [EESR] = 0x0028,
  244. [EESIPR] = 0x0030,
  245. [TRSCER] = 0x0038,
  246. [RMFCR] = 0x0040,
  247. [TFTR] = 0x0048,
  248. [FDR] = 0x0050,
  249. [RMCR] = 0x0058,
  250. [TFUCR] = 0x0064,
  251. [RFOCR] = 0x0068,
  252. [RMIIMR] = 0x006C,
  253. [FCFTR] = 0x0070,
  254. [RPADIR] = 0x0078,
  255. [TRIMD] = 0x007c,
  256. [RBWAR] = 0x00c8,
  257. [RDFAR] = 0x00cc,
  258. [TBRAR] = 0x00d4,
  259. [TDFAR] = 0x00d8,
  260. };
  261. /* Register Address */
  262. #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
  263. #define SH_ETH_TYPE_GETHER
  264. #define BASE_IO_ADDR 0xfee00000
  265. #elif defined(CONFIG_CPU_SH7757) || \
  266. defined(CONFIG_CPU_SH7752) || \
  267. defined(CONFIG_CPU_SH7753)
  268. #if defined(CONFIG_SH_ETHER_USE_GETHER)
  269. #define SH_ETH_TYPE_GETHER
  270. #define BASE_IO_ADDR 0xfee00000
  271. #else
  272. #define SH_ETH_TYPE_ETHER
  273. #define BASE_IO_ADDR 0xfef00000
  274. #endif
  275. #elif defined(CONFIG_CPU_SH7724)
  276. #define SH_ETH_TYPE_ETHER
  277. #define BASE_IO_ADDR 0xA4600000
  278. #elif defined(CONFIG_R8A7740)
  279. #define SH_ETH_TYPE_GETHER
  280. #define BASE_IO_ADDR 0xE9A00000
  281. #elif defined(CONFIG_RCAR_GEN2)
  282. #define SH_ETH_TYPE_ETHER
  283. #define BASE_IO_ADDR 0xEE700200
  284. #elif defined(CONFIG_R7S72100)
  285. #define SH_ETH_TYPE_RZ
  286. #define BASE_IO_ADDR 0xE8203000
  287. #endif
  288. /*
  289. * Register's bits
  290. * Copy from Linux driver source code
  291. */
  292. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  293. /* EDSR */
  294. enum EDSR_BIT {
  295. EDSR_ENT = 0x01, EDSR_ENR = 0x02,
  296. };
  297. #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
  298. #endif
  299. /* EDMR */
  300. enum DMAC_M_BIT {
  301. EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
  302. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  303. EDMR_SRST = 0x03, /* Receive/Send reset */
  304. EMDR_DESC_R = 0x30, /* Descriptor reserve size */
  305. EDMR_EL = 0x40, /* Litte endian */
  306. #elif defined(SH_ETH_TYPE_ETHER)
  307. EDMR_SRST = 0x01,
  308. EMDR_DESC_R = 0x30, /* Descriptor reserve size */
  309. EDMR_EL = 0x40, /* Litte endian */
  310. #else
  311. EDMR_SRST = 0x01,
  312. #endif
  313. };
  314. #if CONFIG_SH_ETHER_ALIGNE_SIZE == 64
  315. # define EMDR_DESC EDMR_DL1
  316. #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32
  317. # define EMDR_DESC EDMR_DL0
  318. #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
  319. # define EMDR_DESC 0
  320. #endif
  321. /* RFLR */
  322. #define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */
  323. /* EDTRR */
  324. enum DMAC_T_BIT {
  325. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  326. EDTRR_TRNS = 0x03,
  327. #else
  328. EDTRR_TRNS = 0x01,
  329. #endif
  330. };
  331. /* GECMR */
  332. enum GECMR_BIT {
  333. #if defined(CONFIG_CPU_SH7757) || \
  334. defined(CONFIG_CPU_SH7752) || \
  335. defined(CONFIG_CPU_SH7753)
  336. GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00,
  337. #else
  338. GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
  339. #endif
  340. };
  341. /* EDRRR*/
  342. enum EDRRR_R_BIT {
  343. EDRRR_R = 0x01,
  344. };
  345. /* TPAUSER */
  346. enum TPAUSER_BIT {
  347. TPAUSER_TPAUSE = 0x0000ffff,
  348. TPAUSER_UNLIMITED = 0,
  349. };
  350. /* BCFR */
  351. enum BCFR_BIT {
  352. BCFR_RPAUSE = 0x0000ffff,
  353. BCFR_UNLIMITED = 0,
  354. };
  355. /* PIR */
  356. enum PIR_BIT {
  357. PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
  358. };
  359. /* PSR */
  360. enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
  361. /* EESR */
  362. enum EESR_BIT {
  363. #if defined(SH_ETH_TYPE_ETHER)
  364. EESR_TWB = 0x40000000,
  365. #else
  366. EESR_TWB = 0xC0000000,
  367. EESR_TC1 = 0x20000000,
  368. EESR_TUC = 0x10000000,
  369. EESR_ROC = 0x80000000,
  370. #endif
  371. EESR_TABT = 0x04000000,
  372. EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
  373. #if defined(SH_ETH_TYPE_ETHER)
  374. EESR_ADE = 0x00800000,
  375. #endif
  376. EESR_ECI = 0x00400000,
  377. EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
  378. EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
  379. EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
  380. #if defined(SH_ETH_TYPE_ETHER)
  381. EESR_CND = 0x00000800,
  382. #endif
  383. EESR_DLC = 0x00000400,
  384. EESR_CD = 0x00000200, EESR_RTO = 0x00000100,
  385. EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
  386. EESR_CELF = 0x00000020, EESR_RRF = 0x00000010,
  387. EESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
  388. EESR_PRE = 0x00000002, EESR_CERF = 0x00000001,
  389. };
  390. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  391. # define TX_CHECK (EESR_TC1 | EESR_FTC)
  392. # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
  393. | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
  394. # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE)
  395. #else
  396. # define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO)
  397. # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
  398. | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
  399. # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)
  400. #endif
  401. /* EESIPR */
  402. enum DMAC_IM_BIT {
  403. DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
  404. DMAC_M_RABT = 0x02000000,
  405. DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
  406. DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
  407. DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
  408. DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
  409. DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
  410. DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
  411. DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
  412. DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
  413. DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
  414. DMAC_M_RINT1 = 0x00000001,
  415. };
  416. /* Receive descriptor bit */
  417. enum RD_STS_BIT {
  418. RD_RACT = 0x80000000, RD_RDLE = 0x40000000,
  419. RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
  420. RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
  421. RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
  422. RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
  423. RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
  424. RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
  425. RD_RFS1 = 0x00000001,
  426. };
  427. #define RDF1ST RD_RFP1
  428. #define RDFEND RD_RFP0
  429. #define RD_RFP (RD_RFP1|RD_RFP0)
  430. /* RDFFR*/
  431. enum RDFFR_BIT {
  432. RDFFR_RDLF = 0x01,
  433. };
  434. /* FCFTR */
  435. enum FCFTR_BIT {
  436. FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
  437. FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
  438. FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
  439. };
  440. #define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
  441. #define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
  442. /* Transfer descriptor bit */
  443. enum TD_STS_BIT {
  444. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) || \
  445. defined(SH_ETH_TYPE_RZ)
  446. TD_TACT = 0x80000000,
  447. #else
  448. TD_TACT = 0x7fffffff,
  449. #endif
  450. TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
  451. TD_TFP0 = 0x10000000,
  452. };
  453. #define TDF1ST TD_TFP1
  454. #define TDFEND TD_TFP0
  455. #define TD_TFP (TD_TFP1|TD_TFP0)
  456. /* RMCR */
  457. enum RECV_RST_BIT { RMCR_RST = 0x01, };
  458. /* ECMR */
  459. enum FELIC_MODE_BIT {
  460. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  461. ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
  462. ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
  463. #endif
  464. ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
  465. ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
  466. ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
  467. ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
  468. ECMR_PRM = 0x00000001,
  469. #ifdef CONFIG_CPU_SH7724
  470. ECMR_RTM = 0x00000010,
  471. #elif defined(CONFIG_RCAR_GEN2)
  472. ECMR_RTM = 0x00000004,
  473. #endif
  474. };
  475. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  476. #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | \
  477. ECMR_RXF | ECMR_TXF | ECMR_MCT)
  478. #elif defined(SH_ETH_TYPE_ETHER)
  479. #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
  480. #else
  481. #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
  482. #endif
  483. /* ECSR */
  484. enum ECSR_STATUS_BIT {
  485. #if defined(SH_ETH_TYPE_ETHER)
  486. ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
  487. #endif
  488. ECSR_LCHNG = 0x04,
  489. ECSR_MPD = 0x02, ECSR_ICD = 0x01,
  490. };
  491. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  492. # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
  493. #else
  494. # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
  495. ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP)
  496. #endif
  497. /* ECSIPR */
  498. enum ECSIPR_STATUS_MASK_BIT {
  499. #if defined(SH_ETH_TYPE_ETHER)
  500. ECSIPR_BRCRXIP = 0x20,
  501. ECSIPR_PSRTOIP = 0x10,
  502. #elif defined(SH_ETY_TYPE_GETHER)
  503. ECSIPR_PSRTOIP = 0x10,
  504. ECSIPR_PHYIP = 0x08,
  505. #endif
  506. ECSIPR_LCHNGIP = 0x04,
  507. ECSIPR_MPDIP = 0x02,
  508. ECSIPR_ICDIP = 0x01,
  509. };
  510. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  511. # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
  512. #else
  513. # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
  514. ECSIPR_ICDIP | ECSIPR_MPDIP)
  515. #endif
  516. /* APR */
  517. enum APR_BIT {
  518. APR_AP = 0x00000004,
  519. };
  520. /* MPR */
  521. enum MPR_BIT {
  522. MPR_MP = 0x00000006,
  523. };
  524. /* TRSCER */
  525. enum DESC_I_BIT {
  526. DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
  527. DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
  528. DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
  529. DESC_I_RINT1 = 0x0001,
  530. };
  531. /* RPADIR */
  532. enum RPADIR_BIT {
  533. RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
  534. RPADIR_PADR = 0x0003f,
  535. };
  536. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  537. # define RPADIR_INIT (0x00)
  538. #else
  539. # define RPADIR_INIT (RPADIR_PADS1)
  540. #endif
  541. /* FDR */
  542. enum FIFO_SIZE_BIT {
  543. FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
  544. };
  545. static inline unsigned long sh_eth_reg_addr(struct sh_eth_info *port,
  546. int enum_index)
  547. {
  548. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  549. const u16 *reg_offset = sh_eth_offset_gigabit;
  550. #elif defined(SH_ETH_TYPE_ETHER)
  551. const u16 *reg_offset = sh_eth_offset_fast_sh4;
  552. #else
  553. #error
  554. #endif
  555. return (unsigned long)port->iobase + reg_offset[enum_index];
  556. }
  557. static inline void sh_eth_write(struct sh_eth_info *port, unsigned long data,
  558. int enum_index)
  559. {
  560. outl(data, sh_eth_reg_addr(port, enum_index));
  561. }
  562. static inline unsigned long sh_eth_read(struct sh_eth_info *port,
  563. int enum_index)
  564. {
  565. return inl(sh_eth_reg_addr(port, enum_index));
  566. }