cortina.c 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Cortina CS4315/CS4340 10G PHY drivers
  4. *
  5. * Copyright 2014 Freescale Semiconductor, Inc.
  6. * Copyright 2018 NXP
  7. *
  8. */
  9. #include <config.h>
  10. #include <common.h>
  11. #include <malloc.h>
  12. #include <linux/ctype.h>
  13. #include <linux/string.h>
  14. #include <linux/err.h>
  15. #include <phy.h>
  16. #include <cortina.h>
  17. #ifdef CONFIG_SYS_CORTINA_FW_IN_NAND
  18. #include <nand.h>
  19. #elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH)
  20. #include <spi_flash.h>
  21. #elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC)
  22. #include <mmc.h>
  23. #endif
  24. #ifndef CONFIG_PHYLIB_10G
  25. #error The Cortina PHY needs 10G support
  26. #endif
  27. #ifndef CORTINA_NO_FW_UPLOAD
  28. struct cortina_reg_config cortina_reg_cfg[] = {
  29. /* CS4315_enable_sr_mode */
  30. {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
  31. {VILLA_MSEQ_OPTIONS, 0xf},
  32. {VILLA_MSEQ_PC, 0x0},
  33. {VILLA_MSEQ_BANKSELECT, 0x4},
  34. {VILLA_LINE_SDS_COMMON_SRX0_RX_CPA, 0x55},
  35. {VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER, 0x30},
  36. {VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT, 0x1},
  37. {VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT, 0x2},
  38. {VILLA_LINE_SDS_COMMON_SRX0_RX_CPB, 0x2003},
  39. {VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL, 0xF047},
  40. {VILLA_MSEQ_ENABLE_MSB, 0x0000},
  41. {VILLA_MSEQ_SPARE21_LSB, 0x6},
  42. {VILLA_MSEQ_RESET_COUNT_LSB, 0x0},
  43. {VILLA_MSEQ_SPARE12_MSB, 0x0000},
  44. /*
  45. * to invert the receiver path, uncomment the next line
  46. * write (VILLA_MSEQ_SPARE12_MSB, 0x4000)
  47. *
  48. * SPARE2_LSB is used to configure the device while in sr mode to
  49. * enable power savings and to use the optical module LOS signal.
  50. * in power savings mode, the internal prbs checker can not be used.
  51. * if the optical module LOS signal is used as an input to the micro
  52. * code, then the micro code will wait until the optical module
  53. * LOS = 0 before turning on the adaptive equalizer.
  54. * Setting SPARE2_LSB bit 0 to 1 places the devie in power savings mode
  55. * while setting bit 0 to 0 disables power savings mode.
  56. * Setting SPARE2_LSB bit 2 to 0 configures the device to use the
  57. * optical module LOS signal while setting bit 2 to 1 configures the
  58. * device so that it will ignore the optical module LOS SPARE2_LSB = 0
  59. */
  60. /* enable power savings, ignore optical module LOS */
  61. {VILLA_MSEQ_SPARE2_LSB, 0x5},
  62. {VILLA_MSEQ_SPARE7_LSB, 0x1e},
  63. {VILLA_MSEQ_BANKSELECT, 0x4},
  64. {VILLA_MSEQ_SPARE9_LSB, 0x2},
  65. {VILLA_MSEQ_SPARE3_LSB, 0x0F53},
  66. {VILLA_MSEQ_SPARE3_MSB, 0x2006},
  67. {VILLA_MSEQ_SPARE8_LSB, 0x3FF7},
  68. {VILLA_MSEQ_SPARE8_MSB, 0x0A46},
  69. {VILLA_MSEQ_COEF8_FFE0_LSB, 0xD500},
  70. {VILLA_MSEQ_COEF8_FFE1_LSB, 0x0200},
  71. {VILLA_MSEQ_COEF8_FFE2_LSB, 0xBA00},
  72. {VILLA_MSEQ_COEF8_FFE3_LSB, 0x0100},
  73. {VILLA_MSEQ_COEF8_FFE4_LSB, 0x0300},
  74. {VILLA_MSEQ_COEF8_FFE5_LSB, 0x0300},
  75. {VILLA_MSEQ_COEF8_DFE0_LSB, 0x0700},
  76. {VILLA_MSEQ_COEF8_DFE0N_LSB, 0x0E00},
  77. {VILLA_MSEQ_COEF8_DFE1_LSB, 0x0B00},
  78. {VILLA_DSP_SDS_DSP_COEF_LARGE_LEAK, 0x2},
  79. {VILLA_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB, 0xD000},
  80. {VILLA_MSEQ_POWER_DOWN_LSB, 0xFFFF},
  81. {VILLA_MSEQ_POWER_DOWN_MSB, 0x0},
  82. {VILLA_MSEQ_CAL_RX_SLICER, 0x80},
  83. {VILLA_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB, 0x3f},
  84. {VILLA_GLOBAL_MSEQCLKCTRL, 0x4},
  85. {VILLA_MSEQ_OPTIONS, 0x7},
  86. /* set up min value for ffe1 */
  87. {VILLA_MSEQ_COEF_INIT_SEL, 0x2},
  88. {VILLA_DSP_SDS_DSP_PRECODEDINITFFE21, 0x41},
  89. /* CS4315_sr_rx_pre_eq_set_4in */
  90. {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
  91. {VILLA_MSEQ_OPTIONS, 0xf},
  92. {VILLA_MSEQ_BANKSELECT, 0x4},
  93. {VILLA_MSEQ_PC, 0x0},
  94. /* for lengths from 3.5 to 4.5inches */
  95. {VILLA_MSEQ_SERDES_PARAM_LSB, 0x0306},
  96. {VILLA_MSEQ_SPARE25_LSB, 0x0306},
  97. {VILLA_MSEQ_SPARE21_LSB, 0x2},
  98. {VILLA_MSEQ_SPARE23_LSB, 0x2},
  99. {VILLA_MSEQ_CAL_RX_DFE_EQ, 0x0},
  100. {VILLA_GLOBAL_MSEQCLKCTRL, 0x4},
  101. {VILLA_MSEQ_OPTIONS, 0x7},
  102. /* CS4315_rx_drive_4inch */
  103. /* for length 4inches */
  104. {VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000},
  105. {VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023},
  106. {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E},
  107. /* CS4315_tx_drive_4inch */
  108. /* for length 4inches */
  109. {VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000},
  110. {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023},
  111. {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E},
  112. };
  113. void cs4340_upload_firmware(struct phy_device *phydev)
  114. {
  115. char line_temp[0x50] = {0};
  116. char reg_addr[0x50] = {0};
  117. char reg_data[0x50] = {0};
  118. int i, line_cnt = 0, column_cnt = 0;
  119. struct cortina_reg_config fw_temp;
  120. char *addr = NULL;
  121. #if defined(CONFIG_SYS_CORTINA_FW_IN_NOR) || \
  122. defined(CONFIG_SYS_CORTINA_FW_IN_REMOTE)
  123. addr = (char *)CONFIG_CORTINA_FW_ADDR;
  124. #elif defined(CONFIG_SYS_CORTINA_FW_IN_NAND)
  125. int ret;
  126. size_t fw_length = CONFIG_CORTINA_FW_LENGTH;
  127. addr = malloc(CONFIG_CORTINA_FW_LENGTH);
  128. ret = nand_read(get_nand_dev_by_index(0),
  129. (loff_t)CONFIG_CORTINA_FW_ADDR,
  130. &fw_length, (u_char *)addr);
  131. if (ret == -EUCLEAN) {
  132. printf("NAND read of Cortina firmware at 0x%x failed %d\n",
  133. CONFIG_CORTINA_FW_ADDR, ret);
  134. }
  135. #elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH)
  136. int ret;
  137. struct spi_flash *ucode_flash;
  138. addr = malloc(CONFIG_CORTINA_FW_LENGTH);
  139. ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
  140. CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
  141. if (!ucode_flash) {
  142. puts("SF: probe for Cortina ucode failed\n");
  143. } else {
  144. ret = spi_flash_read(ucode_flash, CONFIG_CORTINA_FW_ADDR,
  145. CONFIG_CORTINA_FW_LENGTH, addr);
  146. if (ret)
  147. puts("SF: read for Cortina ucode failed\n");
  148. spi_flash_free(ucode_flash);
  149. }
  150. #elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC)
  151. int dev = CONFIG_SYS_MMC_ENV_DEV;
  152. u32 cnt = CONFIG_CORTINA_FW_LENGTH / 512;
  153. u32 blk = CONFIG_CORTINA_FW_ADDR / 512;
  154. struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
  155. if (!mmc) {
  156. puts("Failed to find MMC device for Cortina ucode\n");
  157. } else {
  158. addr = malloc(CONFIG_CORTINA_FW_LENGTH);
  159. printf("MMC read: dev # %u, block # %u, count %u ...\n",
  160. dev, blk, cnt);
  161. mmc_init(mmc);
  162. (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
  163. addr);
  164. }
  165. #endif
  166. while (*addr != 'Q') {
  167. i = 0;
  168. while (*addr != 0x0a) {
  169. line_temp[i++] = *addr++;
  170. if (0x50 < i) {
  171. printf("Not found Cortina PHY ucode at 0x%p\n",
  172. (char *)CONFIG_CORTINA_FW_ADDR);
  173. return;
  174. }
  175. }
  176. addr++; /* skip '\n' */
  177. line_cnt++;
  178. column_cnt = i;
  179. line_temp[column_cnt] = '\0';
  180. if (CONFIG_CORTINA_FW_LENGTH < line_cnt)
  181. return;
  182. for (i = 0; i < column_cnt; i++) {
  183. if (isspace(line_temp[i++]))
  184. break;
  185. }
  186. memcpy(reg_addr, line_temp, i);
  187. memcpy(reg_data, &line_temp[i], column_cnt - i);
  188. strim(reg_addr);
  189. strim(reg_data);
  190. fw_temp.reg_addr = (simple_strtoul(reg_addr, NULL, 0)) & 0xffff;
  191. fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) &
  192. 0xffff;
  193. phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value);
  194. }
  195. }
  196. #endif
  197. int cs4340_phy_init(struct phy_device *phydev)
  198. {
  199. #ifndef CORTINA_NO_FW_UPLOAD
  200. int timeout = 100; /* 100ms */
  201. #endif
  202. int reg_value;
  203. /*
  204. * Cortina phy has provision to store
  205. * phy firmware in attached dedicated EEPROM.
  206. * Boards designed with EEPROM attached to Cortina
  207. * does not require FW upload.
  208. */
  209. #ifndef CORTINA_NO_FW_UPLOAD
  210. /* step1: BIST test */
  211. phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004);
  212. phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000);
  213. phy_write(phydev, 0x00, VILLA_GLOBAL_BIST_CONTROL, 0x0001);
  214. while (--timeout) {
  215. reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_BIST_STATUS);
  216. if (reg_value & mseq_edc_bist_done) {
  217. if (0 == (reg_value & mseq_edc_bist_fail))
  218. break;
  219. }
  220. udelay(1000);
  221. }
  222. if (!timeout) {
  223. printf("%s BIST mseq_edc_bist_done timeout!\n", __func__);
  224. return -1;
  225. }
  226. /* setp2: upload ucode */
  227. cs4340_upload_firmware(phydev);
  228. #endif
  229. reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS);
  230. if (reg_value) {
  231. debug("%s checksum status failed.\n", __func__);
  232. return -1;
  233. }
  234. return 0;
  235. }
  236. int cs4340_config(struct phy_device *phydev)
  237. {
  238. cs4340_phy_init(phydev);
  239. return 0;
  240. }
  241. int cs4340_probe(struct phy_device *phydev)
  242. {
  243. phydev->flags = PHY_FLAG_BROKEN_RESET;
  244. return 0;
  245. }
  246. int cs4340_startup(struct phy_device *phydev)
  247. {
  248. phydev->link = 1;
  249. /* For now just lie and say it's 10G all the time */
  250. phydev->speed = SPEED_10000;
  251. phydev->duplex = DUPLEX_FULL;
  252. return 0;
  253. }
  254. int cs4223_phy_init(struct phy_device *phydev)
  255. {
  256. int reg_value;
  257. reg_value = phy_read(phydev, 0x00, CS4223_EEPROM_STATUS);
  258. if (!(reg_value & CS4223_EEPROM_FIRMWARE_LOADDONE)) {
  259. printf("%s CS4223 Firmware not present in EERPOM\n", __func__);
  260. return -ENOSYS;
  261. }
  262. return 0;
  263. }
  264. int cs4223_config(struct phy_device *phydev)
  265. {
  266. return cs4223_phy_init(phydev);
  267. }
  268. int cs4223_probe(struct phy_device *phydev)
  269. {
  270. phydev->flags = PHY_FLAG_BROKEN_RESET;
  271. return 0;
  272. }
  273. int cs4223_startup(struct phy_device *phydev)
  274. {
  275. phydev->link = 1;
  276. phydev->speed = SPEED_10000;
  277. phydev->duplex = DUPLEX_FULL;
  278. return 0;
  279. }
  280. struct phy_driver cs4340_driver = {
  281. .name = "Cortina CS4315/CS4340",
  282. .uid = PHY_UID_CS4340,
  283. .mask = 0xfffffff0,
  284. .features = PHY_10G_FEATURES,
  285. .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
  286. MDIO_DEVS_PHYXS | MDIO_DEVS_AN |
  287. MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2),
  288. .config = &cs4340_config,
  289. .probe = &cs4340_probe,
  290. .startup = &cs4340_startup,
  291. .shutdown = &gen10g_shutdown,
  292. };
  293. struct phy_driver cs4223_driver = {
  294. .name = "Cortina CS4223",
  295. .uid = PHY_UID_CS4223,
  296. .mask = 0x0ffff00f,
  297. .features = PHY_10G_FEATURES,
  298. .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
  299. MDIO_DEVS_AN),
  300. .config = &cs4223_config,
  301. .probe = &cs4223_probe,
  302. .startup = &cs4223_startup,
  303. .shutdown = &gen10g_shutdown,
  304. };
  305. int phy_cortina_init(void)
  306. {
  307. phy_register(&cs4340_driver);
  308. phy_register(&cs4223_driver);
  309. return 0;
  310. }
  311. int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
  312. {
  313. int phy_reg;
  314. /* Cortina PHY has non-standard offset of PHY ID registers */
  315. phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_LSB);
  316. if (phy_reg < 0)
  317. return -EIO;
  318. *phy_id = (phy_reg & 0xffff) << 16;
  319. phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_MSB);
  320. if (phy_reg < 0)
  321. return -EIO;
  322. *phy_id |= (phy_reg & 0xffff);
  323. if ((*phy_id == PHY_UID_CS4340) || (*phy_id == PHY_UID_CS4223))
  324. return 0;
  325. /*
  326. * If Cortina PHY not detected,
  327. * try generic way to find PHY ID registers
  328. */
  329. phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
  330. if (phy_reg < 0)
  331. return -EIO;
  332. *phy_id = (phy_reg & 0xffff) << 16;
  333. phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
  334. if (phy_reg < 0)
  335. return -EIO;
  336. *phy_id |= (phy_reg & 0xffff);
  337. return 0;
  338. }