mcfmii.c 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
  4. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  5. */
  6. #include <common.h>
  7. #include <config.h>
  8. #include <net.h>
  9. #include <netdev.h>
  10. #ifdef CONFIG_MCF547x_8x
  11. #include <asm/fsl_mcdmafec.h>
  12. #else
  13. #include <asm/fec.h>
  14. #endif
  15. #include <asm/immap.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. #if defined(CONFIG_CMD_NET)
  18. #undef MII_DEBUG
  19. #undef ET_DEBUG
  20. /*extern int fecpin_setclear(struct eth_device *dev, int setclear);*/
  21. #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
  22. #include <miiphy.h>
  23. /* Make MII read/write commands for the FEC. */
  24. #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
  25. (REG & 0x1f) << 18))
  26. #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
  27. (REG & 0x1f) << 18) | (VAL & 0xffff))
  28. #ifndef CONFIG_SYS_UNSPEC_PHYID
  29. # define CONFIG_SYS_UNSPEC_PHYID 0
  30. #endif
  31. #ifndef CONFIG_SYS_UNSPEC_STRID
  32. # define CONFIG_SYS_UNSPEC_STRID 0
  33. #endif
  34. #ifdef CONFIG_MCF547x_8x
  35. typedef struct fec_info_dma FEC_INFO_T;
  36. #define FEC_T fecdma_t
  37. #else
  38. typedef struct fec_info_s FEC_INFO_T;
  39. #define FEC_T fec_t
  40. #endif
  41. typedef struct phy_info_struct {
  42. u32 phyid;
  43. char *strid;
  44. } phy_info_t;
  45. phy_info_t phyinfo[] = {
  46. {0x0022561B, "AMD79C784VC"}, /* AMD 79C784VC */
  47. {0x00406322, "BCM5222"}, /* Broadcom 5222 */
  48. {0x02a80150, "Intel82555"}, /* Intel 82555 */
  49. {0x0016f870, "LSI80225"}, /* LSI 80225 */
  50. {0x0016f880, "LSI80225/B"}, /* LSI 80225/B */
  51. {0x78100000, "LXT970"}, /* LXT970 */
  52. {0x001378e0, "LXT971"}, /* LXT971 and 972 */
  53. {0x00221619, "KS8721BL"}, /* Micrel KS8721BL/SL */
  54. {0x00221512, "KSZ8041NL"}, /* Micrel KSZ8041NL */
  55. {0x20005CE1, "N83640"}, /* National 83640 */
  56. {0x20005C90, "N83848"}, /* National 83848 */
  57. {0x20005CA2, "N83849"}, /* National 83849 */
  58. {0x01814400, "QS6612"}, /* QS6612 */
  59. #if defined(CONFIG_SYS_UNSPEC_PHYID) && defined(CONFIG_SYS_UNSPEC_STRID)
  60. {CONFIG_SYS_UNSPEC_PHYID, CONFIG_SYS_UNSPEC_STRID},
  61. #endif
  62. {0, 0}
  63. };
  64. /*
  65. * mii_init -- Initialize the MII for MII command without ethernet
  66. * This function is a subset of eth_init
  67. */
  68. void mii_reset(FEC_INFO_T *info)
  69. {
  70. volatile FEC_T *fecp = (FEC_T *) (info->miibase);
  71. int i;
  72. fecp->ecr = FEC_ECR_RESET;
  73. for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
  74. udelay(1);
  75. }
  76. if (i == FEC_RESET_DELAY)
  77. printf("FEC_RESET_DELAY timeout\n");
  78. }
  79. /* send command to phy using mii, wait for result */
  80. uint mii_send(uint mii_cmd)
  81. {
  82. FEC_INFO_T *info;
  83. volatile FEC_T *ep;
  84. struct eth_device *dev;
  85. uint mii_reply;
  86. int j = 0;
  87. /* retrieve from register structure */
  88. dev = eth_get_dev();
  89. info = dev->priv;
  90. ep = (FEC_T *) info->miibase;
  91. ep->mmfr = mii_cmd; /* command to phy */
  92. /* wait for mii complete */
  93. while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
  94. udelay(1);
  95. j++;
  96. }
  97. if (j >= MCFFEC_TOUT_LOOP) {
  98. printf("MII not complete\n");
  99. return -1;
  100. }
  101. mii_reply = ep->mmfr; /* result from phy */
  102. ep->eir = FEC_EIR_MII; /* clear MII complete */
  103. #ifdef ET_DEBUG
  104. printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
  105. __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
  106. #endif
  107. return (mii_reply & 0xffff); /* data read from phy */
  108. }
  109. #endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
  110. #if defined(CONFIG_SYS_DISCOVER_PHY)
  111. int mii_discover_phy(struct eth_device *dev)
  112. {
  113. #define MAX_PHY_PASSES 11
  114. FEC_INFO_T *info = dev->priv;
  115. int phyaddr, pass;
  116. uint phyno, phytype;
  117. int i, found = 0;
  118. if (info->phyname_init)
  119. return info->phy_addr;
  120. phyaddr = -1; /* didn't find a PHY yet */
  121. for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
  122. if (pass > 1) {
  123. /* PHY may need more time to recover from reset.
  124. * The LXT970 needs 50ms typical, no maximum is
  125. * specified, so wait 10ms before try again.
  126. * With 11 passes this gives it 100ms to wake up.
  127. */
  128. udelay(10000); /* wait 10ms */
  129. }
  130. for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
  131. phytype = mii_send(mk_mii_read(phyno, MII_PHYSID1));
  132. #ifdef ET_DEBUG
  133. printf("PHY type 0x%x pass %d type\n", phytype, pass);
  134. #endif
  135. if (phytype == 0xffff)
  136. continue;
  137. phyaddr = phyno;
  138. phytype <<= 16;
  139. phytype |=
  140. mii_send(mk_mii_read(phyno, MII_PHYSID2));
  141. #ifdef ET_DEBUG
  142. printf("PHY @ 0x%x pass %d\n", phyno, pass);
  143. #endif
  144. for (i = 0; (i < ARRAY_SIZE(phyinfo))
  145. && (phyinfo[i].phyid != 0); i++) {
  146. if (phyinfo[i].phyid == phytype) {
  147. #ifdef ET_DEBUG
  148. printf("phyid %x - %s\n",
  149. phyinfo[i].phyid,
  150. phyinfo[i].strid);
  151. #endif
  152. strcpy(info->phy_name, phyinfo[i].strid);
  153. info->phyname_init = 1;
  154. found = 1;
  155. break;
  156. }
  157. }
  158. if (!found) {
  159. #ifdef ET_DEBUG
  160. printf("0x%08x\n", phytype);
  161. #endif
  162. strcpy(info->phy_name, "unknown");
  163. info->phyname_init = 1;
  164. break;
  165. }
  166. }
  167. }
  168. if (phyaddr < 0)
  169. printf("No PHY device found.\n");
  170. return phyaddr;
  171. }
  172. #endif /* CONFIG_SYS_DISCOVER_PHY */
  173. void mii_init(void) __attribute__((weak,alias("__mii_init")));
  174. void __mii_init(void)
  175. {
  176. FEC_INFO_T *info;
  177. volatile FEC_T *fecp;
  178. struct eth_device *dev;
  179. int miispd = 0, i = 0;
  180. u16 status = 0;
  181. u16 linkgood = 0;
  182. /* retrieve from register structure */
  183. dev = eth_get_dev();
  184. info = dev->priv;
  185. fecp = (FEC_T *) info->miibase;
  186. fecpin_setclear(dev, 1);
  187. mii_reset(info);
  188. /* We use strictly polling mode only */
  189. fecp->eimr = 0;
  190. /* Clear any pending interrupt */
  191. fecp->eir = 0xffffffff;
  192. /* Set MII speed */
  193. miispd = (gd->bus_clk / 1000000) / 5;
  194. fecp->mscr = miispd << 1;
  195. info->phy_addr = mii_discover_phy(dev);
  196. while (i < MCFFEC_TOUT_LOOP) {
  197. status = 0;
  198. i++;
  199. /* Read PHY control register */
  200. miiphy_read(dev->name, info->phy_addr, MII_BMCR, &status);
  201. /* If phy set to autonegotiate, wait for autonegotiation done,
  202. * if phy is not autonegotiating, just wait for link up.
  203. */
  204. if ((status & BMCR_ANENABLE) == BMCR_ANENABLE) {
  205. linkgood = (BMSR_ANEGCOMPLETE | BMSR_LSTATUS);
  206. } else {
  207. linkgood = BMSR_LSTATUS;
  208. }
  209. /* Read PHY status register */
  210. miiphy_read(dev->name, info->phy_addr, MII_BMSR, &status);
  211. if ((status & linkgood) == linkgood)
  212. break;
  213. udelay(1);
  214. }
  215. if (i >= MCFFEC_TOUT_LOOP) {
  216. printf("Link UP timeout\n");
  217. }
  218. /* adapt to the duplex and speed settings of the phy */
  219. info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
  220. info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
  221. }
  222. /*
  223. * Read and write a MII PHY register, routines used by MII Utilities
  224. *
  225. * FIXME: These routines are expected to return 0 on success, but mii_send
  226. * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
  227. * no PHY connected...
  228. * For now always return 0.
  229. * FIXME: These routines only work after calling eth_init() at least once!
  230. * Otherwise they hang in mii_send() !!! Sorry!
  231. */
  232. int mcffec_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
  233. {
  234. short rdreg; /* register working value */
  235. #ifdef MII_DEBUG
  236. printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
  237. #endif
  238. rdreg = mii_send(mk_mii_read(addr, reg));
  239. #ifdef MII_DEBUG
  240. printf("0x%04x\n", rdreg);
  241. #endif
  242. return rdreg;
  243. }
  244. int mcffec_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
  245. u16 value)
  246. {
  247. #ifdef MII_DEBUG
  248. printf("miiphy_write(0x%x) @ 0x%x = 0x%04x\n", reg, addr, value);
  249. #endif
  250. mii_send(mk_mii_write(addr, reg, value));
  251. return 0;
  252. }
  253. #endif /* CONFIG_CMD_NET */