eepro100.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <malloc.h>
  8. #include <net.h>
  9. #include <netdev.h>
  10. #include <asm/io.h>
  11. #include <pci.h>
  12. #include <miiphy.h>
  13. #undef DEBUG
  14. /* Ethernet chip registers.
  15. */
  16. #define SCBStatus 0 /* Rx/Command Unit Status *Word* */
  17. #define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */
  18. #define SCBCmd 2 /* Rx/Command Unit Command *Word* */
  19. #define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */
  20. #define SCBPointer 4 /* General purpose pointer. */
  21. #define SCBPort 8 /* Misc. commands and operands. */
  22. #define SCBflash 12 /* Flash memory control. */
  23. #define SCBeeprom 14 /* EEPROM memory control. */
  24. #define SCBCtrlMDI 16 /* MDI interface control. */
  25. #define SCBEarlyRx 20 /* Early receive byte count. */
  26. #define SCBGenControl 28 /* 82559 General Control Register */
  27. #define SCBGenStatus 29 /* 82559 General Status register */
  28. /* 82559 SCB status word defnitions
  29. */
  30. #define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */
  31. #define SCB_STATUS_FR 0x4000 /* frame received */
  32. #define SCB_STATUS_CNA 0x2000 /* CU left active state */
  33. #define SCB_STATUS_RNR 0x1000 /* receiver left ready state */
  34. #define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */
  35. #define SCB_STATUS_SWI 0x0400 /* software generated interrupt */
  36. #define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */
  37. #define SCB_INTACK_MASK 0xFD00 /* all the above */
  38. #define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA)
  39. #define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR)
  40. /* System control block commands
  41. */
  42. /* CU Commands */
  43. #define CU_NOP 0x0000
  44. #define CU_START 0x0010
  45. #define CU_RESUME 0x0020
  46. #define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */
  47. #define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */
  48. #define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */
  49. #define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */
  50. /* RUC Commands */
  51. #define RUC_NOP 0x0000
  52. #define RUC_START 0x0001
  53. #define RUC_RESUME 0x0002
  54. #define RUC_ABORT 0x0004
  55. #define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */
  56. #define RUC_RESUMENR 0x0007
  57. #define CU_CMD_MASK 0x00f0
  58. #define RU_CMD_MASK 0x0007
  59. #define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */
  60. #define SCB_SWI 0x0200 /* 1 - cause device to interrupt */
  61. #define CU_STATUS_MASK 0x00C0
  62. #define RU_STATUS_MASK 0x003C
  63. #define RU_STATUS_IDLE (0<<2)
  64. #define RU_STATUS_SUS (1<<2)
  65. #define RU_STATUS_NORES (2<<2)
  66. #define RU_STATUS_READY (4<<2)
  67. #define RU_STATUS_NO_RBDS_SUS ((1<<2)|(8<<2))
  68. #define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2))
  69. #define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2))
  70. /* 82559 Port interface commands.
  71. */
  72. #define I82559_RESET 0x00000000 /* Software reset */
  73. #define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */
  74. #define I82559_SELECTIVE_RESET 0x00000002
  75. #define I82559_DUMP 0x00000003
  76. #define I82559_DUMP_WAKEUP 0x00000007
  77. /* 82559 Eeprom interface.
  78. */
  79. #define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */
  80. #define EE_CS 0x02 /* EEPROM chip select. */
  81. #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
  82. #define EE_WRITE_0 0x01
  83. #define EE_WRITE_1 0x05
  84. #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
  85. #define EE_ENB (0x4800 | EE_CS)
  86. #define EE_CMD_BITS 3
  87. #define EE_DATA_BITS 16
  88. /* The EEPROM commands include the alway-set leading bit.
  89. */
  90. #define EE_EWENB_CMD (4 << addr_len)
  91. #define EE_WRITE_CMD (5 << addr_len)
  92. #define EE_READ_CMD (6 << addr_len)
  93. #define EE_ERASE_CMD (7 << addr_len)
  94. /* Receive frame descriptors.
  95. */
  96. struct RxFD {
  97. volatile u16 status;
  98. volatile u16 control;
  99. volatile u32 link; /* struct RxFD * */
  100. volatile u32 rx_buf_addr; /* void * */
  101. volatile u32 count;
  102. volatile u8 data[PKTSIZE_ALIGN];
  103. };
  104. #define RFD_STATUS_C 0x8000 /* completion of received frame */
  105. #define RFD_STATUS_OK 0x2000 /* frame received with no errors */
  106. #define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */
  107. #define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */
  108. #define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */
  109. #define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */
  110. #define RFD_COUNT_MASK 0x3fff
  111. #define RFD_COUNT_F 0x4000
  112. #define RFD_COUNT_EOF 0x8000
  113. #define RFD_RX_CRC 0x0800 /* crc error */
  114. #define RFD_RX_ALIGNMENT 0x0400 /* alignment error */
  115. #define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */
  116. #define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */
  117. #define RFD_RX_SHORT 0x0080 /* short frame error */
  118. #define RFD_RX_LENGTH 0x0020
  119. #define RFD_RX_ERROR 0x0010 /* receive error */
  120. #define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */
  121. #define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */
  122. #define RFD_RX_TCO 0x0001 /* TCO indication */
  123. /* Transmit frame descriptors
  124. */
  125. struct TxFD { /* Transmit frame descriptor set. */
  126. volatile u16 status;
  127. volatile u16 command;
  128. volatile u32 link; /* void * */
  129. volatile u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */
  130. volatile s32 count;
  131. volatile u32 tx_buf_addr0; /* void *, frame to be transmitted. */
  132. volatile s32 tx_buf_size0; /* Length of Tx frame. */
  133. volatile u32 tx_buf_addr1; /* void *, frame to be transmitted. */
  134. volatile s32 tx_buf_size1; /* Length of Tx frame. */
  135. };
  136. #define TxCB_CMD_TRANSMIT 0x0004 /* transmit command */
  137. #define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */
  138. #define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */
  139. #define TxCB_CMD_I 0x2000 /* generate interrupt on completion */
  140. #define TxCB_CMD_S 0x4000 /* suspend on completion */
  141. #define TxCB_CMD_EL 0x8000 /* last command block in CBL */
  142. #define TxCB_COUNT_MASK 0x3fff
  143. #define TxCB_COUNT_EOF 0x8000
  144. /* The Speedo3 Rx and Tx frame/buffer descriptors.
  145. */
  146. struct descriptor { /* A generic descriptor. */
  147. volatile u16 status;
  148. volatile u16 command;
  149. volatile u32 link; /* struct descriptor * */
  150. unsigned char params[0];
  151. };
  152. #define CONFIG_SYS_CMD_EL 0x8000
  153. #define CONFIG_SYS_CMD_SUSPEND 0x4000
  154. #define CONFIG_SYS_CMD_INT 0x2000
  155. #define CONFIG_SYS_CMD_IAS 0x0001 /* individual address setup */
  156. #define CONFIG_SYS_CMD_CONFIGURE 0x0002 /* configure */
  157. #define CONFIG_SYS_STATUS_C 0x8000
  158. #define CONFIG_SYS_STATUS_OK 0x2000
  159. /* Misc.
  160. */
  161. #define NUM_RX_DESC PKTBUFSRX
  162. #define NUM_TX_DESC 1 /* Number of TX descriptors */
  163. #define TOUT_LOOP 1000000
  164. #define ETH_ALEN 6
  165. static struct RxFD rx_ring[NUM_RX_DESC]; /* RX descriptor ring */
  166. static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
  167. static int rx_next; /* RX descriptor ring pointer */
  168. static int tx_next; /* TX descriptor ring pointer */
  169. static int tx_threshold;
  170. /*
  171. * The parameters for a CmdConfigure operation.
  172. * There are so many options that it would be difficult to document
  173. * each bit. We mostly use the default or recommended settings.
  174. */
  175. static const char i82558_config_cmd[] = {
  176. 22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */
  177. 0, 0x2E, 0, 0x60, 0x08, 0x88,
  178. 0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */
  179. 0x31, 0x05,
  180. };
  181. static void init_rx_ring (struct eth_device *dev);
  182. static void purge_tx_ring (struct eth_device *dev);
  183. static void read_hw_addr (struct eth_device *dev, bd_t * bis);
  184. static int eepro100_init (struct eth_device *dev, bd_t * bis);
  185. static int eepro100_send(struct eth_device *dev, void *packet, int length);
  186. static int eepro100_recv (struct eth_device *dev);
  187. static void eepro100_halt (struct eth_device *dev);
  188. #if defined(CONFIG_E500)
  189. #define bus_to_phys(a) (a)
  190. #define phys_to_bus(a) (a)
  191. #else
  192. #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
  193. #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
  194. #endif
  195. static inline int INW (struct eth_device *dev, u_long addr)
  196. {
  197. return le16_to_cpu(*(volatile u16 *)(addr + (u_long)dev->iobase));
  198. }
  199. static inline void OUTW (struct eth_device *dev, int command, u_long addr)
  200. {
  201. *(volatile u16 *)((addr + (u_long)dev->iobase)) = cpu_to_le16(command);
  202. }
  203. static inline void OUTL (struct eth_device *dev, int command, u_long addr)
  204. {
  205. *(volatile u32 *)((addr + (u_long)dev->iobase)) = cpu_to_le32(command);
  206. }
  207. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  208. static inline int INL (struct eth_device *dev, u_long addr)
  209. {
  210. return le32_to_cpu(*(volatile u32 *)(addr + (u_long)dev->iobase));
  211. }
  212. static int get_phyreg (struct eth_device *dev, unsigned char addr,
  213. unsigned char reg, unsigned short *value)
  214. {
  215. int cmd;
  216. int timeout = 50;
  217. /* read requested data */
  218. cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
  219. OUTL (dev, cmd, SCBCtrlMDI);
  220. do {
  221. udelay(1000);
  222. cmd = INL (dev, SCBCtrlMDI);
  223. } while (!(cmd & (1 << 28)) && (--timeout));
  224. if (timeout == 0)
  225. return -1;
  226. *value = (unsigned short) (cmd & 0xffff);
  227. return 0;
  228. }
  229. static int set_phyreg (struct eth_device *dev, unsigned char addr,
  230. unsigned char reg, unsigned short value)
  231. {
  232. int cmd;
  233. int timeout = 50;
  234. /* write requested data */
  235. cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
  236. OUTL (dev, cmd | value, SCBCtrlMDI);
  237. while (!(INL (dev, SCBCtrlMDI) & (1 << 28)) && (--timeout))
  238. udelay(1000);
  239. if (timeout == 0)
  240. return -1;
  241. return 0;
  242. }
  243. /* Check if given phyaddr is valid, i.e. there is a PHY connected.
  244. * Do this by checking model value field from ID2 register.
  245. */
  246. static struct eth_device* verify_phyaddr (const char *devname,
  247. unsigned char addr)
  248. {
  249. struct eth_device *dev;
  250. unsigned short value;
  251. unsigned char model;
  252. dev = eth_get_dev_by_name(devname);
  253. if (dev == NULL) {
  254. printf("%s: no such device\n", devname);
  255. return NULL;
  256. }
  257. /* read id2 register */
  258. if (get_phyreg(dev, addr, MII_PHYSID2, &value) != 0) {
  259. printf("%s: mii read timeout!\n", devname);
  260. return NULL;
  261. }
  262. /* get model */
  263. model = (unsigned char)((value >> 4) & 0x003f);
  264. if (model == 0) {
  265. printf("%s: no PHY at address %d\n", devname, addr);
  266. return NULL;
  267. }
  268. return dev;
  269. }
  270. static int eepro100_miiphy_read(struct mii_dev *bus, int addr, int devad,
  271. int reg)
  272. {
  273. unsigned short value = 0;
  274. struct eth_device *dev;
  275. dev = verify_phyaddr(bus->name, addr);
  276. if (dev == NULL)
  277. return -1;
  278. if (get_phyreg(dev, addr, reg, &value) != 0) {
  279. printf("%s: mii read timeout!\n", bus->name);
  280. return -1;
  281. }
  282. return value;
  283. }
  284. static int eepro100_miiphy_write(struct mii_dev *bus, int addr, int devad,
  285. int reg, u16 value)
  286. {
  287. struct eth_device *dev;
  288. dev = verify_phyaddr(bus->name, addr);
  289. if (dev == NULL)
  290. return -1;
  291. if (set_phyreg(dev, addr, reg, value) != 0) {
  292. printf("%s: mii write timeout!\n", bus->name);
  293. return -1;
  294. }
  295. return 0;
  296. }
  297. #endif
  298. /* Wait for the chip get the command.
  299. */
  300. static int wait_for_eepro100 (struct eth_device *dev)
  301. {
  302. int i;
  303. for (i = 0; INW (dev, SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) {
  304. if (i >= TOUT_LOOP) {
  305. return 0;
  306. }
  307. }
  308. return 1;
  309. }
  310. static struct pci_device_id supported[] = {
  311. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557},
  312. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559},
  313. {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER},
  314. {}
  315. };
  316. int eepro100_initialize (bd_t * bis)
  317. {
  318. pci_dev_t devno;
  319. int card_number = 0;
  320. struct eth_device *dev;
  321. u32 iobase, status;
  322. int idx = 0;
  323. while (1) {
  324. /* Find PCI device
  325. */
  326. if ((devno = pci_find_devices (supported, idx++)) < 0) {
  327. break;
  328. }
  329. pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase);
  330. iobase &= ~0xf;
  331. #ifdef DEBUG
  332. printf ("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n",
  333. iobase);
  334. #endif
  335. pci_write_config_dword (devno,
  336. PCI_COMMAND,
  337. PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  338. /* Check if I/O accesses and Bus Mastering are enabled.
  339. */
  340. pci_read_config_dword (devno, PCI_COMMAND, &status);
  341. if (!(status & PCI_COMMAND_MEMORY)) {
  342. printf ("Error: Can not enable MEM access.\n");
  343. continue;
  344. }
  345. if (!(status & PCI_COMMAND_MASTER)) {
  346. printf ("Error: Can not enable Bus Mastering.\n");
  347. continue;
  348. }
  349. dev = (struct eth_device *) malloc (sizeof *dev);
  350. if (!dev) {
  351. printf("eepro100: Can not allocate memory\n");
  352. break;
  353. }
  354. memset(dev, 0, sizeof(*dev));
  355. sprintf (dev->name, "i82559#%d", card_number);
  356. dev->priv = (void *) devno; /* this have to come before bus_to_phys() */
  357. dev->iobase = bus_to_phys (iobase);
  358. dev->init = eepro100_init;
  359. dev->halt = eepro100_halt;
  360. dev->send = eepro100_send;
  361. dev->recv = eepro100_recv;
  362. eth_register (dev);
  363. #if defined (CONFIG_MII) || defined(CONFIG_CMD_MII)
  364. /* register mii command access routines */
  365. int retval;
  366. struct mii_dev *mdiodev = mdio_alloc();
  367. if (!mdiodev)
  368. return -ENOMEM;
  369. strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
  370. mdiodev->read = eepro100_miiphy_read;
  371. mdiodev->write = eepro100_miiphy_write;
  372. retval = mdio_register(mdiodev);
  373. if (retval < 0)
  374. return retval;
  375. #endif
  376. card_number++;
  377. /* Set the latency timer for value.
  378. */
  379. pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
  380. udelay (10 * 1000);
  381. read_hw_addr (dev, bis);
  382. }
  383. return card_number;
  384. }
  385. static int eepro100_init (struct eth_device *dev, bd_t * bis)
  386. {
  387. int i, status = -1;
  388. int tx_cur;
  389. struct descriptor *ias_cmd, *cfg_cmd;
  390. /* Reset the ethernet controller
  391. */
  392. OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
  393. udelay (20);
  394. OUTL (dev, I82559_RESET, SCBPort);
  395. udelay (20);
  396. if (!wait_for_eepro100 (dev)) {
  397. printf ("Error: Can not reset ethernet controller.\n");
  398. goto Done;
  399. }
  400. OUTL (dev, 0, SCBPointer);
  401. OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
  402. if (!wait_for_eepro100 (dev)) {
  403. printf ("Error: Can not reset ethernet controller.\n");
  404. goto Done;
  405. }
  406. OUTL (dev, 0, SCBPointer);
  407. OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
  408. /* Initialize Rx and Tx rings.
  409. */
  410. init_rx_ring (dev);
  411. purge_tx_ring (dev);
  412. /* Tell the adapter where the RX ring is located.
  413. */
  414. if (!wait_for_eepro100 (dev)) {
  415. printf ("Error: Can not reset ethernet controller.\n");
  416. goto Done;
  417. }
  418. OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
  419. OUTW (dev, SCB_M | RUC_START, SCBCmd);
  420. /* Send the Configure frame */
  421. tx_cur = tx_next;
  422. tx_next = ((tx_next + 1) % NUM_TX_DESC);
  423. cfg_cmd = (struct descriptor *) &tx_ring[tx_cur];
  424. cfg_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_CONFIGURE));
  425. cfg_cmd->status = 0;
  426. cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
  427. memcpy (cfg_cmd->params, i82558_config_cmd,
  428. sizeof (i82558_config_cmd));
  429. if (!wait_for_eepro100 (dev)) {
  430. printf ("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n");
  431. goto Done;
  432. }
  433. OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
  434. OUTW (dev, SCB_M | CU_START, SCBCmd);
  435. for (i = 0;
  436. !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
  437. i++) {
  438. if (i >= TOUT_LOOP) {
  439. printf ("%s: Tx error buffer not ready\n", dev->name);
  440. goto Done;
  441. }
  442. }
  443. if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
  444. printf ("TX error status = 0x%08X\n",
  445. le16_to_cpu (tx_ring[tx_cur].status));
  446. goto Done;
  447. }
  448. /* Send the Individual Address Setup frame
  449. */
  450. tx_cur = tx_next;
  451. tx_next = ((tx_next + 1) % NUM_TX_DESC);
  452. ias_cmd = (struct descriptor *) &tx_ring[tx_cur];
  453. ias_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_IAS));
  454. ias_cmd->status = 0;
  455. ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
  456. memcpy (ias_cmd->params, dev->enetaddr, 6);
  457. /* Tell the adapter where the TX ring is located.
  458. */
  459. if (!wait_for_eepro100 (dev)) {
  460. printf ("Error: Can not reset ethernet controller.\n");
  461. goto Done;
  462. }
  463. OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
  464. OUTW (dev, SCB_M | CU_START, SCBCmd);
  465. for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
  466. i++) {
  467. if (i >= TOUT_LOOP) {
  468. printf ("%s: Tx error buffer not ready\n",
  469. dev->name);
  470. goto Done;
  471. }
  472. }
  473. if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
  474. printf ("TX error status = 0x%08X\n",
  475. le16_to_cpu (tx_ring[tx_cur].status));
  476. goto Done;
  477. }
  478. status = 0;
  479. Done:
  480. return status;
  481. }
  482. static int eepro100_send(struct eth_device *dev, void *packet, int length)
  483. {
  484. int i, status = -1;
  485. int tx_cur;
  486. if (length <= 0) {
  487. printf ("%s: bad packet size: %d\n", dev->name, length);
  488. goto Done;
  489. }
  490. tx_cur = tx_next;
  491. tx_next = (tx_next + 1) % NUM_TX_DESC;
  492. tx_ring[tx_cur].command = cpu_to_le16 ( TxCB_CMD_TRANSMIT |
  493. TxCB_CMD_SF |
  494. TxCB_CMD_S |
  495. TxCB_CMD_EL );
  496. tx_ring[tx_cur].status = 0;
  497. tx_ring[tx_cur].count = cpu_to_le32 (tx_threshold);
  498. tx_ring[tx_cur].link =
  499. cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
  500. tx_ring[tx_cur].tx_desc_addr =
  501. cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_cur].tx_buf_addr0));
  502. tx_ring[tx_cur].tx_buf_addr0 =
  503. cpu_to_le32 (phys_to_bus ((u_long) packet));
  504. tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32 (length);
  505. if (!wait_for_eepro100 (dev)) {
  506. printf ("%s: Tx error ethernet controller not ready.\n",
  507. dev->name);
  508. goto Done;
  509. }
  510. /* Send the packet.
  511. */
  512. OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
  513. OUTW (dev, SCB_M | CU_START, SCBCmd);
  514. for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
  515. i++) {
  516. if (i >= TOUT_LOOP) {
  517. printf ("%s: Tx error buffer not ready\n", dev->name);
  518. goto Done;
  519. }
  520. }
  521. if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
  522. printf ("TX error status = 0x%08X\n",
  523. le16_to_cpu (tx_ring[tx_cur].status));
  524. goto Done;
  525. }
  526. status = length;
  527. Done:
  528. return status;
  529. }
  530. static int eepro100_recv (struct eth_device *dev)
  531. {
  532. u16 status, stat;
  533. int rx_prev, length = 0;
  534. stat = INW (dev, SCBStatus);
  535. OUTW (dev, stat & SCB_STATUS_RNR, SCBStatus);
  536. for (;;) {
  537. status = le16_to_cpu (rx_ring[rx_next].status);
  538. if (!(status & RFD_STATUS_C)) {
  539. break;
  540. }
  541. /* Valid frame status.
  542. */
  543. if ((status & RFD_STATUS_OK)) {
  544. /* A valid frame received.
  545. */
  546. length = le32_to_cpu (rx_ring[rx_next].count) & 0x3fff;
  547. /* Pass the packet up to the protocol
  548. * layers.
  549. */
  550. net_process_received_packet((u8 *)rx_ring[rx_next].data,
  551. length);
  552. } else {
  553. /* There was an error.
  554. */
  555. printf ("RX error status = 0x%08X\n", status);
  556. }
  557. rx_ring[rx_next].control = cpu_to_le16 (RFD_CONTROL_S);
  558. rx_ring[rx_next].status = 0;
  559. rx_ring[rx_next].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
  560. rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC;
  561. rx_ring[rx_prev].control = 0;
  562. /* Update entry information.
  563. */
  564. rx_next = (rx_next + 1) % NUM_RX_DESC;
  565. }
  566. if (stat & SCB_STATUS_RNR) {
  567. printf ("%s: Receiver is not ready, restart it !\n", dev->name);
  568. /* Reinitialize Rx ring.
  569. */
  570. init_rx_ring (dev);
  571. if (!wait_for_eepro100 (dev)) {
  572. printf ("Error: Can not restart ethernet controller.\n");
  573. goto Done;
  574. }
  575. OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
  576. OUTW (dev, SCB_M | RUC_START, SCBCmd);
  577. }
  578. Done:
  579. return length;
  580. }
  581. static void eepro100_halt (struct eth_device *dev)
  582. {
  583. /* Reset the ethernet controller
  584. */
  585. OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
  586. udelay (20);
  587. OUTL (dev, I82559_RESET, SCBPort);
  588. udelay (20);
  589. if (!wait_for_eepro100 (dev)) {
  590. printf ("Error: Can not reset ethernet controller.\n");
  591. goto Done;
  592. }
  593. OUTL (dev, 0, SCBPointer);
  594. OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
  595. if (!wait_for_eepro100 (dev)) {
  596. printf ("Error: Can not reset ethernet controller.\n");
  597. goto Done;
  598. }
  599. OUTL (dev, 0, SCBPointer);
  600. OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
  601. Done:
  602. return;
  603. }
  604. /* SROM Read.
  605. */
  606. static int read_eeprom (struct eth_device *dev, int location, int addr_len)
  607. {
  608. unsigned short retval = 0;
  609. int read_cmd = location | EE_READ_CMD;
  610. int i;
  611. OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
  612. OUTW (dev, EE_ENB, SCBeeprom);
  613. /* Shift the read command bits out. */
  614. for (i = 12; i >= 0; i--) {
  615. short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
  616. OUTW (dev, EE_ENB | dataval, SCBeeprom);
  617. udelay (1);
  618. OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
  619. udelay (1);
  620. }
  621. OUTW (dev, EE_ENB, SCBeeprom);
  622. for (i = 15; i >= 0; i--) {
  623. OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom);
  624. udelay (1);
  625. retval = (retval << 1) |
  626. ((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0);
  627. OUTW (dev, EE_ENB, SCBeeprom);
  628. udelay (1);
  629. }
  630. /* Terminate the EEPROM access. */
  631. OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
  632. return retval;
  633. }
  634. #ifdef CONFIG_EEPRO100_SROM_WRITE
  635. int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, unsigned short data)
  636. {
  637. unsigned short dataval;
  638. int enable_cmd = 0x3f | EE_EWENB_CMD;
  639. int write_cmd = location | EE_WRITE_CMD;
  640. int i;
  641. unsigned long datalong, tmplong;
  642. OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
  643. udelay(1);
  644. OUTW(dev, EE_ENB, SCBeeprom);
  645. /* Shift the enable command bits out. */
  646. for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
  647. {
  648. dataval = (enable_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
  649. OUTW(dev, EE_ENB | dataval, SCBeeprom);
  650. udelay(1);
  651. OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
  652. udelay(1);
  653. }
  654. OUTW(dev, EE_ENB, SCBeeprom);
  655. udelay(1);
  656. OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
  657. udelay(1);
  658. OUTW(dev, EE_ENB, SCBeeprom);
  659. /* Shift the write command bits out. */
  660. for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
  661. {
  662. dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
  663. OUTW(dev, EE_ENB | dataval, SCBeeprom);
  664. udelay(1);
  665. OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
  666. udelay(1);
  667. }
  668. /* Write the data */
  669. datalong= (unsigned long) ((((data) & 0x00ff) << 8) | ( (data) >> 8));
  670. for (i = 0; i< EE_DATA_BITS; i++)
  671. {
  672. /* Extract and move data bit to bit DI */
  673. dataval = ((datalong & 0x8000)>>13) ? EE_DATA_WRITE : 0;
  674. OUTW(dev, EE_ENB | dataval, SCBeeprom);
  675. udelay(1);
  676. OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
  677. udelay(1);
  678. OUTW(dev, EE_ENB | dataval, SCBeeprom);
  679. udelay(1);
  680. datalong = datalong << 1; /* Adjust significant data bit*/
  681. }
  682. /* Finish up command (toggle CS) */
  683. OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
  684. udelay(1); /* delay for more than 250 ns */
  685. OUTW(dev, EE_ENB, SCBeeprom);
  686. /* Wait for programming ready (D0 = 1) */
  687. tmplong = 10;
  688. do
  689. {
  690. dataval = INW(dev, SCBeeprom);
  691. if (dataval & EE_DATA_READ)
  692. break;
  693. udelay(10000);
  694. }
  695. while (-- tmplong);
  696. if (tmplong == 0)
  697. {
  698. printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n");
  699. return -1;
  700. }
  701. /* Terminate the EEPROM access. */
  702. OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
  703. return 0;
  704. }
  705. #endif
  706. static void init_rx_ring (struct eth_device *dev)
  707. {
  708. int i;
  709. for (i = 0; i < NUM_RX_DESC; i++) {
  710. rx_ring[i].status = 0;
  711. rx_ring[i].control =
  712. (i == NUM_RX_DESC - 1) ? cpu_to_le16 (RFD_CONTROL_S) : 0;
  713. rx_ring[i].link =
  714. cpu_to_le32 (phys_to_bus
  715. ((u32) & rx_ring[(i + 1) % NUM_RX_DESC]));
  716. rx_ring[i].rx_buf_addr = 0xffffffff;
  717. rx_ring[i].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
  718. }
  719. rx_next = 0;
  720. }
  721. static void purge_tx_ring (struct eth_device *dev)
  722. {
  723. int i;
  724. tx_next = 0;
  725. tx_threshold = 0x01208000;
  726. for (i = 0; i < NUM_TX_DESC; i++) {
  727. tx_ring[i].status = 0;
  728. tx_ring[i].command = 0;
  729. tx_ring[i].link = 0;
  730. tx_ring[i].tx_desc_addr = 0;
  731. tx_ring[i].count = 0;
  732. tx_ring[i].tx_buf_addr0 = 0;
  733. tx_ring[i].tx_buf_size0 = 0;
  734. tx_ring[i].tx_buf_addr1 = 0;
  735. tx_ring[i].tx_buf_size1 = 0;
  736. }
  737. }
  738. static void read_hw_addr (struct eth_device *dev, bd_t * bis)
  739. {
  740. u16 sum = 0;
  741. int i, j;
  742. int addr_len = read_eeprom (dev, 0, 6) == 0xffff ? 8 : 6;
  743. for (j = 0, i = 0; i < 0x40; i++) {
  744. u16 value = read_eeprom (dev, i, addr_len);
  745. sum += value;
  746. if (i < 3) {
  747. dev->enetaddr[j++] = value;
  748. dev->enetaddr[j++] = value >> 8;
  749. }
  750. }
  751. if (sum != 0xBABA) {
  752. memset (dev->enetaddr, 0, ETH_ALEN);
  753. #ifdef DEBUG
  754. printf ("%s: Invalid EEPROM checksum %#4.4x, "
  755. "check settings before activating this device!\n",
  756. dev->name, sum);
  757. #endif
  758. }
  759. }