e1000.c 170 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /**************************************************************************
  3. Intel Pro 1000 for ppcboot/das-u-boot
  4. Drivers are port from Intel's Linux driver e1000-4.3.15
  5. and from Etherboot pro 1000 driver by mrakes at vivato dot net
  6. tested on both gig copper and gig fiber boards
  7. ***************************************************************************/
  8. /*******************************************************************************
  9. Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
  10. Contact Information:
  11. Linux NICS <linux.nics@intel.com>
  12. Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  13. *******************************************************************************/
  14. /*
  15. * Copyright (C) Archway Digital Solutions.
  16. *
  17. * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
  18. * 2/9/2002
  19. *
  20. * Copyright (C) Linux Networx.
  21. * Massive upgrade to work with the new intel gigabit NICs.
  22. * <ebiederman at lnxi dot com>
  23. *
  24. * Copyright 2011 Freescale Semiconductor, Inc.
  25. */
  26. #include <common.h>
  27. #include <dm.h>
  28. #include <errno.h>
  29. #include <memalign.h>
  30. #include <pci.h>
  31. #include "e1000.h"
  32. #define TOUT_LOOP 100000
  33. #ifdef CONFIG_DM_ETH
  34. #define virt_to_bus(devno, v) dm_pci_virt_to_mem(devno, (void *) (v))
  35. #define bus_to_phys(devno, a) dm_pci_mem_to_phys(devno, a)
  36. #else
  37. #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
  38. #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
  39. #endif
  40. #define E1000_DEFAULT_PCI_PBA 0x00000030
  41. #define E1000_DEFAULT_PCIE_PBA 0x000a0026
  42. /* NIC specific static variables go here */
  43. /* Intel i210 needs the DMA descriptor rings aligned to 128b */
  44. #define E1000_BUFFER_ALIGN 128
  45. /*
  46. * TODO(sjg@chromium.org): Even with driver model we share these buffers.
  47. * Concurrent receiving on multiple active Ethernet devices will not work.
  48. * Normally U-Boot does not support this anyway. To fix it in this driver,
  49. * move these buffers and the tx/rx pointers to struct e1000_hw.
  50. */
  51. DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN);
  52. DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN);
  53. DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN);
  54. static int tx_tail;
  55. static int rx_tail, rx_last;
  56. #ifdef CONFIG_DM_ETH
  57. static int num_cards; /* Number of E1000 devices seen so far */
  58. #endif
  59. static struct pci_device_id e1000_supported[] = {
  60. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) },
  61. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER) },
  62. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER) },
  63. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER) },
  64. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER) },
  65. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER) },
  66. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM) },
  67. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM) },
  68. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER) },
  69. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER) },
  70. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER) },
  71. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER) },
  72. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER) },
  73. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER) },
  74. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM) },
  75. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER) },
  76. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF) },
  77. /* E1000 PCIe card */
  78. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER) },
  79. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER) },
  80. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES) },
  81. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER) },
  82. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER) },
  83. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER) },
  84. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE) },
  85. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL) },
  86. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD) },
  87. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER) },
  88. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER) },
  89. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES) },
  90. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI) },
  91. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E) },
  92. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT) },
  93. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L) },
  94. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L) },
  95. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3) },
  96. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT) },
  97. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) },
  98. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) },
  99. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) },
  100. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) },
  101. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) },
  102. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) },
  103. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER) },
  104. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS) },
  105. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) },
  106. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) },
  107. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) },
  108. {}
  109. };
  110. /* Function forward declarations */
  111. static int e1000_setup_link(struct e1000_hw *hw);
  112. static int e1000_setup_fiber_link(struct e1000_hw *hw);
  113. static int e1000_setup_copper_link(struct e1000_hw *hw);
  114. static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
  115. static void e1000_config_collision_dist(struct e1000_hw *hw);
  116. static int e1000_config_mac_to_phy(struct e1000_hw *hw);
  117. static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
  118. static int e1000_check_for_link(struct e1000_hw *hw);
  119. static int e1000_wait_autoneg(struct e1000_hw *hw);
  120. static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
  121. uint16_t * duplex);
  122. static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
  123. uint16_t * phy_data);
  124. static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
  125. uint16_t phy_data);
  126. static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
  127. static int e1000_phy_reset(struct e1000_hw *hw);
  128. static int e1000_detect_gig_phy(struct e1000_hw *hw);
  129. static void e1000_set_media_type(struct e1000_hw *hw);
  130. static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
  131. static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
  132. static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
  133. #ifndef CONFIG_E1000_NO_NVM
  134. static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
  135. static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
  136. static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
  137. uint16_t words,
  138. uint16_t *data);
  139. /******************************************************************************
  140. * Raises the EEPROM's clock input.
  141. *
  142. * hw - Struct containing variables accessed by shared code
  143. * eecd - EECD's current value
  144. *****************************************************************************/
  145. void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
  146. {
  147. /* Raise the clock input to the EEPROM (by setting the SK bit), and then
  148. * wait 50 microseconds.
  149. */
  150. *eecd = *eecd | E1000_EECD_SK;
  151. E1000_WRITE_REG(hw, EECD, *eecd);
  152. E1000_WRITE_FLUSH(hw);
  153. udelay(50);
  154. }
  155. /******************************************************************************
  156. * Lowers the EEPROM's clock input.
  157. *
  158. * hw - Struct containing variables accessed by shared code
  159. * eecd - EECD's current value
  160. *****************************************************************************/
  161. void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
  162. {
  163. /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
  164. * wait 50 microseconds.
  165. */
  166. *eecd = *eecd & ~E1000_EECD_SK;
  167. E1000_WRITE_REG(hw, EECD, *eecd);
  168. E1000_WRITE_FLUSH(hw);
  169. udelay(50);
  170. }
  171. /******************************************************************************
  172. * Shift data bits out to the EEPROM.
  173. *
  174. * hw - Struct containing variables accessed by shared code
  175. * data - data to send to the EEPROM
  176. * count - number of bits to shift out
  177. *****************************************************************************/
  178. static void
  179. e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
  180. {
  181. uint32_t eecd;
  182. uint32_t mask;
  183. /* We need to shift "count" bits out to the EEPROM. So, value in the
  184. * "data" parameter will be shifted out to the EEPROM one bit at a time.
  185. * In order to do this, "data" must be broken down into bits.
  186. */
  187. mask = 0x01 << (count - 1);
  188. eecd = E1000_READ_REG(hw, EECD);
  189. eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
  190. do {
  191. /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
  192. * and then raising and then lowering the clock (the SK bit controls
  193. * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
  194. * by setting "DI" to "0" and then raising and then lowering the clock.
  195. */
  196. eecd &= ~E1000_EECD_DI;
  197. if (data & mask)
  198. eecd |= E1000_EECD_DI;
  199. E1000_WRITE_REG(hw, EECD, eecd);
  200. E1000_WRITE_FLUSH(hw);
  201. udelay(50);
  202. e1000_raise_ee_clk(hw, &eecd);
  203. e1000_lower_ee_clk(hw, &eecd);
  204. mask = mask >> 1;
  205. } while (mask);
  206. /* We leave the "DI" bit set to "0" when we leave this routine. */
  207. eecd &= ~E1000_EECD_DI;
  208. E1000_WRITE_REG(hw, EECD, eecd);
  209. }
  210. /******************************************************************************
  211. * Shift data bits in from the EEPROM
  212. *
  213. * hw - Struct containing variables accessed by shared code
  214. *****************************************************************************/
  215. static uint16_t
  216. e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
  217. {
  218. uint32_t eecd;
  219. uint32_t i;
  220. uint16_t data;
  221. /* In order to read a register from the EEPROM, we need to shift 'count'
  222. * bits in from the EEPROM. Bits are "shifted in" by raising the clock
  223. * input to the EEPROM (setting the SK bit), and then reading the
  224. * value of the "DO" bit. During this "shifting in" process the
  225. * "DI" bit should always be clear.
  226. */
  227. eecd = E1000_READ_REG(hw, EECD);
  228. eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
  229. data = 0;
  230. for (i = 0; i < count; i++) {
  231. data = data << 1;
  232. e1000_raise_ee_clk(hw, &eecd);
  233. eecd = E1000_READ_REG(hw, EECD);
  234. eecd &= ~(E1000_EECD_DI);
  235. if (eecd & E1000_EECD_DO)
  236. data |= 1;
  237. e1000_lower_ee_clk(hw, &eecd);
  238. }
  239. return data;
  240. }
  241. /******************************************************************************
  242. * Returns EEPROM to a "standby" state
  243. *
  244. * hw - Struct containing variables accessed by shared code
  245. *****************************************************************************/
  246. void e1000_standby_eeprom(struct e1000_hw *hw)
  247. {
  248. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  249. uint32_t eecd;
  250. eecd = E1000_READ_REG(hw, EECD);
  251. if (eeprom->type == e1000_eeprom_microwire) {
  252. eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
  253. E1000_WRITE_REG(hw, EECD, eecd);
  254. E1000_WRITE_FLUSH(hw);
  255. udelay(eeprom->delay_usec);
  256. /* Clock high */
  257. eecd |= E1000_EECD_SK;
  258. E1000_WRITE_REG(hw, EECD, eecd);
  259. E1000_WRITE_FLUSH(hw);
  260. udelay(eeprom->delay_usec);
  261. /* Select EEPROM */
  262. eecd |= E1000_EECD_CS;
  263. E1000_WRITE_REG(hw, EECD, eecd);
  264. E1000_WRITE_FLUSH(hw);
  265. udelay(eeprom->delay_usec);
  266. /* Clock low */
  267. eecd &= ~E1000_EECD_SK;
  268. E1000_WRITE_REG(hw, EECD, eecd);
  269. E1000_WRITE_FLUSH(hw);
  270. udelay(eeprom->delay_usec);
  271. } else if (eeprom->type == e1000_eeprom_spi) {
  272. /* Toggle CS to flush commands */
  273. eecd |= E1000_EECD_CS;
  274. E1000_WRITE_REG(hw, EECD, eecd);
  275. E1000_WRITE_FLUSH(hw);
  276. udelay(eeprom->delay_usec);
  277. eecd &= ~E1000_EECD_CS;
  278. E1000_WRITE_REG(hw, EECD, eecd);
  279. E1000_WRITE_FLUSH(hw);
  280. udelay(eeprom->delay_usec);
  281. }
  282. }
  283. /***************************************************************************
  284. * Description: Determines if the onboard NVM is FLASH or EEPROM.
  285. *
  286. * hw - Struct containing variables accessed by shared code
  287. ****************************************************************************/
  288. static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
  289. {
  290. uint32_t eecd = 0;
  291. DEBUGFUNC();
  292. if (hw->mac_type == e1000_ich8lan)
  293. return false;
  294. if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
  295. eecd = E1000_READ_REG(hw, EECD);
  296. /* Isolate bits 15 & 16 */
  297. eecd = ((eecd >> 15) & 0x03);
  298. /* If both bits are set, device is Flash type */
  299. if (eecd == 0x03)
  300. return false;
  301. }
  302. return true;
  303. }
  304. /******************************************************************************
  305. * Prepares EEPROM for access
  306. *
  307. * hw - Struct containing variables accessed by shared code
  308. *
  309. * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
  310. * function should be called before issuing a command to the EEPROM.
  311. *****************************************************************************/
  312. int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
  313. {
  314. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  315. uint32_t eecd, i = 0;
  316. DEBUGFUNC();
  317. if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
  318. return -E1000_ERR_SWFW_SYNC;
  319. eecd = E1000_READ_REG(hw, EECD);
  320. if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) {
  321. /* Request EEPROM Access */
  322. if (hw->mac_type > e1000_82544) {
  323. eecd |= E1000_EECD_REQ;
  324. E1000_WRITE_REG(hw, EECD, eecd);
  325. eecd = E1000_READ_REG(hw, EECD);
  326. while ((!(eecd & E1000_EECD_GNT)) &&
  327. (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
  328. i++;
  329. udelay(5);
  330. eecd = E1000_READ_REG(hw, EECD);
  331. }
  332. if (!(eecd & E1000_EECD_GNT)) {
  333. eecd &= ~E1000_EECD_REQ;
  334. E1000_WRITE_REG(hw, EECD, eecd);
  335. DEBUGOUT("Could not acquire EEPROM grant\n");
  336. return -E1000_ERR_EEPROM;
  337. }
  338. }
  339. }
  340. /* Setup EEPROM for Read/Write */
  341. if (eeprom->type == e1000_eeprom_microwire) {
  342. /* Clear SK and DI */
  343. eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
  344. E1000_WRITE_REG(hw, EECD, eecd);
  345. /* Set CS */
  346. eecd |= E1000_EECD_CS;
  347. E1000_WRITE_REG(hw, EECD, eecd);
  348. } else if (eeprom->type == e1000_eeprom_spi) {
  349. /* Clear SK and CS */
  350. eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
  351. E1000_WRITE_REG(hw, EECD, eecd);
  352. udelay(1);
  353. }
  354. return E1000_SUCCESS;
  355. }
  356. /******************************************************************************
  357. * Sets up eeprom variables in the hw struct. Must be called after mac_type
  358. * is configured. Additionally, if this is ICH8, the flash controller GbE
  359. * registers must be mapped, or this will crash.
  360. *
  361. * hw - Struct containing variables accessed by shared code
  362. *****************************************************************************/
  363. static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
  364. {
  365. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  366. uint32_t eecd;
  367. int32_t ret_val = E1000_SUCCESS;
  368. uint16_t eeprom_size;
  369. if (hw->mac_type == e1000_igb)
  370. eecd = E1000_READ_REG(hw, I210_EECD);
  371. else
  372. eecd = E1000_READ_REG(hw, EECD);
  373. DEBUGFUNC();
  374. switch (hw->mac_type) {
  375. case e1000_82542_rev2_0:
  376. case e1000_82542_rev2_1:
  377. case e1000_82543:
  378. case e1000_82544:
  379. eeprom->type = e1000_eeprom_microwire;
  380. eeprom->word_size = 64;
  381. eeprom->opcode_bits = 3;
  382. eeprom->address_bits = 6;
  383. eeprom->delay_usec = 50;
  384. eeprom->use_eerd = false;
  385. eeprom->use_eewr = false;
  386. break;
  387. case e1000_82540:
  388. case e1000_82545:
  389. case e1000_82545_rev_3:
  390. case e1000_82546:
  391. case e1000_82546_rev_3:
  392. eeprom->type = e1000_eeprom_microwire;
  393. eeprom->opcode_bits = 3;
  394. eeprom->delay_usec = 50;
  395. if (eecd & E1000_EECD_SIZE) {
  396. eeprom->word_size = 256;
  397. eeprom->address_bits = 8;
  398. } else {
  399. eeprom->word_size = 64;
  400. eeprom->address_bits = 6;
  401. }
  402. eeprom->use_eerd = false;
  403. eeprom->use_eewr = false;
  404. break;
  405. case e1000_82541:
  406. case e1000_82541_rev_2:
  407. case e1000_82547:
  408. case e1000_82547_rev_2:
  409. if (eecd & E1000_EECD_TYPE) {
  410. eeprom->type = e1000_eeprom_spi;
  411. eeprom->opcode_bits = 8;
  412. eeprom->delay_usec = 1;
  413. if (eecd & E1000_EECD_ADDR_BITS) {
  414. eeprom->page_size = 32;
  415. eeprom->address_bits = 16;
  416. } else {
  417. eeprom->page_size = 8;
  418. eeprom->address_bits = 8;
  419. }
  420. } else {
  421. eeprom->type = e1000_eeprom_microwire;
  422. eeprom->opcode_bits = 3;
  423. eeprom->delay_usec = 50;
  424. if (eecd & E1000_EECD_ADDR_BITS) {
  425. eeprom->word_size = 256;
  426. eeprom->address_bits = 8;
  427. } else {
  428. eeprom->word_size = 64;
  429. eeprom->address_bits = 6;
  430. }
  431. }
  432. eeprom->use_eerd = false;
  433. eeprom->use_eewr = false;
  434. break;
  435. case e1000_82571:
  436. case e1000_82572:
  437. eeprom->type = e1000_eeprom_spi;
  438. eeprom->opcode_bits = 8;
  439. eeprom->delay_usec = 1;
  440. if (eecd & E1000_EECD_ADDR_BITS) {
  441. eeprom->page_size = 32;
  442. eeprom->address_bits = 16;
  443. } else {
  444. eeprom->page_size = 8;
  445. eeprom->address_bits = 8;
  446. }
  447. eeprom->use_eerd = false;
  448. eeprom->use_eewr = false;
  449. break;
  450. case e1000_82573:
  451. case e1000_82574:
  452. eeprom->type = e1000_eeprom_spi;
  453. eeprom->opcode_bits = 8;
  454. eeprom->delay_usec = 1;
  455. if (eecd & E1000_EECD_ADDR_BITS) {
  456. eeprom->page_size = 32;
  457. eeprom->address_bits = 16;
  458. } else {
  459. eeprom->page_size = 8;
  460. eeprom->address_bits = 8;
  461. }
  462. if (e1000_is_onboard_nvm_eeprom(hw) == false) {
  463. eeprom->use_eerd = true;
  464. eeprom->use_eewr = true;
  465. eeprom->type = e1000_eeprom_flash;
  466. eeprom->word_size = 2048;
  467. /* Ensure that the Autonomous FLASH update bit is cleared due to
  468. * Flash update issue on parts which use a FLASH for NVM. */
  469. eecd &= ~E1000_EECD_AUPDEN;
  470. E1000_WRITE_REG(hw, EECD, eecd);
  471. }
  472. break;
  473. case e1000_80003es2lan:
  474. eeprom->type = e1000_eeprom_spi;
  475. eeprom->opcode_bits = 8;
  476. eeprom->delay_usec = 1;
  477. if (eecd & E1000_EECD_ADDR_BITS) {
  478. eeprom->page_size = 32;
  479. eeprom->address_bits = 16;
  480. } else {
  481. eeprom->page_size = 8;
  482. eeprom->address_bits = 8;
  483. }
  484. eeprom->use_eerd = true;
  485. eeprom->use_eewr = false;
  486. break;
  487. case e1000_igb:
  488. /* i210 has 4k of iNVM mapped as EEPROM */
  489. eeprom->type = e1000_eeprom_invm;
  490. eeprom->opcode_bits = 8;
  491. eeprom->delay_usec = 1;
  492. eeprom->page_size = 32;
  493. eeprom->address_bits = 16;
  494. eeprom->use_eerd = true;
  495. eeprom->use_eewr = false;
  496. break;
  497. default:
  498. break;
  499. }
  500. if (eeprom->type == e1000_eeprom_spi ||
  501. eeprom->type == e1000_eeprom_invm) {
  502. /* eeprom_size will be an enum [0..8] that maps
  503. * to eeprom sizes 128B to
  504. * 32KB (incremented by powers of 2).
  505. */
  506. if (hw->mac_type <= e1000_82547_rev_2) {
  507. /* Set to default value for initial eeprom read. */
  508. eeprom->word_size = 64;
  509. ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
  510. &eeprom_size);
  511. if (ret_val)
  512. return ret_val;
  513. eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
  514. >> EEPROM_SIZE_SHIFT;
  515. /* 256B eeprom size was not supported in earlier
  516. * hardware, so we bump eeprom_size up one to
  517. * ensure that "1" (which maps to 256B) is never
  518. * the result used in the shifting logic below. */
  519. if (eeprom_size)
  520. eeprom_size++;
  521. } else {
  522. eeprom_size = (uint16_t)((eecd &
  523. E1000_EECD_SIZE_EX_MASK) >>
  524. E1000_EECD_SIZE_EX_SHIFT);
  525. }
  526. eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
  527. }
  528. return ret_val;
  529. }
  530. /******************************************************************************
  531. * Polls the status bit (bit 1) of the EERD to determine when the read is done.
  532. *
  533. * hw - Struct containing variables accessed by shared code
  534. *****************************************************************************/
  535. static int32_t
  536. e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
  537. {
  538. uint32_t attempts = 100000;
  539. uint32_t i, reg = 0;
  540. int32_t done = E1000_ERR_EEPROM;
  541. for (i = 0; i < attempts; i++) {
  542. if (eerd == E1000_EEPROM_POLL_READ) {
  543. if (hw->mac_type == e1000_igb)
  544. reg = E1000_READ_REG(hw, I210_EERD);
  545. else
  546. reg = E1000_READ_REG(hw, EERD);
  547. } else {
  548. if (hw->mac_type == e1000_igb)
  549. reg = E1000_READ_REG(hw, I210_EEWR);
  550. else
  551. reg = E1000_READ_REG(hw, EEWR);
  552. }
  553. if (reg & E1000_EEPROM_RW_REG_DONE) {
  554. done = E1000_SUCCESS;
  555. break;
  556. }
  557. udelay(5);
  558. }
  559. return done;
  560. }
  561. /******************************************************************************
  562. * Reads a 16 bit word from the EEPROM using the EERD register.
  563. *
  564. * hw - Struct containing variables accessed by shared code
  565. * offset - offset of word in the EEPROM to read
  566. * data - word read from the EEPROM
  567. * words - number of words to read
  568. *****************************************************************************/
  569. static int32_t
  570. e1000_read_eeprom_eerd(struct e1000_hw *hw,
  571. uint16_t offset,
  572. uint16_t words,
  573. uint16_t *data)
  574. {
  575. uint32_t i, eerd = 0;
  576. int32_t error = 0;
  577. for (i = 0; i < words; i++) {
  578. eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
  579. E1000_EEPROM_RW_REG_START;
  580. if (hw->mac_type == e1000_igb)
  581. E1000_WRITE_REG(hw, I210_EERD, eerd);
  582. else
  583. E1000_WRITE_REG(hw, EERD, eerd);
  584. error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
  585. if (error)
  586. break;
  587. if (hw->mac_type == e1000_igb) {
  588. data[i] = (E1000_READ_REG(hw, I210_EERD) >>
  589. E1000_EEPROM_RW_REG_DATA);
  590. } else {
  591. data[i] = (E1000_READ_REG(hw, EERD) >>
  592. E1000_EEPROM_RW_REG_DATA);
  593. }
  594. }
  595. return error;
  596. }
  597. void e1000_release_eeprom(struct e1000_hw *hw)
  598. {
  599. uint32_t eecd;
  600. DEBUGFUNC();
  601. eecd = E1000_READ_REG(hw, EECD);
  602. if (hw->eeprom.type == e1000_eeprom_spi) {
  603. eecd |= E1000_EECD_CS; /* Pull CS high */
  604. eecd &= ~E1000_EECD_SK; /* Lower SCK */
  605. E1000_WRITE_REG(hw, EECD, eecd);
  606. udelay(hw->eeprom.delay_usec);
  607. } else if (hw->eeprom.type == e1000_eeprom_microwire) {
  608. /* cleanup eeprom */
  609. /* CS on Microwire is active-high */
  610. eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
  611. E1000_WRITE_REG(hw, EECD, eecd);
  612. /* Rising edge of clock */
  613. eecd |= E1000_EECD_SK;
  614. E1000_WRITE_REG(hw, EECD, eecd);
  615. E1000_WRITE_FLUSH(hw);
  616. udelay(hw->eeprom.delay_usec);
  617. /* Falling edge of clock */
  618. eecd &= ~E1000_EECD_SK;
  619. E1000_WRITE_REG(hw, EECD, eecd);
  620. E1000_WRITE_FLUSH(hw);
  621. udelay(hw->eeprom.delay_usec);
  622. }
  623. /* Stop requesting EEPROM access */
  624. if (hw->mac_type > e1000_82544) {
  625. eecd &= ~E1000_EECD_REQ;
  626. E1000_WRITE_REG(hw, EECD, eecd);
  627. }
  628. e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
  629. }
  630. /******************************************************************************
  631. * Reads a 16 bit word from the EEPROM.
  632. *
  633. * hw - Struct containing variables accessed by shared code
  634. *****************************************************************************/
  635. static int32_t
  636. e1000_spi_eeprom_ready(struct e1000_hw *hw)
  637. {
  638. uint16_t retry_count = 0;
  639. uint8_t spi_stat_reg;
  640. DEBUGFUNC();
  641. /* Read "Status Register" repeatedly until the LSB is cleared. The
  642. * EEPROM will signal that the command has been completed by clearing
  643. * bit 0 of the internal status register. If it's not cleared within
  644. * 5 milliseconds, then error out.
  645. */
  646. retry_count = 0;
  647. do {
  648. e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
  649. hw->eeprom.opcode_bits);
  650. spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
  651. if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
  652. break;
  653. udelay(5);
  654. retry_count += 5;
  655. e1000_standby_eeprom(hw);
  656. } while (retry_count < EEPROM_MAX_RETRY_SPI);
  657. /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
  658. * only 0-5mSec on 5V devices)
  659. */
  660. if (retry_count >= EEPROM_MAX_RETRY_SPI) {
  661. DEBUGOUT("SPI EEPROM Status error\n");
  662. return -E1000_ERR_EEPROM;
  663. }
  664. return E1000_SUCCESS;
  665. }
  666. /******************************************************************************
  667. * Reads a 16 bit word from the EEPROM.
  668. *
  669. * hw - Struct containing variables accessed by shared code
  670. * offset - offset of word in the EEPROM to read
  671. * data - word read from the EEPROM
  672. *****************************************************************************/
  673. static int32_t
  674. e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
  675. uint16_t words, uint16_t *data)
  676. {
  677. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  678. uint32_t i = 0;
  679. DEBUGFUNC();
  680. /* If eeprom is not yet detected, do so now */
  681. if (eeprom->word_size == 0)
  682. e1000_init_eeprom_params(hw);
  683. /* A check for invalid values: offset too large, too many words,
  684. * and not enough words.
  685. */
  686. if ((offset >= eeprom->word_size) ||
  687. (words > eeprom->word_size - offset) ||
  688. (words == 0)) {
  689. DEBUGOUT("\"words\" parameter out of bounds."
  690. "Words = %d, size = %d\n", offset, eeprom->word_size);
  691. return -E1000_ERR_EEPROM;
  692. }
  693. /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
  694. * directly. In this case, we need to acquire the EEPROM so that
  695. * FW or other port software does not interrupt.
  696. */
  697. if (e1000_is_onboard_nvm_eeprom(hw) == true &&
  698. hw->eeprom.use_eerd == false) {
  699. /* Prepare the EEPROM for bit-bang reading */
  700. if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
  701. return -E1000_ERR_EEPROM;
  702. }
  703. /* Eerd register EEPROM access requires no eeprom aquire/release */
  704. if (eeprom->use_eerd == true)
  705. return e1000_read_eeprom_eerd(hw, offset, words, data);
  706. /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
  707. * acquired the EEPROM at this point, so any returns should relase it */
  708. if (eeprom->type == e1000_eeprom_spi) {
  709. uint16_t word_in;
  710. uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
  711. if (e1000_spi_eeprom_ready(hw)) {
  712. e1000_release_eeprom(hw);
  713. return -E1000_ERR_EEPROM;
  714. }
  715. e1000_standby_eeprom(hw);
  716. /* Some SPI eeproms use the 8th address bit embedded in
  717. * the opcode */
  718. if ((eeprom->address_bits == 8) && (offset >= 128))
  719. read_opcode |= EEPROM_A8_OPCODE_SPI;
  720. /* Send the READ command (opcode + addr) */
  721. e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
  722. e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
  723. eeprom->address_bits);
  724. /* Read the data. The address of the eeprom internally
  725. * increments with each byte (spi) being read, saving on the
  726. * overhead of eeprom setup and tear-down. The address
  727. * counter will roll over if reading beyond the size of
  728. * the eeprom, thus allowing the entire memory to be read
  729. * starting from any offset. */
  730. for (i = 0; i < words; i++) {
  731. word_in = e1000_shift_in_ee_bits(hw, 16);
  732. data[i] = (word_in >> 8) | (word_in << 8);
  733. }
  734. } else if (eeprom->type == e1000_eeprom_microwire) {
  735. for (i = 0; i < words; i++) {
  736. /* Send the READ command (opcode + addr) */
  737. e1000_shift_out_ee_bits(hw,
  738. EEPROM_READ_OPCODE_MICROWIRE,
  739. eeprom->opcode_bits);
  740. e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
  741. eeprom->address_bits);
  742. /* Read the data. For microwire, each word requires
  743. * the overhead of eeprom setup and tear-down. */
  744. data[i] = e1000_shift_in_ee_bits(hw, 16);
  745. e1000_standby_eeprom(hw);
  746. }
  747. }
  748. /* End this read operation */
  749. e1000_release_eeprom(hw);
  750. return E1000_SUCCESS;
  751. }
  752. #ifndef CONFIG_DM_ETH
  753. /******************************************************************************
  754. * e1000_write_eeprom_srwr - Write to Shadow Ram using EEWR
  755. * @hw: pointer to the HW structure
  756. * @offset: offset within the Shadow Ram to be written to
  757. * @words: number of words to write
  758. * @data: 16 bit word(s) to be written to the Shadow Ram
  759. *
  760. * Writes data to Shadow Ram at offset using EEWR register.
  761. *
  762. * If e1000_update_eeprom_checksum_i210 is not called after this function, the
  763. * Shadow Ram will most likely contain an invalid checksum.
  764. *****************************************************************************/
  765. static int32_t e1000_write_eeprom_srwr(struct e1000_hw *hw, uint16_t offset,
  766. uint16_t words, uint16_t *data)
  767. {
  768. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  769. uint32_t i, k, eewr = 0;
  770. uint32_t attempts = 100000;
  771. int32_t ret_val = 0;
  772. /* A check for invalid values: offset too large, too many words,
  773. * too many words for the offset, and not enough words.
  774. */
  775. if ((offset >= eeprom->word_size) ||
  776. (words > (eeprom->word_size - offset)) || (words == 0)) {
  777. DEBUGOUT("nvm parameter(s) out of bounds\n");
  778. ret_val = -E1000_ERR_EEPROM;
  779. goto out;
  780. }
  781. for (i = 0; i < words; i++) {
  782. eewr = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT)
  783. | (data[i] << E1000_EEPROM_RW_REG_DATA) |
  784. E1000_EEPROM_RW_REG_START;
  785. E1000_WRITE_REG(hw, I210_EEWR, eewr);
  786. for (k = 0; k < attempts; k++) {
  787. if (E1000_EEPROM_RW_REG_DONE &
  788. E1000_READ_REG(hw, I210_EEWR)) {
  789. ret_val = 0;
  790. break;
  791. }
  792. udelay(5);
  793. }
  794. if (ret_val) {
  795. DEBUGOUT("Shadow RAM write EEWR timed out\n");
  796. break;
  797. }
  798. }
  799. out:
  800. return ret_val;
  801. }
  802. /******************************************************************************
  803. * e1000_pool_flash_update_done_i210 - Pool FLUDONE status.
  804. * @hw: pointer to the HW structure
  805. *
  806. *****************************************************************************/
  807. static int32_t e1000_pool_flash_update_done_i210(struct e1000_hw *hw)
  808. {
  809. int32_t ret_val = -E1000_ERR_EEPROM;
  810. uint32_t i, reg;
  811. for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {
  812. reg = E1000_READ_REG(hw, EECD);
  813. if (reg & E1000_EECD_FLUDONE_I210) {
  814. ret_val = 0;
  815. break;
  816. }
  817. udelay(5);
  818. }
  819. return ret_val;
  820. }
  821. /******************************************************************************
  822. * e1000_update_flash_i210 - Commit EEPROM to the flash
  823. * @hw: pointer to the HW structure
  824. *
  825. *****************************************************************************/
  826. static int32_t e1000_update_flash_i210(struct e1000_hw *hw)
  827. {
  828. int32_t ret_val = 0;
  829. uint32_t flup;
  830. ret_val = e1000_pool_flash_update_done_i210(hw);
  831. if (ret_val == -E1000_ERR_EEPROM) {
  832. DEBUGOUT("Flash update time out\n");
  833. goto out;
  834. }
  835. flup = E1000_READ_REG(hw, EECD) | E1000_EECD_FLUPD_I210;
  836. E1000_WRITE_REG(hw, EECD, flup);
  837. ret_val = e1000_pool_flash_update_done_i210(hw);
  838. if (ret_val)
  839. DEBUGOUT("Flash update time out\n");
  840. else
  841. DEBUGOUT("Flash update complete\n");
  842. out:
  843. return ret_val;
  844. }
  845. /******************************************************************************
  846. * e1000_update_eeprom_checksum_i210 - Update EEPROM checksum
  847. * @hw: pointer to the HW structure
  848. *
  849. * Updates the EEPROM checksum by reading/adding each word of the EEPROM
  850. * up to the checksum. Then calculates the EEPROM checksum and writes the
  851. * value to the EEPROM. Next commit EEPROM data onto the Flash.
  852. *****************************************************************************/
  853. static int32_t e1000_update_eeprom_checksum_i210(struct e1000_hw *hw)
  854. {
  855. int32_t ret_val = 0;
  856. uint16_t checksum = 0;
  857. uint16_t i, nvm_data;
  858. /* Read the first word from the EEPROM. If this times out or fails, do
  859. * not continue or we could be in for a very long wait while every
  860. * EEPROM read fails
  861. */
  862. ret_val = e1000_read_eeprom_eerd(hw, 0, 1, &nvm_data);
  863. if (ret_val) {
  864. DEBUGOUT("EEPROM read failed\n");
  865. goto out;
  866. }
  867. if (!(e1000_get_hw_eeprom_semaphore(hw))) {
  868. /* Do not use hw->nvm.ops.write, hw->nvm.ops.read
  869. * because we do not want to take the synchronization
  870. * semaphores twice here.
  871. */
  872. for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
  873. ret_val = e1000_read_eeprom_eerd(hw, i, 1, &nvm_data);
  874. if (ret_val) {
  875. e1000_put_hw_eeprom_semaphore(hw);
  876. DEBUGOUT("EEPROM Read Error while updating checksum.\n");
  877. goto out;
  878. }
  879. checksum += nvm_data;
  880. }
  881. checksum = (uint16_t)EEPROM_SUM - checksum;
  882. ret_val = e1000_write_eeprom_srwr(hw, EEPROM_CHECKSUM_REG, 1,
  883. &checksum);
  884. if (ret_val) {
  885. e1000_put_hw_eeprom_semaphore(hw);
  886. DEBUGOUT("EEPROM Write Error while updating checksum.\n");
  887. goto out;
  888. }
  889. e1000_put_hw_eeprom_semaphore(hw);
  890. ret_val = e1000_update_flash_i210(hw);
  891. } else {
  892. ret_val = -E1000_ERR_SWFW_SYNC;
  893. }
  894. out:
  895. return ret_val;
  896. }
  897. #endif
  898. /******************************************************************************
  899. * Verifies that the EEPROM has a valid checksum
  900. *
  901. * hw - Struct containing variables accessed by shared code
  902. *
  903. * Reads the first 64 16 bit words of the EEPROM and sums the values read.
  904. * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
  905. * valid.
  906. *****************************************************************************/
  907. static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
  908. {
  909. uint16_t i, checksum, checksum_reg, *buf;
  910. DEBUGFUNC();
  911. /* Allocate a temporary buffer */
  912. buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
  913. if (!buf) {
  914. E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n");
  915. return -E1000_ERR_EEPROM;
  916. }
  917. /* Read the EEPROM */
  918. if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
  919. E1000_ERR(hw, "Unable to read EEPROM!\n");
  920. return -E1000_ERR_EEPROM;
  921. }
  922. /* Compute the checksum */
  923. checksum = 0;
  924. for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
  925. checksum += buf[i];
  926. checksum = ((uint16_t)EEPROM_SUM) - checksum;
  927. checksum_reg = buf[i];
  928. /* Verify it! */
  929. if (checksum == checksum_reg)
  930. return 0;
  931. /* Hrm, verification failed, print an error */
  932. E1000_ERR(hw, "EEPROM checksum is incorrect!\n");
  933. E1000_ERR(hw, " ...register was 0x%04hx, calculated 0x%04hx\n",
  934. checksum_reg, checksum);
  935. return -E1000_ERR_EEPROM;
  936. }
  937. #endif /* CONFIG_E1000_NO_NVM */
  938. /*****************************************************************************
  939. * Set PHY to class A mode
  940. * Assumes the following operations will follow to enable the new class mode.
  941. * 1. Do a PHY soft reset
  942. * 2. Restart auto-negotiation or force link.
  943. *
  944. * hw - Struct containing variables accessed by shared code
  945. ****************************************************************************/
  946. static int32_t
  947. e1000_set_phy_mode(struct e1000_hw *hw)
  948. {
  949. #ifndef CONFIG_E1000_NO_NVM
  950. int32_t ret_val;
  951. uint16_t eeprom_data;
  952. DEBUGFUNC();
  953. if ((hw->mac_type == e1000_82545_rev_3) &&
  954. (hw->media_type == e1000_media_type_copper)) {
  955. ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
  956. 1, &eeprom_data);
  957. if (ret_val)
  958. return ret_val;
  959. if ((eeprom_data != EEPROM_RESERVED_WORD) &&
  960. (eeprom_data & EEPROM_PHY_CLASS_A)) {
  961. ret_val = e1000_write_phy_reg(hw,
  962. M88E1000_PHY_PAGE_SELECT, 0x000B);
  963. if (ret_val)
  964. return ret_val;
  965. ret_val = e1000_write_phy_reg(hw,
  966. M88E1000_PHY_GEN_CONTROL, 0x8104);
  967. if (ret_val)
  968. return ret_val;
  969. hw->phy_reset_disable = false;
  970. }
  971. }
  972. #endif
  973. return E1000_SUCCESS;
  974. }
  975. #ifndef CONFIG_E1000_NO_NVM
  976. /***************************************************************************
  977. *
  978. * Obtaining software semaphore bit (SMBI) before resetting PHY.
  979. *
  980. * hw: Struct containing variables accessed by shared code
  981. *
  982. * returns: - E1000_ERR_RESET if fail to obtain semaphore.
  983. * E1000_SUCCESS at any other case.
  984. *
  985. ***************************************************************************/
  986. static int32_t
  987. e1000_get_software_semaphore(struct e1000_hw *hw)
  988. {
  989. int32_t timeout = hw->eeprom.word_size + 1;
  990. uint32_t swsm;
  991. DEBUGFUNC();
  992. if (hw->mac_type != e1000_80003es2lan && hw->mac_type != e1000_igb)
  993. return E1000_SUCCESS;
  994. while (timeout) {
  995. swsm = E1000_READ_REG(hw, SWSM);
  996. /* If SMBI bit cleared, it is now set and we hold
  997. * the semaphore */
  998. if (!(swsm & E1000_SWSM_SMBI))
  999. break;
  1000. mdelay(1);
  1001. timeout--;
  1002. }
  1003. if (!timeout) {
  1004. DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
  1005. return -E1000_ERR_RESET;
  1006. }
  1007. return E1000_SUCCESS;
  1008. }
  1009. #endif
  1010. /***************************************************************************
  1011. * This function clears HW semaphore bits.
  1012. *
  1013. * hw: Struct containing variables accessed by shared code
  1014. *
  1015. * returns: - None.
  1016. *
  1017. ***************************************************************************/
  1018. static void
  1019. e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
  1020. {
  1021. #ifndef CONFIG_E1000_NO_NVM
  1022. uint32_t swsm;
  1023. DEBUGFUNC();
  1024. if (!hw->eeprom_semaphore_present)
  1025. return;
  1026. swsm = E1000_READ_REG(hw, SWSM);
  1027. if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
  1028. /* Release both semaphores. */
  1029. swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
  1030. } else
  1031. swsm &= ~(E1000_SWSM_SWESMBI);
  1032. E1000_WRITE_REG(hw, SWSM, swsm);
  1033. #endif
  1034. }
  1035. /***************************************************************************
  1036. *
  1037. * Using the combination of SMBI and SWESMBI semaphore bits when resetting
  1038. * adapter or Eeprom access.
  1039. *
  1040. * hw: Struct containing variables accessed by shared code
  1041. *
  1042. * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
  1043. * E1000_SUCCESS at any other case.
  1044. *
  1045. ***************************************************************************/
  1046. static int32_t
  1047. e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
  1048. {
  1049. #ifndef CONFIG_E1000_NO_NVM
  1050. int32_t timeout;
  1051. uint32_t swsm;
  1052. DEBUGFUNC();
  1053. if (!hw->eeprom_semaphore_present)
  1054. return E1000_SUCCESS;
  1055. if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
  1056. /* Get the SW semaphore. */
  1057. if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
  1058. return -E1000_ERR_EEPROM;
  1059. }
  1060. /* Get the FW semaphore. */
  1061. timeout = hw->eeprom.word_size + 1;
  1062. while (timeout) {
  1063. swsm = E1000_READ_REG(hw, SWSM);
  1064. swsm |= E1000_SWSM_SWESMBI;
  1065. E1000_WRITE_REG(hw, SWSM, swsm);
  1066. /* if we managed to set the bit we got the semaphore. */
  1067. swsm = E1000_READ_REG(hw, SWSM);
  1068. if (swsm & E1000_SWSM_SWESMBI)
  1069. break;
  1070. udelay(50);
  1071. timeout--;
  1072. }
  1073. if (!timeout) {
  1074. /* Release semaphores */
  1075. e1000_put_hw_eeprom_semaphore(hw);
  1076. DEBUGOUT("Driver can't access the Eeprom - "
  1077. "SWESMBI bit is set.\n");
  1078. return -E1000_ERR_EEPROM;
  1079. }
  1080. #endif
  1081. return E1000_SUCCESS;
  1082. }
  1083. /* Take ownership of the PHY */
  1084. static int32_t
  1085. e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
  1086. {
  1087. uint32_t swfw_sync = 0;
  1088. uint32_t swmask = mask;
  1089. uint32_t fwmask = mask << 16;
  1090. int32_t timeout = 200;
  1091. DEBUGFUNC();
  1092. while (timeout) {
  1093. if (e1000_get_hw_eeprom_semaphore(hw))
  1094. return -E1000_ERR_SWFW_SYNC;
  1095. swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
  1096. if (!(swfw_sync & (fwmask | swmask)))
  1097. break;
  1098. /* firmware currently using resource (fwmask) */
  1099. /* or other software thread currently using resource (swmask) */
  1100. e1000_put_hw_eeprom_semaphore(hw);
  1101. mdelay(5);
  1102. timeout--;
  1103. }
  1104. if (!timeout) {
  1105. DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
  1106. return -E1000_ERR_SWFW_SYNC;
  1107. }
  1108. swfw_sync |= swmask;
  1109. E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
  1110. e1000_put_hw_eeprom_semaphore(hw);
  1111. return E1000_SUCCESS;
  1112. }
  1113. static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
  1114. {
  1115. uint32_t swfw_sync = 0;
  1116. DEBUGFUNC();
  1117. while (e1000_get_hw_eeprom_semaphore(hw))
  1118. ; /* Empty */
  1119. swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
  1120. swfw_sync &= ~mask;
  1121. E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
  1122. e1000_put_hw_eeprom_semaphore(hw);
  1123. }
  1124. static bool e1000_is_second_port(struct e1000_hw *hw)
  1125. {
  1126. switch (hw->mac_type) {
  1127. case e1000_80003es2lan:
  1128. case e1000_82546:
  1129. case e1000_82571:
  1130. if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
  1131. return true;
  1132. /* Fallthrough */
  1133. default:
  1134. return false;
  1135. }
  1136. }
  1137. #ifndef CONFIG_E1000_NO_NVM
  1138. /******************************************************************************
  1139. * Reads the adapter's MAC address from the EEPROM
  1140. *
  1141. * hw - Struct containing variables accessed by shared code
  1142. * enetaddr - buffering where the MAC address will be stored
  1143. *****************************************************************************/
  1144. static int e1000_read_mac_addr_from_eeprom(struct e1000_hw *hw,
  1145. unsigned char enetaddr[6])
  1146. {
  1147. uint16_t offset;
  1148. uint16_t eeprom_data;
  1149. int i;
  1150. for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
  1151. offset = i >> 1;
  1152. if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
  1153. DEBUGOUT("EEPROM Read Error\n");
  1154. return -E1000_ERR_EEPROM;
  1155. }
  1156. enetaddr[i] = eeprom_data & 0xff;
  1157. enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
  1158. }
  1159. return 0;
  1160. }
  1161. /******************************************************************************
  1162. * Reads the adapter's MAC address from the RAL/RAH registers
  1163. *
  1164. * hw - Struct containing variables accessed by shared code
  1165. * enetaddr - buffering where the MAC address will be stored
  1166. *****************************************************************************/
  1167. static int e1000_read_mac_addr_from_regs(struct e1000_hw *hw,
  1168. unsigned char enetaddr[6])
  1169. {
  1170. uint16_t offset, tmp;
  1171. uint32_t reg_data = 0;
  1172. int i;
  1173. if (hw->mac_type != e1000_igb)
  1174. return -E1000_ERR_MAC_TYPE;
  1175. for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
  1176. offset = i >> 1;
  1177. if (offset == 0)
  1178. reg_data = E1000_READ_REG_ARRAY(hw, RA, 0);
  1179. else if (offset == 1)
  1180. reg_data >>= 16;
  1181. else if (offset == 2)
  1182. reg_data = E1000_READ_REG_ARRAY(hw, RA, 1);
  1183. tmp = reg_data & 0xffff;
  1184. enetaddr[i] = tmp & 0xff;
  1185. enetaddr[i + 1] = (tmp >> 8) & 0xff;
  1186. }
  1187. return 0;
  1188. }
  1189. /******************************************************************************
  1190. * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
  1191. * second function of dual function devices
  1192. *
  1193. * hw - Struct containing variables accessed by shared code
  1194. * enetaddr - buffering where the MAC address will be stored
  1195. *****************************************************************************/
  1196. static int e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6])
  1197. {
  1198. int ret_val;
  1199. if (hw->mac_type == e1000_igb) {
  1200. /* i210 preloads MAC address into RAL/RAH registers */
  1201. ret_val = e1000_read_mac_addr_from_regs(hw, enetaddr);
  1202. } else {
  1203. ret_val = e1000_read_mac_addr_from_eeprom(hw, enetaddr);
  1204. }
  1205. if (ret_val)
  1206. return ret_val;
  1207. /* Invert the last bit if this is the second device */
  1208. if (e1000_is_second_port(hw))
  1209. enetaddr[5] ^= 1;
  1210. return 0;
  1211. }
  1212. #endif
  1213. /******************************************************************************
  1214. * Initializes receive address filters.
  1215. *
  1216. * hw - Struct containing variables accessed by shared code
  1217. *
  1218. * Places the MAC address in receive address register 0 and clears the rest
  1219. * of the receive addresss registers. Clears the multicast table. Assumes
  1220. * the receiver is in reset when the routine is called.
  1221. *****************************************************************************/
  1222. static void
  1223. e1000_init_rx_addrs(struct e1000_hw *hw, unsigned char enetaddr[6])
  1224. {
  1225. uint32_t i;
  1226. uint32_t addr_low;
  1227. uint32_t addr_high;
  1228. DEBUGFUNC();
  1229. /* Setup the receive address. */
  1230. DEBUGOUT("Programming MAC Address into RAR[0]\n");
  1231. addr_low = (enetaddr[0] |
  1232. (enetaddr[1] << 8) |
  1233. (enetaddr[2] << 16) | (enetaddr[3] << 24));
  1234. addr_high = (enetaddr[4] | (enetaddr[5] << 8) | E1000_RAH_AV);
  1235. E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
  1236. E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
  1237. /* Zero out the other 15 receive addresses. */
  1238. DEBUGOUT("Clearing RAR[1-15]\n");
  1239. for (i = 1; i < E1000_RAR_ENTRIES; i++) {
  1240. E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
  1241. E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
  1242. }
  1243. }
  1244. /******************************************************************************
  1245. * Clears the VLAN filer table
  1246. *
  1247. * hw - Struct containing variables accessed by shared code
  1248. *****************************************************************************/
  1249. static void
  1250. e1000_clear_vfta(struct e1000_hw *hw)
  1251. {
  1252. uint32_t offset;
  1253. for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
  1254. E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
  1255. }
  1256. /******************************************************************************
  1257. * Set the mac type member in the hw struct.
  1258. *
  1259. * hw - Struct containing variables accessed by shared code
  1260. *****************************************************************************/
  1261. int32_t
  1262. e1000_set_mac_type(struct e1000_hw *hw)
  1263. {
  1264. DEBUGFUNC();
  1265. switch (hw->device_id) {
  1266. case E1000_DEV_ID_82542:
  1267. switch (hw->revision_id) {
  1268. case E1000_82542_2_0_REV_ID:
  1269. hw->mac_type = e1000_82542_rev2_0;
  1270. break;
  1271. case E1000_82542_2_1_REV_ID:
  1272. hw->mac_type = e1000_82542_rev2_1;
  1273. break;
  1274. default:
  1275. /* Invalid 82542 revision ID */
  1276. return -E1000_ERR_MAC_TYPE;
  1277. }
  1278. break;
  1279. case E1000_DEV_ID_82543GC_FIBER:
  1280. case E1000_DEV_ID_82543GC_COPPER:
  1281. hw->mac_type = e1000_82543;
  1282. break;
  1283. case E1000_DEV_ID_82544EI_COPPER:
  1284. case E1000_DEV_ID_82544EI_FIBER:
  1285. case E1000_DEV_ID_82544GC_COPPER:
  1286. case E1000_DEV_ID_82544GC_LOM:
  1287. hw->mac_type = e1000_82544;
  1288. break;
  1289. case E1000_DEV_ID_82540EM:
  1290. case E1000_DEV_ID_82540EM_LOM:
  1291. case E1000_DEV_ID_82540EP:
  1292. case E1000_DEV_ID_82540EP_LOM:
  1293. case E1000_DEV_ID_82540EP_LP:
  1294. hw->mac_type = e1000_82540;
  1295. break;
  1296. case E1000_DEV_ID_82545EM_COPPER:
  1297. case E1000_DEV_ID_82545EM_FIBER:
  1298. hw->mac_type = e1000_82545;
  1299. break;
  1300. case E1000_DEV_ID_82545GM_COPPER:
  1301. case E1000_DEV_ID_82545GM_FIBER:
  1302. case E1000_DEV_ID_82545GM_SERDES:
  1303. hw->mac_type = e1000_82545_rev_3;
  1304. break;
  1305. case E1000_DEV_ID_82546EB_COPPER:
  1306. case E1000_DEV_ID_82546EB_FIBER:
  1307. case E1000_DEV_ID_82546EB_QUAD_COPPER:
  1308. hw->mac_type = e1000_82546;
  1309. break;
  1310. case E1000_DEV_ID_82546GB_COPPER:
  1311. case E1000_DEV_ID_82546GB_FIBER:
  1312. case E1000_DEV_ID_82546GB_SERDES:
  1313. case E1000_DEV_ID_82546GB_PCIE:
  1314. case E1000_DEV_ID_82546GB_QUAD_COPPER:
  1315. case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
  1316. hw->mac_type = e1000_82546_rev_3;
  1317. break;
  1318. case E1000_DEV_ID_82541EI:
  1319. case E1000_DEV_ID_82541EI_MOBILE:
  1320. case E1000_DEV_ID_82541ER_LOM:
  1321. hw->mac_type = e1000_82541;
  1322. break;
  1323. case E1000_DEV_ID_82541ER:
  1324. case E1000_DEV_ID_82541GI:
  1325. case E1000_DEV_ID_82541GI_LF:
  1326. case E1000_DEV_ID_82541GI_MOBILE:
  1327. hw->mac_type = e1000_82541_rev_2;
  1328. break;
  1329. case E1000_DEV_ID_82547EI:
  1330. case E1000_DEV_ID_82547EI_MOBILE:
  1331. hw->mac_type = e1000_82547;
  1332. break;
  1333. case E1000_DEV_ID_82547GI:
  1334. hw->mac_type = e1000_82547_rev_2;
  1335. break;
  1336. case E1000_DEV_ID_82571EB_COPPER:
  1337. case E1000_DEV_ID_82571EB_FIBER:
  1338. case E1000_DEV_ID_82571EB_SERDES:
  1339. case E1000_DEV_ID_82571EB_SERDES_DUAL:
  1340. case E1000_DEV_ID_82571EB_SERDES_QUAD:
  1341. case E1000_DEV_ID_82571EB_QUAD_COPPER:
  1342. case E1000_DEV_ID_82571PT_QUAD_COPPER:
  1343. case E1000_DEV_ID_82571EB_QUAD_FIBER:
  1344. case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
  1345. hw->mac_type = e1000_82571;
  1346. break;
  1347. case E1000_DEV_ID_82572EI_COPPER:
  1348. case E1000_DEV_ID_82572EI_FIBER:
  1349. case E1000_DEV_ID_82572EI_SERDES:
  1350. case E1000_DEV_ID_82572EI:
  1351. hw->mac_type = e1000_82572;
  1352. break;
  1353. case E1000_DEV_ID_82573E:
  1354. case E1000_DEV_ID_82573E_IAMT:
  1355. case E1000_DEV_ID_82573L:
  1356. hw->mac_type = e1000_82573;
  1357. break;
  1358. case E1000_DEV_ID_82574L:
  1359. hw->mac_type = e1000_82574;
  1360. break;
  1361. case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
  1362. case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
  1363. case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
  1364. case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
  1365. hw->mac_type = e1000_80003es2lan;
  1366. break;
  1367. case E1000_DEV_ID_ICH8_IGP_M_AMT:
  1368. case E1000_DEV_ID_ICH8_IGP_AMT:
  1369. case E1000_DEV_ID_ICH8_IGP_C:
  1370. case E1000_DEV_ID_ICH8_IFE:
  1371. case E1000_DEV_ID_ICH8_IFE_GT:
  1372. case E1000_DEV_ID_ICH8_IFE_G:
  1373. case E1000_DEV_ID_ICH8_IGP_M:
  1374. hw->mac_type = e1000_ich8lan;
  1375. break;
  1376. case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED:
  1377. case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED:
  1378. case PCI_DEVICE_ID_INTEL_I210_COPPER:
  1379. case PCI_DEVICE_ID_INTEL_I211_COPPER:
  1380. case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS:
  1381. case PCI_DEVICE_ID_INTEL_I210_SERDES:
  1382. case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS:
  1383. case PCI_DEVICE_ID_INTEL_I210_1000BASEKX:
  1384. hw->mac_type = e1000_igb;
  1385. break;
  1386. default:
  1387. /* Should never have loaded on this device */
  1388. return -E1000_ERR_MAC_TYPE;
  1389. }
  1390. return E1000_SUCCESS;
  1391. }
  1392. /******************************************************************************
  1393. * Reset the transmit and receive units; mask and clear all interrupts.
  1394. *
  1395. * hw - Struct containing variables accessed by shared code
  1396. *****************************************************************************/
  1397. void
  1398. e1000_reset_hw(struct e1000_hw *hw)
  1399. {
  1400. uint32_t ctrl;
  1401. uint32_t ctrl_ext;
  1402. uint32_t manc;
  1403. uint32_t pba = 0;
  1404. uint32_t reg;
  1405. DEBUGFUNC();
  1406. /* get the correct pba value for both PCI and PCIe*/
  1407. if (hw->mac_type < e1000_82571)
  1408. pba = E1000_DEFAULT_PCI_PBA;
  1409. else
  1410. pba = E1000_DEFAULT_PCIE_PBA;
  1411. /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
  1412. if (hw->mac_type == e1000_82542_rev2_0) {
  1413. DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
  1414. #ifdef CONFIG_DM_ETH
  1415. dm_pci_write_config16(hw->pdev, PCI_COMMAND,
  1416. hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
  1417. #else
  1418. pci_write_config_word(hw->pdev, PCI_COMMAND,
  1419. hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
  1420. #endif
  1421. }
  1422. /* Clear interrupt mask to stop board from generating interrupts */
  1423. DEBUGOUT("Masking off all interrupts\n");
  1424. if (hw->mac_type == e1000_igb)
  1425. E1000_WRITE_REG(hw, I210_IAM, 0);
  1426. E1000_WRITE_REG(hw, IMC, 0xffffffff);
  1427. /* Disable the Transmit and Receive units. Then delay to allow
  1428. * any pending transactions to complete before we hit the MAC with
  1429. * the global reset.
  1430. */
  1431. E1000_WRITE_REG(hw, RCTL, 0);
  1432. E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
  1433. E1000_WRITE_FLUSH(hw);
  1434. /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
  1435. hw->tbi_compatibility_on = false;
  1436. /* Delay to allow any outstanding PCI transactions to complete before
  1437. * resetting the device
  1438. */
  1439. mdelay(10);
  1440. /* Issue a global reset to the MAC. This will reset the chip's
  1441. * transmit, receive, DMA, and link units. It will not effect
  1442. * the current PCI configuration. The global reset bit is self-
  1443. * clearing, and should clear within a microsecond.
  1444. */
  1445. DEBUGOUT("Issuing a global reset to MAC\n");
  1446. ctrl = E1000_READ_REG(hw, CTRL);
  1447. E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
  1448. /* Force a reload from the EEPROM if necessary */
  1449. if (hw->mac_type == e1000_igb) {
  1450. mdelay(20);
  1451. reg = E1000_READ_REG(hw, STATUS);
  1452. if (reg & E1000_STATUS_PF_RST_DONE)
  1453. DEBUGOUT("PF OK\n");
  1454. reg = E1000_READ_REG(hw, I210_EECD);
  1455. if (reg & E1000_EECD_AUTO_RD)
  1456. DEBUGOUT("EEC OK\n");
  1457. } else if (hw->mac_type < e1000_82540) {
  1458. /* Wait for reset to complete */
  1459. udelay(10);
  1460. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  1461. ctrl_ext |= E1000_CTRL_EXT_EE_RST;
  1462. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  1463. E1000_WRITE_FLUSH(hw);
  1464. /* Wait for EEPROM reload */
  1465. mdelay(2);
  1466. } else {
  1467. /* Wait for EEPROM reload (it happens automatically) */
  1468. mdelay(4);
  1469. /* Dissable HW ARPs on ASF enabled adapters */
  1470. manc = E1000_READ_REG(hw, MANC);
  1471. manc &= ~(E1000_MANC_ARP_EN);
  1472. E1000_WRITE_REG(hw, MANC, manc);
  1473. }
  1474. /* Clear interrupt mask to stop board from generating interrupts */
  1475. DEBUGOUT("Masking off all interrupts\n");
  1476. if (hw->mac_type == e1000_igb)
  1477. E1000_WRITE_REG(hw, I210_IAM, 0);
  1478. E1000_WRITE_REG(hw, IMC, 0xffffffff);
  1479. /* Clear any pending interrupt events. */
  1480. E1000_READ_REG(hw, ICR);
  1481. /* If MWI was previously enabled, reenable it. */
  1482. if (hw->mac_type == e1000_82542_rev2_0) {
  1483. #ifdef CONFIG_DM_ETH
  1484. dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
  1485. #else
  1486. pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
  1487. #endif
  1488. }
  1489. if (hw->mac_type != e1000_igb)
  1490. E1000_WRITE_REG(hw, PBA, pba);
  1491. }
  1492. /******************************************************************************
  1493. *
  1494. * Initialize a number of hardware-dependent bits
  1495. *
  1496. * hw: Struct containing variables accessed by shared code
  1497. *
  1498. * This function contains hardware limitation workarounds for PCI-E adapters
  1499. *
  1500. *****************************************************************************/
  1501. static void
  1502. e1000_initialize_hardware_bits(struct e1000_hw *hw)
  1503. {
  1504. if ((hw->mac_type >= e1000_82571) &&
  1505. (!hw->initialize_hw_bits_disable)) {
  1506. /* Settings common to all PCI-express silicon */
  1507. uint32_t reg_ctrl, reg_ctrl_ext;
  1508. uint32_t reg_tarc0, reg_tarc1;
  1509. uint32_t reg_tctl;
  1510. uint32_t reg_txdctl, reg_txdctl1;
  1511. /* link autonegotiation/sync workarounds */
  1512. reg_tarc0 = E1000_READ_REG(hw, TARC0);
  1513. reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
  1514. /* Enable not-done TX descriptor counting */
  1515. reg_txdctl = E1000_READ_REG(hw, TXDCTL);
  1516. reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
  1517. E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
  1518. reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
  1519. reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
  1520. E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
  1521. switch (hw->mac_type) {
  1522. case e1000_igb: /* IGB is cool */
  1523. return;
  1524. case e1000_82571:
  1525. case e1000_82572:
  1526. /* Clear PHY TX compatible mode bits */
  1527. reg_tarc1 = E1000_READ_REG(hw, TARC1);
  1528. reg_tarc1 &= ~((1 << 30)|(1 << 29));
  1529. /* link autonegotiation/sync workarounds */
  1530. reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
  1531. /* TX ring control fixes */
  1532. reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
  1533. /* Multiple read bit is reversed polarity */
  1534. reg_tctl = E1000_READ_REG(hw, TCTL);
  1535. if (reg_tctl & E1000_TCTL_MULR)
  1536. reg_tarc1 &= ~(1 << 28);
  1537. else
  1538. reg_tarc1 |= (1 << 28);
  1539. E1000_WRITE_REG(hw, TARC1, reg_tarc1);
  1540. break;
  1541. case e1000_82573:
  1542. case e1000_82574:
  1543. reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  1544. reg_ctrl_ext &= ~(1 << 23);
  1545. reg_ctrl_ext |= (1 << 22);
  1546. /* TX byte count fix */
  1547. reg_ctrl = E1000_READ_REG(hw, CTRL);
  1548. reg_ctrl &= ~(1 << 29);
  1549. E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
  1550. E1000_WRITE_REG(hw, CTRL, reg_ctrl);
  1551. break;
  1552. case e1000_80003es2lan:
  1553. /* improve small packet performace for fiber/serdes */
  1554. if ((hw->media_type == e1000_media_type_fiber)
  1555. || (hw->media_type ==
  1556. e1000_media_type_internal_serdes)) {
  1557. reg_tarc0 &= ~(1 << 20);
  1558. }
  1559. /* Multiple read bit is reversed polarity */
  1560. reg_tctl = E1000_READ_REG(hw, TCTL);
  1561. reg_tarc1 = E1000_READ_REG(hw, TARC1);
  1562. if (reg_tctl & E1000_TCTL_MULR)
  1563. reg_tarc1 &= ~(1 << 28);
  1564. else
  1565. reg_tarc1 |= (1 << 28);
  1566. E1000_WRITE_REG(hw, TARC1, reg_tarc1);
  1567. break;
  1568. case e1000_ich8lan:
  1569. /* Reduce concurrent DMA requests to 3 from 4 */
  1570. if ((hw->revision_id < 3) ||
  1571. ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
  1572. (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
  1573. reg_tarc0 |= ((1 << 29)|(1 << 28));
  1574. reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  1575. reg_ctrl_ext |= (1 << 22);
  1576. E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
  1577. /* workaround TX hang with TSO=on */
  1578. reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
  1579. /* Multiple read bit is reversed polarity */
  1580. reg_tctl = E1000_READ_REG(hw, TCTL);
  1581. reg_tarc1 = E1000_READ_REG(hw, TARC1);
  1582. if (reg_tctl & E1000_TCTL_MULR)
  1583. reg_tarc1 &= ~(1 << 28);
  1584. else
  1585. reg_tarc1 |= (1 << 28);
  1586. /* workaround TX hang with TSO=on */
  1587. reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
  1588. E1000_WRITE_REG(hw, TARC1, reg_tarc1);
  1589. break;
  1590. default:
  1591. break;
  1592. }
  1593. E1000_WRITE_REG(hw, TARC0, reg_tarc0);
  1594. }
  1595. }
  1596. /******************************************************************************
  1597. * Performs basic configuration of the adapter.
  1598. *
  1599. * hw - Struct containing variables accessed by shared code
  1600. *
  1601. * Assumes that the controller has previously been reset and is in a
  1602. * post-reset uninitialized state. Initializes the receive address registers,
  1603. * multicast table, and VLAN filter table. Calls routines to setup link
  1604. * configuration and flow control settings. Clears all on-chip counters. Leaves
  1605. * the transmit and receive units disabled and uninitialized.
  1606. *****************************************************************************/
  1607. static int
  1608. e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6])
  1609. {
  1610. uint32_t ctrl;
  1611. uint32_t i;
  1612. int32_t ret_val;
  1613. uint16_t pcix_cmd_word;
  1614. uint16_t pcix_stat_hi_word;
  1615. uint16_t cmd_mmrbc;
  1616. uint16_t stat_mmrbc;
  1617. uint32_t mta_size;
  1618. uint32_t reg_data;
  1619. uint32_t ctrl_ext;
  1620. DEBUGFUNC();
  1621. /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
  1622. if ((hw->mac_type == e1000_ich8lan) &&
  1623. ((hw->revision_id < 3) ||
  1624. ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
  1625. (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
  1626. reg_data = E1000_READ_REG(hw, STATUS);
  1627. reg_data &= ~0x80000000;
  1628. E1000_WRITE_REG(hw, STATUS, reg_data);
  1629. }
  1630. /* Do not need initialize Identification LED */
  1631. /* Set the media type and TBI compatibility */
  1632. e1000_set_media_type(hw);
  1633. /* Must be called after e1000_set_media_type
  1634. * because media_type is used */
  1635. e1000_initialize_hardware_bits(hw);
  1636. /* Disabling VLAN filtering. */
  1637. DEBUGOUT("Initializing the IEEE VLAN\n");
  1638. /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
  1639. if (hw->mac_type != e1000_ich8lan) {
  1640. if (hw->mac_type < e1000_82545_rev_3)
  1641. E1000_WRITE_REG(hw, VET, 0);
  1642. e1000_clear_vfta(hw);
  1643. }
  1644. /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
  1645. if (hw->mac_type == e1000_82542_rev2_0) {
  1646. DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
  1647. #ifdef CONFIG_DM_ETH
  1648. dm_pci_write_config16(hw->pdev, PCI_COMMAND,
  1649. hw->
  1650. pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
  1651. #else
  1652. pci_write_config_word(hw->pdev, PCI_COMMAND,
  1653. hw->
  1654. pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
  1655. #endif
  1656. E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
  1657. E1000_WRITE_FLUSH(hw);
  1658. mdelay(5);
  1659. }
  1660. /* Setup the receive address. This involves initializing all of the Receive
  1661. * Address Registers (RARs 0 - 15).
  1662. */
  1663. e1000_init_rx_addrs(hw, enetaddr);
  1664. /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
  1665. if (hw->mac_type == e1000_82542_rev2_0) {
  1666. E1000_WRITE_REG(hw, RCTL, 0);
  1667. E1000_WRITE_FLUSH(hw);
  1668. mdelay(1);
  1669. #ifdef CONFIG_DM_ETH
  1670. dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
  1671. #else
  1672. pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
  1673. #endif
  1674. }
  1675. /* Zero out the Multicast HASH table */
  1676. DEBUGOUT("Zeroing the MTA\n");
  1677. mta_size = E1000_MC_TBL_SIZE;
  1678. if (hw->mac_type == e1000_ich8lan)
  1679. mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
  1680. for (i = 0; i < mta_size; i++) {
  1681. E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
  1682. /* use write flush to prevent Memory Write Block (MWB) from
  1683. * occuring when accessing our register space */
  1684. E1000_WRITE_FLUSH(hw);
  1685. }
  1686. switch (hw->mac_type) {
  1687. case e1000_82545_rev_3:
  1688. case e1000_82546_rev_3:
  1689. case e1000_igb:
  1690. break;
  1691. default:
  1692. /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
  1693. if (hw->bus_type == e1000_bus_type_pcix) {
  1694. #ifdef CONFIG_DM_ETH
  1695. dm_pci_read_config16(hw->pdev, PCIX_COMMAND_REGISTER,
  1696. &pcix_cmd_word);
  1697. dm_pci_read_config16(hw->pdev, PCIX_STATUS_REGISTER_HI,
  1698. &pcix_stat_hi_word);
  1699. #else
  1700. pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
  1701. &pcix_cmd_word);
  1702. pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
  1703. &pcix_stat_hi_word);
  1704. #endif
  1705. cmd_mmrbc =
  1706. (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
  1707. PCIX_COMMAND_MMRBC_SHIFT;
  1708. stat_mmrbc =
  1709. (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
  1710. PCIX_STATUS_HI_MMRBC_SHIFT;
  1711. if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
  1712. stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
  1713. if (cmd_mmrbc > stat_mmrbc) {
  1714. pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
  1715. pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
  1716. #ifdef CONFIG_DM_ETH
  1717. dm_pci_write_config16(hw->pdev, PCIX_COMMAND_REGISTER,
  1718. pcix_cmd_word);
  1719. #else
  1720. pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
  1721. pcix_cmd_word);
  1722. #endif
  1723. }
  1724. }
  1725. break;
  1726. }
  1727. /* More time needed for PHY to initialize */
  1728. if (hw->mac_type == e1000_ich8lan)
  1729. mdelay(15);
  1730. if (hw->mac_type == e1000_igb)
  1731. mdelay(15);
  1732. /* Call a subroutine to configure the link and setup flow control. */
  1733. ret_val = e1000_setup_link(hw);
  1734. /* Set the transmit descriptor write-back policy */
  1735. if (hw->mac_type > e1000_82544) {
  1736. ctrl = E1000_READ_REG(hw, TXDCTL);
  1737. ctrl =
  1738. (ctrl & ~E1000_TXDCTL_WTHRESH) |
  1739. E1000_TXDCTL_FULL_TX_DESC_WB;
  1740. E1000_WRITE_REG(hw, TXDCTL, ctrl);
  1741. }
  1742. /* Set the receive descriptor write back policy */
  1743. if (hw->mac_type >= e1000_82571) {
  1744. ctrl = E1000_READ_REG(hw, RXDCTL);
  1745. ctrl =
  1746. (ctrl & ~E1000_RXDCTL_WTHRESH) |
  1747. E1000_RXDCTL_FULL_RX_DESC_WB;
  1748. E1000_WRITE_REG(hw, RXDCTL, ctrl);
  1749. }
  1750. switch (hw->mac_type) {
  1751. default:
  1752. break;
  1753. case e1000_80003es2lan:
  1754. /* Enable retransmit on late collisions */
  1755. reg_data = E1000_READ_REG(hw, TCTL);
  1756. reg_data |= E1000_TCTL_RTLC;
  1757. E1000_WRITE_REG(hw, TCTL, reg_data);
  1758. /* Configure Gigabit Carry Extend Padding */
  1759. reg_data = E1000_READ_REG(hw, TCTL_EXT);
  1760. reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
  1761. reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
  1762. E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
  1763. /* Configure Transmit Inter-Packet Gap */
  1764. reg_data = E1000_READ_REG(hw, TIPG);
  1765. reg_data &= ~E1000_TIPG_IPGT_MASK;
  1766. reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
  1767. E1000_WRITE_REG(hw, TIPG, reg_data);
  1768. reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
  1769. reg_data &= ~0x00100000;
  1770. E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
  1771. /* Fall through */
  1772. case e1000_82571:
  1773. case e1000_82572:
  1774. case e1000_ich8lan:
  1775. ctrl = E1000_READ_REG(hw, TXDCTL1);
  1776. ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
  1777. | E1000_TXDCTL_FULL_TX_DESC_WB;
  1778. E1000_WRITE_REG(hw, TXDCTL1, ctrl);
  1779. break;
  1780. case e1000_82573:
  1781. case e1000_82574:
  1782. reg_data = E1000_READ_REG(hw, GCR);
  1783. reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
  1784. E1000_WRITE_REG(hw, GCR, reg_data);
  1785. case e1000_igb:
  1786. break;
  1787. }
  1788. if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
  1789. hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
  1790. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  1791. /* Relaxed ordering must be disabled to avoid a parity
  1792. * error crash in a PCI slot. */
  1793. ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
  1794. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  1795. }
  1796. return ret_val;
  1797. }
  1798. /******************************************************************************
  1799. * Configures flow control and link settings.
  1800. *
  1801. * hw - Struct containing variables accessed by shared code
  1802. *
  1803. * Determines which flow control settings to use. Calls the apropriate media-
  1804. * specific link configuration function. Configures the flow control settings.
  1805. * Assuming the adapter has a valid link partner, a valid link should be
  1806. * established. Assumes the hardware has previously been reset and the
  1807. * transmitter and receiver are not enabled.
  1808. *****************************************************************************/
  1809. static int
  1810. e1000_setup_link(struct e1000_hw *hw)
  1811. {
  1812. int32_t ret_val;
  1813. #ifndef CONFIG_E1000_NO_NVM
  1814. uint32_t ctrl_ext;
  1815. uint16_t eeprom_data;
  1816. #endif
  1817. DEBUGFUNC();
  1818. /* In the case of the phy reset being blocked, we already have a link.
  1819. * We do not have to set it up again. */
  1820. if (e1000_check_phy_reset_block(hw))
  1821. return E1000_SUCCESS;
  1822. #ifndef CONFIG_E1000_NO_NVM
  1823. /* Read and store word 0x0F of the EEPROM. This word contains bits
  1824. * that determine the hardware's default PAUSE (flow control) mode,
  1825. * a bit that determines whether the HW defaults to enabling or
  1826. * disabling auto-negotiation, and the direction of the
  1827. * SW defined pins. If there is no SW over-ride of the flow
  1828. * control setting, then the variable hw->fc will
  1829. * be initialized based on a value in the EEPROM.
  1830. */
  1831. if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
  1832. &eeprom_data) < 0) {
  1833. DEBUGOUT("EEPROM Read Error\n");
  1834. return -E1000_ERR_EEPROM;
  1835. }
  1836. #endif
  1837. if (hw->fc == e1000_fc_default) {
  1838. switch (hw->mac_type) {
  1839. case e1000_ich8lan:
  1840. case e1000_82573:
  1841. case e1000_82574:
  1842. case e1000_igb:
  1843. hw->fc = e1000_fc_full;
  1844. break;
  1845. default:
  1846. #ifndef CONFIG_E1000_NO_NVM
  1847. ret_val = e1000_read_eeprom(hw,
  1848. EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
  1849. if (ret_val) {
  1850. DEBUGOUT("EEPROM Read Error\n");
  1851. return -E1000_ERR_EEPROM;
  1852. }
  1853. if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
  1854. hw->fc = e1000_fc_none;
  1855. else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
  1856. EEPROM_WORD0F_ASM_DIR)
  1857. hw->fc = e1000_fc_tx_pause;
  1858. else
  1859. #endif
  1860. hw->fc = e1000_fc_full;
  1861. break;
  1862. }
  1863. }
  1864. /* We want to save off the original Flow Control configuration just
  1865. * in case we get disconnected and then reconnected into a different
  1866. * hub or switch with different Flow Control capabilities.
  1867. */
  1868. if (hw->mac_type == e1000_82542_rev2_0)
  1869. hw->fc &= (~e1000_fc_tx_pause);
  1870. if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
  1871. hw->fc &= (~e1000_fc_rx_pause);
  1872. hw->original_fc = hw->fc;
  1873. DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
  1874. #ifndef CONFIG_E1000_NO_NVM
  1875. /* Take the 4 bits from EEPROM word 0x0F that determine the initial
  1876. * polarity value for the SW controlled pins, and setup the
  1877. * Extended Device Control reg with that info.
  1878. * This is needed because one of the SW controlled pins is used for
  1879. * signal detection. So this should be done before e1000_setup_pcs_link()
  1880. * or e1000_phy_setup() is called.
  1881. */
  1882. if (hw->mac_type == e1000_82543) {
  1883. ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
  1884. SWDPIO__EXT_SHIFT);
  1885. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  1886. }
  1887. #endif
  1888. /* Call the necessary subroutine to configure the link. */
  1889. ret_val = (hw->media_type == e1000_media_type_fiber) ?
  1890. e1000_setup_fiber_link(hw) : e1000_setup_copper_link(hw);
  1891. if (ret_val < 0) {
  1892. return ret_val;
  1893. }
  1894. /* Initialize the flow control address, type, and PAUSE timer
  1895. * registers to their default values. This is done even if flow
  1896. * control is disabled, because it does not hurt anything to
  1897. * initialize these registers.
  1898. */
  1899. DEBUGOUT("Initializing the Flow Control address, type"
  1900. "and timer regs\n");
  1901. /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
  1902. if (hw->mac_type != e1000_ich8lan) {
  1903. E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
  1904. E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
  1905. E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
  1906. }
  1907. E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
  1908. /* Set the flow control receive threshold registers. Normally,
  1909. * these registers will be set to a default threshold that may be
  1910. * adjusted later by the driver's runtime code. However, if the
  1911. * ability to transmit pause frames in not enabled, then these
  1912. * registers will be set to 0.
  1913. */
  1914. if (!(hw->fc & e1000_fc_tx_pause)) {
  1915. E1000_WRITE_REG(hw, FCRTL, 0);
  1916. E1000_WRITE_REG(hw, FCRTH, 0);
  1917. } else {
  1918. /* We need to set up the Receive Threshold high and low water marks
  1919. * as well as (optionally) enabling the transmission of XON frames.
  1920. */
  1921. if (hw->fc_send_xon) {
  1922. E1000_WRITE_REG(hw, FCRTL,
  1923. (hw->fc_low_water | E1000_FCRTL_XONE));
  1924. E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
  1925. } else {
  1926. E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
  1927. E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
  1928. }
  1929. }
  1930. return ret_val;
  1931. }
  1932. /******************************************************************************
  1933. * Sets up link for a fiber based adapter
  1934. *
  1935. * hw - Struct containing variables accessed by shared code
  1936. *
  1937. * Manipulates Physical Coding Sublayer functions in order to configure
  1938. * link. Assumes the hardware has been previously reset and the transmitter
  1939. * and receiver are not enabled.
  1940. *****************************************************************************/
  1941. static int
  1942. e1000_setup_fiber_link(struct e1000_hw *hw)
  1943. {
  1944. uint32_t ctrl;
  1945. uint32_t status;
  1946. uint32_t txcw = 0;
  1947. uint32_t i;
  1948. uint32_t signal;
  1949. int32_t ret_val;
  1950. DEBUGFUNC();
  1951. /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
  1952. * set when the optics detect a signal. On older adapters, it will be
  1953. * cleared when there is a signal
  1954. */
  1955. ctrl = E1000_READ_REG(hw, CTRL);
  1956. if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
  1957. signal = E1000_CTRL_SWDPIN1;
  1958. else
  1959. signal = 0;
  1960. printf("signal for %s is %x (ctrl %08x)!!!!\n", hw->name, signal,
  1961. ctrl);
  1962. /* Take the link out of reset */
  1963. ctrl &= ~(E1000_CTRL_LRST);
  1964. e1000_config_collision_dist(hw);
  1965. /* Check for a software override of the flow control settings, and setup
  1966. * the device accordingly. If auto-negotiation is enabled, then software
  1967. * will have to set the "PAUSE" bits to the correct value in the Tranmsit
  1968. * Config Word Register (TXCW) and re-start auto-negotiation. However, if
  1969. * auto-negotiation is disabled, then software will have to manually
  1970. * configure the two flow control enable bits in the CTRL register.
  1971. *
  1972. * The possible values of the "fc" parameter are:
  1973. * 0: Flow control is completely disabled
  1974. * 1: Rx flow control is enabled (we can receive pause frames, but
  1975. * not send pause frames).
  1976. * 2: Tx flow control is enabled (we can send pause frames but we do
  1977. * not support receiving pause frames).
  1978. * 3: Both Rx and TX flow control (symmetric) are enabled.
  1979. */
  1980. switch (hw->fc) {
  1981. case e1000_fc_none:
  1982. /* Flow control is completely disabled by a software over-ride. */
  1983. txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
  1984. break;
  1985. case e1000_fc_rx_pause:
  1986. /* RX Flow control is enabled and TX Flow control is disabled by a
  1987. * software over-ride. Since there really isn't a way to advertise
  1988. * that we are capable of RX Pause ONLY, we will advertise that we
  1989. * support both symmetric and asymmetric RX PAUSE. Later, we will
  1990. * disable the adapter's ability to send PAUSE frames.
  1991. */
  1992. txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
  1993. break;
  1994. case e1000_fc_tx_pause:
  1995. /* TX Flow control is enabled, and RX Flow control is disabled, by a
  1996. * software over-ride.
  1997. */
  1998. txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
  1999. break;
  2000. case e1000_fc_full:
  2001. /* Flow control (both RX and TX) is enabled by a software over-ride. */
  2002. txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
  2003. break;
  2004. default:
  2005. DEBUGOUT("Flow control param set incorrectly\n");
  2006. return -E1000_ERR_CONFIG;
  2007. break;
  2008. }
  2009. /* Since auto-negotiation is enabled, take the link out of reset (the link
  2010. * will be in reset, because we previously reset the chip). This will
  2011. * restart auto-negotiation. If auto-neogtiation is successful then the
  2012. * link-up status bit will be set and the flow control enable bits (RFCE
  2013. * and TFCE) will be set according to their negotiated value.
  2014. */
  2015. DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
  2016. E1000_WRITE_REG(hw, TXCW, txcw);
  2017. E1000_WRITE_REG(hw, CTRL, ctrl);
  2018. E1000_WRITE_FLUSH(hw);
  2019. hw->txcw = txcw;
  2020. mdelay(1);
  2021. /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
  2022. * indication in the Device Status Register. Time-out if a link isn't
  2023. * seen in 500 milliseconds seconds (Auto-negotiation should complete in
  2024. * less than 500 milliseconds even if the other end is doing it in SW).
  2025. */
  2026. if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
  2027. DEBUGOUT("Looking for Link\n");
  2028. for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
  2029. mdelay(10);
  2030. status = E1000_READ_REG(hw, STATUS);
  2031. if (status & E1000_STATUS_LU)
  2032. break;
  2033. }
  2034. if (i == (LINK_UP_TIMEOUT / 10)) {
  2035. /* AutoNeg failed to achieve a link, so we'll call
  2036. * e1000_check_for_link. This routine will force the link up if we
  2037. * detect a signal. This will allow us to communicate with
  2038. * non-autonegotiating link partners.
  2039. */
  2040. DEBUGOUT("Never got a valid link from auto-neg!!!\n");
  2041. hw->autoneg_failed = 1;
  2042. ret_val = e1000_check_for_link(hw);
  2043. if (ret_val < 0) {
  2044. DEBUGOUT("Error while checking for link\n");
  2045. return ret_val;
  2046. }
  2047. hw->autoneg_failed = 0;
  2048. } else {
  2049. hw->autoneg_failed = 0;
  2050. DEBUGOUT("Valid Link Found\n");
  2051. }
  2052. } else {
  2053. DEBUGOUT("No Signal Detected\n");
  2054. return -E1000_ERR_NOLINK;
  2055. }
  2056. return 0;
  2057. }
  2058. /******************************************************************************
  2059. * Make sure we have a valid PHY and change PHY mode before link setup.
  2060. *
  2061. * hw - Struct containing variables accessed by shared code
  2062. ******************************************************************************/
  2063. static int32_t
  2064. e1000_copper_link_preconfig(struct e1000_hw *hw)
  2065. {
  2066. uint32_t ctrl;
  2067. int32_t ret_val;
  2068. uint16_t phy_data;
  2069. DEBUGFUNC();
  2070. ctrl = E1000_READ_REG(hw, CTRL);
  2071. /* With 82543, we need to force speed and duplex on the MAC equal to what
  2072. * the PHY speed and duplex configuration is. In addition, we need to
  2073. * perform a hardware reset on the PHY to take it out of reset.
  2074. */
  2075. if (hw->mac_type > e1000_82543) {
  2076. ctrl |= E1000_CTRL_SLU;
  2077. ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
  2078. E1000_WRITE_REG(hw, CTRL, ctrl);
  2079. } else {
  2080. ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
  2081. | E1000_CTRL_SLU);
  2082. E1000_WRITE_REG(hw, CTRL, ctrl);
  2083. ret_val = e1000_phy_hw_reset(hw);
  2084. if (ret_val)
  2085. return ret_val;
  2086. }
  2087. /* Make sure we have a valid PHY */
  2088. ret_val = e1000_detect_gig_phy(hw);
  2089. if (ret_val) {
  2090. DEBUGOUT("Error, did not detect valid phy.\n");
  2091. return ret_val;
  2092. }
  2093. DEBUGOUT("Phy ID = %x\n", hw->phy_id);
  2094. /* Set PHY to class A mode (if necessary) */
  2095. ret_val = e1000_set_phy_mode(hw);
  2096. if (ret_val)
  2097. return ret_val;
  2098. if ((hw->mac_type == e1000_82545_rev_3) ||
  2099. (hw->mac_type == e1000_82546_rev_3)) {
  2100. ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
  2101. &phy_data);
  2102. phy_data |= 0x00000008;
  2103. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
  2104. phy_data);
  2105. }
  2106. if (hw->mac_type <= e1000_82543 ||
  2107. hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
  2108. hw->mac_type == e1000_82541_rev_2
  2109. || hw->mac_type == e1000_82547_rev_2)
  2110. hw->phy_reset_disable = false;
  2111. return E1000_SUCCESS;
  2112. }
  2113. /*****************************************************************************
  2114. *
  2115. * This function sets the lplu state according to the active flag. When
  2116. * activating lplu this function also disables smart speed and vise versa.
  2117. * lplu will not be activated unless the device autonegotiation advertisment
  2118. * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
  2119. * hw: Struct containing variables accessed by shared code
  2120. * active - true to enable lplu false to disable lplu.
  2121. *
  2122. * returns: - E1000_ERR_PHY if fail to read/write the PHY
  2123. * E1000_SUCCESS at any other case.
  2124. *
  2125. ****************************************************************************/
  2126. static int32_t
  2127. e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
  2128. {
  2129. uint32_t phy_ctrl = 0;
  2130. int32_t ret_val;
  2131. uint16_t phy_data;
  2132. DEBUGFUNC();
  2133. if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
  2134. && hw->phy_type != e1000_phy_igp_3)
  2135. return E1000_SUCCESS;
  2136. /* During driver activity LPLU should not be used or it will attain link
  2137. * from the lowest speeds starting from 10Mbps. The capability is used
  2138. * for Dx transitions and states */
  2139. if (hw->mac_type == e1000_82541_rev_2
  2140. || hw->mac_type == e1000_82547_rev_2) {
  2141. ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
  2142. &phy_data);
  2143. if (ret_val)
  2144. return ret_val;
  2145. } else if (hw->mac_type == e1000_ich8lan) {
  2146. /* MAC writes into PHY register based on the state transition
  2147. * and start auto-negotiation. SW driver can overwrite the
  2148. * settings in CSR PHY power control E1000_PHY_CTRL register. */
  2149. phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
  2150. } else {
  2151. ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
  2152. &phy_data);
  2153. if (ret_val)
  2154. return ret_val;
  2155. }
  2156. if (!active) {
  2157. if (hw->mac_type == e1000_82541_rev_2 ||
  2158. hw->mac_type == e1000_82547_rev_2) {
  2159. phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
  2160. ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
  2161. phy_data);
  2162. if (ret_val)
  2163. return ret_val;
  2164. } else {
  2165. if (hw->mac_type == e1000_ich8lan) {
  2166. phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
  2167. E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
  2168. } else {
  2169. phy_data &= ~IGP02E1000_PM_D3_LPLU;
  2170. ret_val = e1000_write_phy_reg(hw,
  2171. IGP02E1000_PHY_POWER_MGMT, phy_data);
  2172. if (ret_val)
  2173. return ret_val;
  2174. }
  2175. }
  2176. /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
  2177. * Dx states where the power conservation is most important. During
  2178. * driver activity we should enable SmartSpeed, so performance is
  2179. * maintained. */
  2180. if (hw->smart_speed == e1000_smart_speed_on) {
  2181. ret_val = e1000_read_phy_reg(hw,
  2182. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2183. if (ret_val)
  2184. return ret_val;
  2185. phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
  2186. ret_val = e1000_write_phy_reg(hw,
  2187. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2188. if (ret_val)
  2189. return ret_val;
  2190. } else if (hw->smart_speed == e1000_smart_speed_off) {
  2191. ret_val = e1000_read_phy_reg(hw,
  2192. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2193. if (ret_val)
  2194. return ret_val;
  2195. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  2196. ret_val = e1000_write_phy_reg(hw,
  2197. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2198. if (ret_val)
  2199. return ret_val;
  2200. }
  2201. } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
  2202. || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
  2203. (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
  2204. if (hw->mac_type == e1000_82541_rev_2 ||
  2205. hw->mac_type == e1000_82547_rev_2) {
  2206. phy_data |= IGP01E1000_GMII_FLEX_SPD;
  2207. ret_val = e1000_write_phy_reg(hw,
  2208. IGP01E1000_GMII_FIFO, phy_data);
  2209. if (ret_val)
  2210. return ret_val;
  2211. } else {
  2212. if (hw->mac_type == e1000_ich8lan) {
  2213. phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
  2214. E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
  2215. } else {
  2216. phy_data |= IGP02E1000_PM_D3_LPLU;
  2217. ret_val = e1000_write_phy_reg(hw,
  2218. IGP02E1000_PHY_POWER_MGMT, phy_data);
  2219. if (ret_val)
  2220. return ret_val;
  2221. }
  2222. }
  2223. /* When LPLU is enabled we should disable SmartSpeed */
  2224. ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  2225. &phy_data);
  2226. if (ret_val)
  2227. return ret_val;
  2228. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  2229. ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  2230. phy_data);
  2231. if (ret_val)
  2232. return ret_val;
  2233. }
  2234. return E1000_SUCCESS;
  2235. }
  2236. /*****************************************************************************
  2237. *
  2238. * This function sets the lplu d0 state according to the active flag. When
  2239. * activating lplu this function also disables smart speed and vise versa.
  2240. * lplu will not be activated unless the device autonegotiation advertisment
  2241. * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
  2242. * hw: Struct containing variables accessed by shared code
  2243. * active - true to enable lplu false to disable lplu.
  2244. *
  2245. * returns: - E1000_ERR_PHY if fail to read/write the PHY
  2246. * E1000_SUCCESS at any other case.
  2247. *
  2248. ****************************************************************************/
  2249. static int32_t
  2250. e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
  2251. {
  2252. uint32_t phy_ctrl = 0;
  2253. int32_t ret_val;
  2254. uint16_t phy_data;
  2255. DEBUGFUNC();
  2256. if (hw->mac_type <= e1000_82547_rev_2)
  2257. return E1000_SUCCESS;
  2258. if (hw->mac_type == e1000_ich8lan) {
  2259. phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
  2260. } else if (hw->mac_type == e1000_igb) {
  2261. phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL);
  2262. } else {
  2263. ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
  2264. &phy_data);
  2265. if (ret_val)
  2266. return ret_val;
  2267. }
  2268. if (!active) {
  2269. if (hw->mac_type == e1000_ich8lan) {
  2270. phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
  2271. E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
  2272. } else if (hw->mac_type == e1000_igb) {
  2273. phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
  2274. E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
  2275. } else {
  2276. phy_data &= ~IGP02E1000_PM_D0_LPLU;
  2277. ret_val = e1000_write_phy_reg(hw,
  2278. IGP02E1000_PHY_POWER_MGMT, phy_data);
  2279. if (ret_val)
  2280. return ret_val;
  2281. }
  2282. if (hw->mac_type == e1000_igb)
  2283. return E1000_SUCCESS;
  2284. /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
  2285. * Dx states where the power conservation is most important. During
  2286. * driver activity we should enable SmartSpeed, so performance is
  2287. * maintained. */
  2288. if (hw->smart_speed == e1000_smart_speed_on) {
  2289. ret_val = e1000_read_phy_reg(hw,
  2290. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2291. if (ret_val)
  2292. return ret_val;
  2293. phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
  2294. ret_val = e1000_write_phy_reg(hw,
  2295. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2296. if (ret_val)
  2297. return ret_val;
  2298. } else if (hw->smart_speed == e1000_smart_speed_off) {
  2299. ret_val = e1000_read_phy_reg(hw,
  2300. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2301. if (ret_val)
  2302. return ret_val;
  2303. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  2304. ret_val = e1000_write_phy_reg(hw,
  2305. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2306. if (ret_val)
  2307. return ret_val;
  2308. }
  2309. } else {
  2310. if (hw->mac_type == e1000_ich8lan) {
  2311. phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
  2312. E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
  2313. } else if (hw->mac_type == e1000_igb) {
  2314. phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
  2315. E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
  2316. } else {
  2317. phy_data |= IGP02E1000_PM_D0_LPLU;
  2318. ret_val = e1000_write_phy_reg(hw,
  2319. IGP02E1000_PHY_POWER_MGMT, phy_data);
  2320. if (ret_val)
  2321. return ret_val;
  2322. }
  2323. if (hw->mac_type == e1000_igb)
  2324. return E1000_SUCCESS;
  2325. /* When LPLU is enabled we should disable SmartSpeed */
  2326. ret_val = e1000_read_phy_reg(hw,
  2327. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2328. if (ret_val)
  2329. return ret_val;
  2330. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  2331. ret_val = e1000_write_phy_reg(hw,
  2332. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2333. if (ret_val)
  2334. return ret_val;
  2335. }
  2336. return E1000_SUCCESS;
  2337. }
  2338. /********************************************************************
  2339. * Copper link setup for e1000_phy_igp series.
  2340. *
  2341. * hw - Struct containing variables accessed by shared code
  2342. *********************************************************************/
  2343. static int32_t
  2344. e1000_copper_link_igp_setup(struct e1000_hw *hw)
  2345. {
  2346. uint32_t led_ctrl;
  2347. int32_t ret_val;
  2348. uint16_t phy_data;
  2349. DEBUGFUNC();
  2350. if (hw->phy_reset_disable)
  2351. return E1000_SUCCESS;
  2352. ret_val = e1000_phy_reset(hw);
  2353. if (ret_val) {
  2354. DEBUGOUT("Error Resetting the PHY\n");
  2355. return ret_val;
  2356. }
  2357. /* Wait 15ms for MAC to configure PHY from eeprom settings */
  2358. mdelay(15);
  2359. if (hw->mac_type != e1000_ich8lan) {
  2360. /* Configure activity LED after PHY reset */
  2361. led_ctrl = E1000_READ_REG(hw, LEDCTL);
  2362. led_ctrl &= IGP_ACTIVITY_LED_MASK;
  2363. led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
  2364. E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
  2365. }
  2366. /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
  2367. if (hw->phy_type == e1000_phy_igp) {
  2368. /* disable lplu d3 during driver init */
  2369. ret_val = e1000_set_d3_lplu_state(hw, false);
  2370. if (ret_val) {
  2371. DEBUGOUT("Error Disabling LPLU D3\n");
  2372. return ret_val;
  2373. }
  2374. }
  2375. /* disable lplu d0 during driver init */
  2376. ret_val = e1000_set_d0_lplu_state(hw, false);
  2377. if (ret_val) {
  2378. DEBUGOUT("Error Disabling LPLU D0\n");
  2379. return ret_val;
  2380. }
  2381. /* Configure mdi-mdix settings */
  2382. ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
  2383. if (ret_val)
  2384. return ret_val;
  2385. if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
  2386. hw->dsp_config_state = e1000_dsp_config_disabled;
  2387. /* Force MDI for earlier revs of the IGP PHY */
  2388. phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
  2389. | IGP01E1000_PSCR_FORCE_MDI_MDIX);
  2390. hw->mdix = 1;
  2391. } else {
  2392. hw->dsp_config_state = e1000_dsp_config_enabled;
  2393. phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
  2394. switch (hw->mdix) {
  2395. case 1:
  2396. phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
  2397. break;
  2398. case 2:
  2399. phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
  2400. break;
  2401. case 0:
  2402. default:
  2403. phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
  2404. break;
  2405. }
  2406. }
  2407. ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
  2408. if (ret_val)
  2409. return ret_val;
  2410. /* set auto-master slave resolution settings */
  2411. if (hw->autoneg) {
  2412. e1000_ms_type phy_ms_setting = hw->master_slave;
  2413. if (hw->ffe_config_state == e1000_ffe_config_active)
  2414. hw->ffe_config_state = e1000_ffe_config_enabled;
  2415. if (hw->dsp_config_state == e1000_dsp_config_activated)
  2416. hw->dsp_config_state = e1000_dsp_config_enabled;
  2417. /* when autonegotiation advertisment is only 1000Mbps then we
  2418. * should disable SmartSpeed and enable Auto MasterSlave
  2419. * resolution as hardware default. */
  2420. if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
  2421. /* Disable SmartSpeed */
  2422. ret_val = e1000_read_phy_reg(hw,
  2423. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2424. if (ret_val)
  2425. return ret_val;
  2426. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  2427. ret_val = e1000_write_phy_reg(hw,
  2428. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2429. if (ret_val)
  2430. return ret_val;
  2431. /* Set auto Master/Slave resolution process */
  2432. ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
  2433. &phy_data);
  2434. if (ret_val)
  2435. return ret_val;
  2436. phy_data &= ~CR_1000T_MS_ENABLE;
  2437. ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
  2438. phy_data);
  2439. if (ret_val)
  2440. return ret_val;
  2441. }
  2442. ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
  2443. if (ret_val)
  2444. return ret_val;
  2445. /* load defaults for future use */
  2446. hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
  2447. ((phy_data & CR_1000T_MS_VALUE) ?
  2448. e1000_ms_force_master :
  2449. e1000_ms_force_slave) :
  2450. e1000_ms_auto;
  2451. switch (phy_ms_setting) {
  2452. case e1000_ms_force_master:
  2453. phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
  2454. break;
  2455. case e1000_ms_force_slave:
  2456. phy_data |= CR_1000T_MS_ENABLE;
  2457. phy_data &= ~(CR_1000T_MS_VALUE);
  2458. break;
  2459. case e1000_ms_auto:
  2460. phy_data &= ~CR_1000T_MS_ENABLE;
  2461. default:
  2462. break;
  2463. }
  2464. ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
  2465. if (ret_val)
  2466. return ret_val;
  2467. }
  2468. return E1000_SUCCESS;
  2469. }
  2470. /*****************************************************************************
  2471. * This function checks the mode of the firmware.
  2472. *
  2473. * returns - true when the mode is IAMT or false.
  2474. ****************************************************************************/
  2475. bool
  2476. e1000_check_mng_mode(struct e1000_hw *hw)
  2477. {
  2478. uint32_t fwsm;
  2479. DEBUGFUNC();
  2480. fwsm = E1000_READ_REG(hw, FWSM);
  2481. if (hw->mac_type == e1000_ich8lan) {
  2482. if ((fwsm & E1000_FWSM_MODE_MASK) ==
  2483. (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
  2484. return true;
  2485. } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
  2486. (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
  2487. return true;
  2488. return false;
  2489. }
  2490. static int32_t
  2491. e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
  2492. {
  2493. uint16_t swfw = E1000_SWFW_PHY0_SM;
  2494. uint32_t reg_val;
  2495. DEBUGFUNC();
  2496. if (e1000_is_second_port(hw))
  2497. swfw = E1000_SWFW_PHY1_SM;
  2498. if (e1000_swfw_sync_acquire(hw, swfw))
  2499. return -E1000_ERR_SWFW_SYNC;
  2500. reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
  2501. & E1000_KUMCTRLSTA_OFFSET) | data;
  2502. E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
  2503. udelay(2);
  2504. return E1000_SUCCESS;
  2505. }
  2506. static int32_t
  2507. e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
  2508. {
  2509. uint16_t swfw = E1000_SWFW_PHY0_SM;
  2510. uint32_t reg_val;
  2511. DEBUGFUNC();
  2512. if (e1000_is_second_port(hw))
  2513. swfw = E1000_SWFW_PHY1_SM;
  2514. if (e1000_swfw_sync_acquire(hw, swfw)) {
  2515. debug("%s[%i]\n", __func__, __LINE__);
  2516. return -E1000_ERR_SWFW_SYNC;
  2517. }
  2518. /* Write register address */
  2519. reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
  2520. E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
  2521. E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
  2522. udelay(2);
  2523. /* Read the data returned */
  2524. reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
  2525. *data = (uint16_t)reg_val;
  2526. return E1000_SUCCESS;
  2527. }
  2528. /********************************************************************
  2529. * Copper link setup for e1000_phy_gg82563 series.
  2530. *
  2531. * hw - Struct containing variables accessed by shared code
  2532. *********************************************************************/
  2533. static int32_t
  2534. e1000_copper_link_ggp_setup(struct e1000_hw *hw)
  2535. {
  2536. int32_t ret_val;
  2537. uint16_t phy_data;
  2538. uint32_t reg_data;
  2539. DEBUGFUNC();
  2540. if (!hw->phy_reset_disable) {
  2541. /* Enable CRS on TX for half-duplex operation. */
  2542. ret_val = e1000_read_phy_reg(hw,
  2543. GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
  2544. if (ret_val)
  2545. return ret_val;
  2546. phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
  2547. /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
  2548. phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
  2549. ret_val = e1000_write_phy_reg(hw,
  2550. GG82563_PHY_MAC_SPEC_CTRL, phy_data);
  2551. if (ret_val)
  2552. return ret_val;
  2553. /* Options:
  2554. * MDI/MDI-X = 0 (default)
  2555. * 0 - Auto for all speeds
  2556. * 1 - MDI mode
  2557. * 2 - MDI-X mode
  2558. * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
  2559. */
  2560. ret_val = e1000_read_phy_reg(hw,
  2561. GG82563_PHY_SPEC_CTRL, &phy_data);
  2562. if (ret_val)
  2563. return ret_val;
  2564. phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
  2565. switch (hw->mdix) {
  2566. case 1:
  2567. phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
  2568. break;
  2569. case 2:
  2570. phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
  2571. break;
  2572. case 0:
  2573. default:
  2574. phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
  2575. break;
  2576. }
  2577. /* Options:
  2578. * disable_polarity_correction = 0 (default)
  2579. * Automatic Correction for Reversed Cable Polarity
  2580. * 0 - Disabled
  2581. * 1 - Enabled
  2582. */
  2583. phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
  2584. ret_val = e1000_write_phy_reg(hw,
  2585. GG82563_PHY_SPEC_CTRL, phy_data);
  2586. if (ret_val)
  2587. return ret_val;
  2588. /* SW Reset the PHY so all changes take effect */
  2589. ret_val = e1000_phy_reset(hw);
  2590. if (ret_val) {
  2591. DEBUGOUT("Error Resetting the PHY\n");
  2592. return ret_val;
  2593. }
  2594. } /* phy_reset_disable */
  2595. if (hw->mac_type == e1000_80003es2lan) {
  2596. /* Bypass RX and TX FIFO's */
  2597. ret_val = e1000_write_kmrn_reg(hw,
  2598. E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
  2599. E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
  2600. | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
  2601. if (ret_val)
  2602. return ret_val;
  2603. ret_val = e1000_read_phy_reg(hw,
  2604. GG82563_PHY_SPEC_CTRL_2, &phy_data);
  2605. if (ret_val)
  2606. return ret_val;
  2607. phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
  2608. ret_val = e1000_write_phy_reg(hw,
  2609. GG82563_PHY_SPEC_CTRL_2, phy_data);
  2610. if (ret_val)
  2611. return ret_val;
  2612. reg_data = E1000_READ_REG(hw, CTRL_EXT);
  2613. reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
  2614. E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
  2615. ret_val = e1000_read_phy_reg(hw,
  2616. GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
  2617. if (ret_val)
  2618. return ret_val;
  2619. /* Do not init these registers when the HW is in IAMT mode, since the
  2620. * firmware will have already initialized them. We only initialize
  2621. * them if the HW is not in IAMT mode.
  2622. */
  2623. if (e1000_check_mng_mode(hw) == false) {
  2624. /* Enable Electrical Idle on the PHY */
  2625. phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
  2626. ret_val = e1000_write_phy_reg(hw,
  2627. GG82563_PHY_PWR_MGMT_CTRL, phy_data);
  2628. if (ret_val)
  2629. return ret_val;
  2630. ret_val = e1000_read_phy_reg(hw,
  2631. GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
  2632. if (ret_val)
  2633. return ret_val;
  2634. phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
  2635. ret_val = e1000_write_phy_reg(hw,
  2636. GG82563_PHY_KMRN_MODE_CTRL, phy_data);
  2637. if (ret_val)
  2638. return ret_val;
  2639. }
  2640. /* Workaround: Disable padding in Kumeran interface in the MAC
  2641. * and in the PHY to avoid CRC errors.
  2642. */
  2643. ret_val = e1000_read_phy_reg(hw,
  2644. GG82563_PHY_INBAND_CTRL, &phy_data);
  2645. if (ret_val)
  2646. return ret_val;
  2647. phy_data |= GG82563_ICR_DIS_PADDING;
  2648. ret_val = e1000_write_phy_reg(hw,
  2649. GG82563_PHY_INBAND_CTRL, phy_data);
  2650. if (ret_val)
  2651. return ret_val;
  2652. }
  2653. return E1000_SUCCESS;
  2654. }
  2655. /********************************************************************
  2656. * Copper link setup for e1000_phy_m88 series.
  2657. *
  2658. * hw - Struct containing variables accessed by shared code
  2659. *********************************************************************/
  2660. static int32_t
  2661. e1000_copper_link_mgp_setup(struct e1000_hw *hw)
  2662. {
  2663. int32_t ret_val;
  2664. uint16_t phy_data;
  2665. DEBUGFUNC();
  2666. if (hw->phy_reset_disable)
  2667. return E1000_SUCCESS;
  2668. /* Enable CRS on TX. This must be set for half-duplex operation. */
  2669. ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
  2670. if (ret_val)
  2671. return ret_val;
  2672. phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
  2673. /* Options:
  2674. * MDI/MDI-X = 0 (default)
  2675. * 0 - Auto for all speeds
  2676. * 1 - MDI mode
  2677. * 2 - MDI-X mode
  2678. * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
  2679. */
  2680. phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
  2681. switch (hw->mdix) {
  2682. case 1:
  2683. phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
  2684. break;
  2685. case 2:
  2686. phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
  2687. break;
  2688. case 3:
  2689. phy_data |= M88E1000_PSCR_AUTO_X_1000T;
  2690. break;
  2691. case 0:
  2692. default:
  2693. phy_data |= M88E1000_PSCR_AUTO_X_MODE;
  2694. break;
  2695. }
  2696. /* Options:
  2697. * disable_polarity_correction = 0 (default)
  2698. * Automatic Correction for Reversed Cable Polarity
  2699. * 0 - Disabled
  2700. * 1 - Enabled
  2701. */
  2702. phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
  2703. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
  2704. if (ret_val)
  2705. return ret_val;
  2706. if (hw->phy_revision < M88E1011_I_REV_4) {
  2707. /* Force TX_CLK in the Extended PHY Specific Control Register
  2708. * to 25MHz clock.
  2709. */
  2710. ret_val = e1000_read_phy_reg(hw,
  2711. M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
  2712. if (ret_val)
  2713. return ret_val;
  2714. phy_data |= M88E1000_EPSCR_TX_CLK_25;
  2715. if ((hw->phy_revision == E1000_REVISION_2) &&
  2716. (hw->phy_id == M88E1111_I_PHY_ID)) {
  2717. /* Vidalia Phy, set the downshift counter to 5x */
  2718. phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
  2719. phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
  2720. ret_val = e1000_write_phy_reg(hw,
  2721. M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
  2722. if (ret_val)
  2723. return ret_val;
  2724. } else {
  2725. /* Configure Master and Slave downshift values */
  2726. phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
  2727. | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
  2728. phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
  2729. | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
  2730. ret_val = e1000_write_phy_reg(hw,
  2731. M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
  2732. if (ret_val)
  2733. return ret_val;
  2734. }
  2735. }
  2736. /* SW Reset the PHY so all changes take effect */
  2737. ret_val = e1000_phy_reset(hw);
  2738. if (ret_val) {
  2739. DEBUGOUT("Error Resetting the PHY\n");
  2740. return ret_val;
  2741. }
  2742. return E1000_SUCCESS;
  2743. }
  2744. /********************************************************************
  2745. * Setup auto-negotiation and flow control advertisements,
  2746. * and then perform auto-negotiation.
  2747. *
  2748. * hw - Struct containing variables accessed by shared code
  2749. *********************************************************************/
  2750. static int32_t
  2751. e1000_copper_link_autoneg(struct e1000_hw *hw)
  2752. {
  2753. int32_t ret_val;
  2754. uint16_t phy_data;
  2755. DEBUGFUNC();
  2756. /* Perform some bounds checking on the hw->autoneg_advertised
  2757. * parameter. If this variable is zero, then set it to the default.
  2758. */
  2759. hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
  2760. /* If autoneg_advertised is zero, we assume it was not defaulted
  2761. * by the calling code so we set to advertise full capability.
  2762. */
  2763. if (hw->autoneg_advertised == 0)
  2764. hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  2765. /* IFE phy only supports 10/100 */
  2766. if (hw->phy_type == e1000_phy_ife)
  2767. hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
  2768. DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
  2769. ret_val = e1000_phy_setup_autoneg(hw);
  2770. if (ret_val) {
  2771. DEBUGOUT("Error Setting up Auto-Negotiation\n");
  2772. return ret_val;
  2773. }
  2774. DEBUGOUT("Restarting Auto-Neg\n");
  2775. /* Restart auto-negotiation by setting the Auto Neg Enable bit and
  2776. * the Auto Neg Restart bit in the PHY control register.
  2777. */
  2778. ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
  2779. if (ret_val)
  2780. return ret_val;
  2781. phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
  2782. ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
  2783. if (ret_val)
  2784. return ret_val;
  2785. /* Does the user want to wait for Auto-Neg to complete here, or
  2786. * check at a later time (for example, callback routine).
  2787. */
  2788. /* If we do not wait for autonegtation to complete I
  2789. * do not see a valid link status.
  2790. * wait_autoneg_complete = 1 .
  2791. */
  2792. if (hw->wait_autoneg_complete) {
  2793. ret_val = e1000_wait_autoneg(hw);
  2794. if (ret_val) {
  2795. DEBUGOUT("Error while waiting for autoneg"
  2796. "to complete\n");
  2797. return ret_val;
  2798. }
  2799. }
  2800. hw->get_link_status = true;
  2801. return E1000_SUCCESS;
  2802. }
  2803. /******************************************************************************
  2804. * Config the MAC and the PHY after link is up.
  2805. * 1) Set up the MAC to the current PHY speed/duplex
  2806. * if we are on 82543. If we
  2807. * are on newer silicon, we only need to configure
  2808. * collision distance in the Transmit Control Register.
  2809. * 2) Set up flow control on the MAC to that established with
  2810. * the link partner.
  2811. * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
  2812. *
  2813. * hw - Struct containing variables accessed by shared code
  2814. ******************************************************************************/
  2815. static int32_t
  2816. e1000_copper_link_postconfig(struct e1000_hw *hw)
  2817. {
  2818. int32_t ret_val;
  2819. DEBUGFUNC();
  2820. if (hw->mac_type >= e1000_82544) {
  2821. e1000_config_collision_dist(hw);
  2822. } else {
  2823. ret_val = e1000_config_mac_to_phy(hw);
  2824. if (ret_val) {
  2825. DEBUGOUT("Error configuring MAC to PHY settings\n");
  2826. return ret_val;
  2827. }
  2828. }
  2829. ret_val = e1000_config_fc_after_link_up(hw);
  2830. if (ret_val) {
  2831. DEBUGOUT("Error Configuring Flow Control\n");
  2832. return ret_val;
  2833. }
  2834. return E1000_SUCCESS;
  2835. }
  2836. /******************************************************************************
  2837. * Detects which PHY is present and setup the speed and duplex
  2838. *
  2839. * hw - Struct containing variables accessed by shared code
  2840. ******************************************************************************/
  2841. static int
  2842. e1000_setup_copper_link(struct e1000_hw *hw)
  2843. {
  2844. int32_t ret_val;
  2845. uint16_t i;
  2846. uint16_t phy_data;
  2847. uint16_t reg_data;
  2848. DEBUGFUNC();
  2849. switch (hw->mac_type) {
  2850. case e1000_80003es2lan:
  2851. case e1000_ich8lan:
  2852. /* Set the mac to wait the maximum time between each
  2853. * iteration and increase the max iterations when
  2854. * polling the phy; this fixes erroneous timeouts at 10Mbps. */
  2855. ret_val = e1000_write_kmrn_reg(hw,
  2856. GG82563_REG(0x34, 4), 0xFFFF);
  2857. if (ret_val)
  2858. return ret_val;
  2859. ret_val = e1000_read_kmrn_reg(hw,
  2860. GG82563_REG(0x34, 9), &reg_data);
  2861. if (ret_val)
  2862. return ret_val;
  2863. reg_data |= 0x3F;
  2864. ret_val = e1000_write_kmrn_reg(hw,
  2865. GG82563_REG(0x34, 9), reg_data);
  2866. if (ret_val)
  2867. return ret_val;
  2868. default:
  2869. break;
  2870. }
  2871. /* Check if it is a valid PHY and set PHY mode if necessary. */
  2872. ret_val = e1000_copper_link_preconfig(hw);
  2873. if (ret_val)
  2874. return ret_val;
  2875. switch (hw->mac_type) {
  2876. case e1000_80003es2lan:
  2877. /* Kumeran registers are written-only */
  2878. reg_data =
  2879. E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
  2880. reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
  2881. ret_val = e1000_write_kmrn_reg(hw,
  2882. E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
  2883. if (ret_val)
  2884. return ret_val;
  2885. break;
  2886. default:
  2887. break;
  2888. }
  2889. if (hw->phy_type == e1000_phy_igp ||
  2890. hw->phy_type == e1000_phy_igp_3 ||
  2891. hw->phy_type == e1000_phy_igp_2) {
  2892. ret_val = e1000_copper_link_igp_setup(hw);
  2893. if (ret_val)
  2894. return ret_val;
  2895. } else if (hw->phy_type == e1000_phy_m88 ||
  2896. hw->phy_type == e1000_phy_igb) {
  2897. ret_val = e1000_copper_link_mgp_setup(hw);
  2898. if (ret_val)
  2899. return ret_val;
  2900. } else if (hw->phy_type == e1000_phy_gg82563) {
  2901. ret_val = e1000_copper_link_ggp_setup(hw);
  2902. if (ret_val)
  2903. return ret_val;
  2904. }
  2905. /* always auto */
  2906. /* Setup autoneg and flow control advertisement
  2907. * and perform autonegotiation */
  2908. ret_val = e1000_copper_link_autoneg(hw);
  2909. if (ret_val)
  2910. return ret_val;
  2911. /* Check link status. Wait up to 100 microseconds for link to become
  2912. * valid.
  2913. */
  2914. for (i = 0; i < 10; i++) {
  2915. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
  2916. if (ret_val)
  2917. return ret_val;
  2918. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
  2919. if (ret_val)
  2920. return ret_val;
  2921. if (phy_data & MII_SR_LINK_STATUS) {
  2922. /* Config the MAC and PHY after link is up */
  2923. ret_val = e1000_copper_link_postconfig(hw);
  2924. if (ret_val)
  2925. return ret_val;
  2926. DEBUGOUT("Valid link established!!!\n");
  2927. return E1000_SUCCESS;
  2928. }
  2929. udelay(10);
  2930. }
  2931. DEBUGOUT("Unable to establish link!!!\n");
  2932. return E1000_SUCCESS;
  2933. }
  2934. /******************************************************************************
  2935. * Configures PHY autoneg and flow control advertisement settings
  2936. *
  2937. * hw - Struct containing variables accessed by shared code
  2938. ******************************************************************************/
  2939. int32_t
  2940. e1000_phy_setup_autoneg(struct e1000_hw *hw)
  2941. {
  2942. int32_t ret_val;
  2943. uint16_t mii_autoneg_adv_reg;
  2944. uint16_t mii_1000t_ctrl_reg;
  2945. DEBUGFUNC();
  2946. /* Read the MII Auto-Neg Advertisement Register (Address 4). */
  2947. ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
  2948. if (ret_val)
  2949. return ret_val;
  2950. if (hw->phy_type != e1000_phy_ife) {
  2951. /* Read the MII 1000Base-T Control Register (Address 9). */
  2952. ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
  2953. &mii_1000t_ctrl_reg);
  2954. if (ret_val)
  2955. return ret_val;
  2956. } else
  2957. mii_1000t_ctrl_reg = 0;
  2958. /* Need to parse both autoneg_advertised and fc and set up
  2959. * the appropriate PHY registers. First we will parse for
  2960. * autoneg_advertised software override. Since we can advertise
  2961. * a plethora of combinations, we need to check each bit
  2962. * individually.
  2963. */
  2964. /* First we clear all the 10/100 mb speed bits in the Auto-Neg
  2965. * Advertisement Register (Address 4) and the 1000 mb speed bits in
  2966. * the 1000Base-T Control Register (Address 9).
  2967. */
  2968. mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
  2969. mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
  2970. DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
  2971. /* Do we want to advertise 10 Mb Half Duplex? */
  2972. if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
  2973. DEBUGOUT("Advertise 10mb Half duplex\n");
  2974. mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
  2975. }
  2976. /* Do we want to advertise 10 Mb Full Duplex? */
  2977. if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
  2978. DEBUGOUT("Advertise 10mb Full duplex\n");
  2979. mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
  2980. }
  2981. /* Do we want to advertise 100 Mb Half Duplex? */
  2982. if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
  2983. DEBUGOUT("Advertise 100mb Half duplex\n");
  2984. mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
  2985. }
  2986. /* Do we want to advertise 100 Mb Full Duplex? */
  2987. if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
  2988. DEBUGOUT("Advertise 100mb Full duplex\n");
  2989. mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
  2990. }
  2991. /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
  2992. if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
  2993. DEBUGOUT
  2994. ("Advertise 1000mb Half duplex requested, request denied!\n");
  2995. }
  2996. /* Do we want to advertise 1000 Mb Full Duplex? */
  2997. if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
  2998. DEBUGOUT("Advertise 1000mb Full duplex\n");
  2999. mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
  3000. }
  3001. /* Check for a software override of the flow control settings, and
  3002. * setup the PHY advertisement registers accordingly. If
  3003. * auto-negotiation is enabled, then software will have to set the
  3004. * "PAUSE" bits to the correct value in the Auto-Negotiation
  3005. * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
  3006. *
  3007. * The possible values of the "fc" parameter are:
  3008. * 0: Flow control is completely disabled
  3009. * 1: Rx flow control is enabled (we can receive pause frames
  3010. * but not send pause frames).
  3011. * 2: Tx flow control is enabled (we can send pause frames
  3012. * but we do not support receiving pause frames).
  3013. * 3: Both Rx and TX flow control (symmetric) are enabled.
  3014. * other: No software override. The flow control configuration
  3015. * in the EEPROM is used.
  3016. */
  3017. switch (hw->fc) {
  3018. case e1000_fc_none: /* 0 */
  3019. /* Flow control (RX & TX) is completely disabled by a
  3020. * software over-ride.
  3021. */
  3022. mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  3023. break;
  3024. case e1000_fc_rx_pause: /* 1 */
  3025. /* RX Flow control is enabled, and TX Flow control is
  3026. * disabled, by a software over-ride.
  3027. */
  3028. /* Since there really isn't a way to advertise that we are
  3029. * capable of RX Pause ONLY, we will advertise that we
  3030. * support both symmetric and asymmetric RX PAUSE. Later
  3031. * (in e1000_config_fc_after_link_up) we will disable the
  3032. *hw's ability to send PAUSE frames.
  3033. */
  3034. mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  3035. break;
  3036. case e1000_fc_tx_pause: /* 2 */
  3037. /* TX Flow control is enabled, and RX Flow control is
  3038. * disabled, by a software over-ride.
  3039. */
  3040. mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
  3041. mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
  3042. break;
  3043. case e1000_fc_full: /* 3 */
  3044. /* Flow control (both RX and TX) is enabled by a software
  3045. * over-ride.
  3046. */
  3047. mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  3048. break;
  3049. default:
  3050. DEBUGOUT("Flow control param set incorrectly\n");
  3051. return -E1000_ERR_CONFIG;
  3052. }
  3053. ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
  3054. if (ret_val)
  3055. return ret_val;
  3056. DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
  3057. if (hw->phy_type != e1000_phy_ife) {
  3058. ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
  3059. mii_1000t_ctrl_reg);
  3060. if (ret_val)
  3061. return ret_val;
  3062. }
  3063. return E1000_SUCCESS;
  3064. }
  3065. /******************************************************************************
  3066. * Sets the collision distance in the Transmit Control register
  3067. *
  3068. * hw - Struct containing variables accessed by shared code
  3069. *
  3070. * Link should have been established previously. Reads the speed and duplex
  3071. * information from the Device Status register.
  3072. ******************************************************************************/
  3073. static void
  3074. e1000_config_collision_dist(struct e1000_hw *hw)
  3075. {
  3076. uint32_t tctl, coll_dist;
  3077. DEBUGFUNC();
  3078. if (hw->mac_type < e1000_82543)
  3079. coll_dist = E1000_COLLISION_DISTANCE_82542;
  3080. else
  3081. coll_dist = E1000_COLLISION_DISTANCE;
  3082. tctl = E1000_READ_REG(hw, TCTL);
  3083. tctl &= ~E1000_TCTL_COLD;
  3084. tctl |= coll_dist << E1000_COLD_SHIFT;
  3085. E1000_WRITE_REG(hw, TCTL, tctl);
  3086. E1000_WRITE_FLUSH(hw);
  3087. }
  3088. /******************************************************************************
  3089. * Sets MAC speed and duplex settings to reflect the those in the PHY
  3090. *
  3091. * hw - Struct containing variables accessed by shared code
  3092. * mii_reg - data to write to the MII control register
  3093. *
  3094. * The contents of the PHY register containing the needed information need to
  3095. * be passed in.
  3096. ******************************************************************************/
  3097. static int
  3098. e1000_config_mac_to_phy(struct e1000_hw *hw)
  3099. {
  3100. uint32_t ctrl;
  3101. uint16_t phy_data;
  3102. DEBUGFUNC();
  3103. /* Read the Device Control Register and set the bits to Force Speed
  3104. * and Duplex.
  3105. */
  3106. ctrl = E1000_READ_REG(hw, CTRL);
  3107. ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
  3108. ctrl &= ~(E1000_CTRL_ILOS);
  3109. ctrl |= (E1000_CTRL_SPD_SEL);
  3110. /* Set up duplex in the Device Control and Transmit Control
  3111. * registers depending on negotiated values.
  3112. */
  3113. if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
  3114. DEBUGOUT("PHY Read Error\n");
  3115. return -E1000_ERR_PHY;
  3116. }
  3117. if (phy_data & M88E1000_PSSR_DPLX)
  3118. ctrl |= E1000_CTRL_FD;
  3119. else
  3120. ctrl &= ~E1000_CTRL_FD;
  3121. e1000_config_collision_dist(hw);
  3122. /* Set up speed in the Device Control register depending on
  3123. * negotiated values.
  3124. */
  3125. if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
  3126. ctrl |= E1000_CTRL_SPD_1000;
  3127. else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
  3128. ctrl |= E1000_CTRL_SPD_100;
  3129. /* Write the configured values back to the Device Control Reg. */
  3130. E1000_WRITE_REG(hw, CTRL, ctrl);
  3131. return 0;
  3132. }
  3133. /******************************************************************************
  3134. * Forces the MAC's flow control settings.
  3135. *
  3136. * hw - Struct containing variables accessed by shared code
  3137. *
  3138. * Sets the TFCE and RFCE bits in the device control register to reflect
  3139. * the adapter settings. TFCE and RFCE need to be explicitly set by
  3140. * software when a Copper PHY is used because autonegotiation is managed
  3141. * by the PHY rather than the MAC. Software must also configure these
  3142. * bits when link is forced on a fiber connection.
  3143. *****************************************************************************/
  3144. static int
  3145. e1000_force_mac_fc(struct e1000_hw *hw)
  3146. {
  3147. uint32_t ctrl;
  3148. DEBUGFUNC();
  3149. /* Get the current configuration of the Device Control Register */
  3150. ctrl = E1000_READ_REG(hw, CTRL);
  3151. /* Because we didn't get link via the internal auto-negotiation
  3152. * mechanism (we either forced link or we got link via PHY
  3153. * auto-neg), we have to manually enable/disable transmit an
  3154. * receive flow control.
  3155. *
  3156. * The "Case" statement below enables/disable flow control
  3157. * according to the "hw->fc" parameter.
  3158. *
  3159. * The possible values of the "fc" parameter are:
  3160. * 0: Flow control is completely disabled
  3161. * 1: Rx flow control is enabled (we can receive pause
  3162. * frames but not send pause frames).
  3163. * 2: Tx flow control is enabled (we can send pause frames
  3164. * frames but we do not receive pause frames).
  3165. * 3: Both Rx and TX flow control (symmetric) is enabled.
  3166. * other: No other values should be possible at this point.
  3167. */
  3168. switch (hw->fc) {
  3169. case e1000_fc_none:
  3170. ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
  3171. break;
  3172. case e1000_fc_rx_pause:
  3173. ctrl &= (~E1000_CTRL_TFCE);
  3174. ctrl |= E1000_CTRL_RFCE;
  3175. break;
  3176. case e1000_fc_tx_pause:
  3177. ctrl &= (~E1000_CTRL_RFCE);
  3178. ctrl |= E1000_CTRL_TFCE;
  3179. break;
  3180. case e1000_fc_full:
  3181. ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
  3182. break;
  3183. default:
  3184. DEBUGOUT("Flow control param set incorrectly\n");
  3185. return -E1000_ERR_CONFIG;
  3186. }
  3187. /* Disable TX Flow Control for 82542 (rev 2.0) */
  3188. if (hw->mac_type == e1000_82542_rev2_0)
  3189. ctrl &= (~E1000_CTRL_TFCE);
  3190. E1000_WRITE_REG(hw, CTRL, ctrl);
  3191. return 0;
  3192. }
  3193. /******************************************************************************
  3194. * Configures flow control settings after link is established
  3195. *
  3196. * hw - Struct containing variables accessed by shared code
  3197. *
  3198. * Should be called immediately after a valid link has been established.
  3199. * Forces MAC flow control settings if link was forced. When in MII/GMII mode
  3200. * and autonegotiation is enabled, the MAC flow control settings will be set
  3201. * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
  3202. * and RFCE bits will be automaticaly set to the negotiated flow control mode.
  3203. *****************************************************************************/
  3204. static int32_t
  3205. e1000_config_fc_after_link_up(struct e1000_hw *hw)
  3206. {
  3207. int32_t ret_val;
  3208. uint16_t mii_status_reg;
  3209. uint16_t mii_nway_adv_reg;
  3210. uint16_t mii_nway_lp_ability_reg;
  3211. uint16_t speed;
  3212. uint16_t duplex;
  3213. DEBUGFUNC();
  3214. /* Check for the case where we have fiber media and auto-neg failed
  3215. * so we had to force link. In this case, we need to force the
  3216. * configuration of the MAC to match the "fc" parameter.
  3217. */
  3218. if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
  3219. || ((hw->media_type == e1000_media_type_internal_serdes)
  3220. && (hw->autoneg_failed))
  3221. || ((hw->media_type == e1000_media_type_copper)
  3222. && (!hw->autoneg))) {
  3223. ret_val = e1000_force_mac_fc(hw);
  3224. if (ret_val < 0) {
  3225. DEBUGOUT("Error forcing flow control settings\n");
  3226. return ret_val;
  3227. }
  3228. }
  3229. /* Check for the case where we have copper media and auto-neg is
  3230. * enabled. In this case, we need to check and see if Auto-Neg
  3231. * has completed, and if so, how the PHY and link partner has
  3232. * flow control configured.
  3233. */
  3234. if (hw->media_type == e1000_media_type_copper) {
  3235. /* Read the MII Status Register and check to see if AutoNeg
  3236. * has completed. We read this twice because this reg has
  3237. * some "sticky" (latched) bits.
  3238. */
  3239. if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
  3240. DEBUGOUT("PHY Read Error\n");
  3241. return -E1000_ERR_PHY;
  3242. }
  3243. if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
  3244. DEBUGOUT("PHY Read Error\n");
  3245. return -E1000_ERR_PHY;
  3246. }
  3247. if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
  3248. /* The AutoNeg process has completed, so we now need to
  3249. * read both the Auto Negotiation Advertisement Register
  3250. * (Address 4) and the Auto_Negotiation Base Page Ability
  3251. * Register (Address 5) to determine how flow control was
  3252. * negotiated.
  3253. */
  3254. if (e1000_read_phy_reg
  3255. (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
  3256. DEBUGOUT("PHY Read Error\n");
  3257. return -E1000_ERR_PHY;
  3258. }
  3259. if (e1000_read_phy_reg
  3260. (hw, PHY_LP_ABILITY,
  3261. &mii_nway_lp_ability_reg) < 0) {
  3262. DEBUGOUT("PHY Read Error\n");
  3263. return -E1000_ERR_PHY;
  3264. }
  3265. /* Two bits in the Auto Negotiation Advertisement Register
  3266. * (Address 4) and two bits in the Auto Negotiation Base
  3267. * Page Ability Register (Address 5) determine flow control
  3268. * for both the PHY and the link partner. The following
  3269. * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
  3270. * 1999, describes these PAUSE resolution bits and how flow
  3271. * control is determined based upon these settings.
  3272. * NOTE: DC = Don't Care
  3273. *
  3274. * LOCAL DEVICE | LINK PARTNER
  3275. * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
  3276. *-------|---------|-------|---------|--------------------
  3277. * 0 | 0 | DC | DC | e1000_fc_none
  3278. * 0 | 1 | 0 | DC | e1000_fc_none
  3279. * 0 | 1 | 1 | 0 | e1000_fc_none
  3280. * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
  3281. * 1 | 0 | 0 | DC | e1000_fc_none
  3282. * 1 | DC | 1 | DC | e1000_fc_full
  3283. * 1 | 1 | 0 | 0 | e1000_fc_none
  3284. * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
  3285. *
  3286. */
  3287. /* Are both PAUSE bits set to 1? If so, this implies
  3288. * Symmetric Flow Control is enabled at both ends. The
  3289. * ASM_DIR bits are irrelevant per the spec.
  3290. *
  3291. * For Symmetric Flow Control:
  3292. *
  3293. * LOCAL DEVICE | LINK PARTNER
  3294. * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
  3295. *-------|---------|-------|---------|--------------------
  3296. * 1 | DC | 1 | DC | e1000_fc_full
  3297. *
  3298. */
  3299. if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
  3300. (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
  3301. /* Now we need to check if the user selected RX ONLY
  3302. * of pause frames. In this case, we had to advertise
  3303. * FULL flow control because we could not advertise RX
  3304. * ONLY. Hence, we must now check to see if we need to
  3305. * turn OFF the TRANSMISSION of PAUSE frames.
  3306. */
  3307. if (hw->original_fc == e1000_fc_full) {
  3308. hw->fc = e1000_fc_full;
  3309. DEBUGOUT("Flow Control = FULL.\r\n");
  3310. } else {
  3311. hw->fc = e1000_fc_rx_pause;
  3312. DEBUGOUT
  3313. ("Flow Control = RX PAUSE frames only.\r\n");
  3314. }
  3315. }
  3316. /* For receiving PAUSE frames ONLY.
  3317. *
  3318. * LOCAL DEVICE | LINK PARTNER
  3319. * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
  3320. *-------|---------|-------|---------|--------------------
  3321. * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
  3322. *
  3323. */
  3324. else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
  3325. (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
  3326. (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
  3327. (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
  3328. {
  3329. hw->fc = e1000_fc_tx_pause;
  3330. DEBUGOUT
  3331. ("Flow Control = TX PAUSE frames only.\r\n");
  3332. }
  3333. /* For transmitting PAUSE frames ONLY.
  3334. *
  3335. * LOCAL DEVICE | LINK PARTNER
  3336. * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
  3337. *-------|---------|-------|---------|--------------------
  3338. * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
  3339. *
  3340. */
  3341. else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
  3342. (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
  3343. !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
  3344. (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
  3345. {
  3346. hw->fc = e1000_fc_rx_pause;
  3347. DEBUGOUT
  3348. ("Flow Control = RX PAUSE frames only.\r\n");
  3349. }
  3350. /* Per the IEEE spec, at this point flow control should be
  3351. * disabled. However, we want to consider that we could
  3352. * be connected to a legacy switch that doesn't advertise
  3353. * desired flow control, but can be forced on the link
  3354. * partner. So if we advertised no flow control, that is
  3355. * what we will resolve to. If we advertised some kind of
  3356. * receive capability (Rx Pause Only or Full Flow Control)
  3357. * and the link partner advertised none, we will configure
  3358. * ourselves to enable Rx Flow Control only. We can do
  3359. * this safely for two reasons: If the link partner really
  3360. * didn't want flow control enabled, and we enable Rx, no
  3361. * harm done since we won't be receiving any PAUSE frames
  3362. * anyway. If the intent on the link partner was to have
  3363. * flow control enabled, then by us enabling RX only, we
  3364. * can at least receive pause frames and process them.
  3365. * This is a good idea because in most cases, since we are
  3366. * predominantly a server NIC, more times than not we will
  3367. * be asked to delay transmission of packets than asking
  3368. * our link partner to pause transmission of frames.
  3369. */
  3370. else if (hw->original_fc == e1000_fc_none ||
  3371. hw->original_fc == e1000_fc_tx_pause) {
  3372. hw->fc = e1000_fc_none;
  3373. DEBUGOUT("Flow Control = NONE.\r\n");
  3374. } else {
  3375. hw->fc = e1000_fc_rx_pause;
  3376. DEBUGOUT
  3377. ("Flow Control = RX PAUSE frames only.\r\n");
  3378. }
  3379. /* Now we need to do one last check... If we auto-
  3380. * negotiated to HALF DUPLEX, flow control should not be
  3381. * enabled per IEEE 802.3 spec.
  3382. */
  3383. e1000_get_speed_and_duplex(hw, &speed, &duplex);
  3384. if (duplex == HALF_DUPLEX)
  3385. hw->fc = e1000_fc_none;
  3386. /* Now we call a subroutine to actually force the MAC
  3387. * controller to use the correct flow control settings.
  3388. */
  3389. ret_val = e1000_force_mac_fc(hw);
  3390. if (ret_val < 0) {
  3391. DEBUGOUT
  3392. ("Error forcing flow control settings\n");
  3393. return ret_val;
  3394. }
  3395. } else {
  3396. DEBUGOUT
  3397. ("Copper PHY and Auto Neg has not completed.\r\n");
  3398. }
  3399. }
  3400. return E1000_SUCCESS;
  3401. }
  3402. /******************************************************************************
  3403. * Checks to see if the link status of the hardware has changed.
  3404. *
  3405. * hw - Struct containing variables accessed by shared code
  3406. *
  3407. * Called by any function that needs to check the link status of the adapter.
  3408. *****************************************************************************/
  3409. static int
  3410. e1000_check_for_link(struct e1000_hw *hw)
  3411. {
  3412. uint32_t rxcw;
  3413. uint32_t ctrl;
  3414. uint32_t status;
  3415. uint32_t rctl;
  3416. uint32_t signal;
  3417. int32_t ret_val;
  3418. uint16_t phy_data;
  3419. uint16_t lp_capability;
  3420. DEBUGFUNC();
  3421. /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
  3422. * set when the optics detect a signal. On older adapters, it will be
  3423. * cleared when there is a signal
  3424. */
  3425. ctrl = E1000_READ_REG(hw, CTRL);
  3426. if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
  3427. signal = E1000_CTRL_SWDPIN1;
  3428. else
  3429. signal = 0;
  3430. status = E1000_READ_REG(hw, STATUS);
  3431. rxcw = E1000_READ_REG(hw, RXCW);
  3432. DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
  3433. /* If we have a copper PHY then we only want to go out to the PHY
  3434. * registers to see if Auto-Neg has completed and/or if our link
  3435. * status has changed. The get_link_status flag will be set if we
  3436. * receive a Link Status Change interrupt or we have Rx Sequence
  3437. * Errors.
  3438. */
  3439. if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
  3440. /* First we want to see if the MII Status Register reports
  3441. * link. If so, then we want to get the current speed/duplex
  3442. * of the PHY.
  3443. * Read the register twice since the link bit is sticky.
  3444. */
  3445. if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  3446. DEBUGOUT("PHY Read Error\n");
  3447. return -E1000_ERR_PHY;
  3448. }
  3449. if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  3450. DEBUGOUT("PHY Read Error\n");
  3451. return -E1000_ERR_PHY;
  3452. }
  3453. if (phy_data & MII_SR_LINK_STATUS) {
  3454. hw->get_link_status = false;
  3455. } else {
  3456. /* No link detected */
  3457. return -E1000_ERR_NOLINK;
  3458. }
  3459. /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
  3460. * have Si on board that is 82544 or newer, Auto
  3461. * Speed Detection takes care of MAC speed/duplex
  3462. * configuration. So we only need to configure Collision
  3463. * Distance in the MAC. Otherwise, we need to force
  3464. * speed/duplex on the MAC to the current PHY speed/duplex
  3465. * settings.
  3466. */
  3467. if (hw->mac_type >= e1000_82544)
  3468. e1000_config_collision_dist(hw);
  3469. else {
  3470. ret_val = e1000_config_mac_to_phy(hw);
  3471. if (ret_val < 0) {
  3472. DEBUGOUT
  3473. ("Error configuring MAC to PHY settings\n");
  3474. return ret_val;
  3475. }
  3476. }
  3477. /* Configure Flow Control now that Auto-Neg has completed. First, we
  3478. * need to restore the desired flow control settings because we may
  3479. * have had to re-autoneg with a different link partner.
  3480. */
  3481. ret_val = e1000_config_fc_after_link_up(hw);
  3482. if (ret_val < 0) {
  3483. DEBUGOUT("Error configuring flow control\n");
  3484. return ret_val;
  3485. }
  3486. /* At this point we know that we are on copper and we have
  3487. * auto-negotiated link. These are conditions for checking the link
  3488. * parter capability register. We use the link partner capability to
  3489. * determine if TBI Compatibility needs to be turned on or off. If
  3490. * the link partner advertises any speed in addition to Gigabit, then
  3491. * we assume that they are GMII-based, and TBI compatibility is not
  3492. * needed. If no other speeds are advertised, we assume the link
  3493. * partner is TBI-based, and we turn on TBI Compatibility.
  3494. */
  3495. if (hw->tbi_compatibility_en) {
  3496. if (e1000_read_phy_reg
  3497. (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
  3498. DEBUGOUT("PHY Read Error\n");
  3499. return -E1000_ERR_PHY;
  3500. }
  3501. if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
  3502. NWAY_LPAR_10T_FD_CAPS |
  3503. NWAY_LPAR_100TX_HD_CAPS |
  3504. NWAY_LPAR_100TX_FD_CAPS |
  3505. NWAY_LPAR_100T4_CAPS)) {
  3506. /* If our link partner advertises anything in addition to
  3507. * gigabit, we do not need to enable TBI compatibility.
  3508. */
  3509. if (hw->tbi_compatibility_on) {
  3510. /* If we previously were in the mode, turn it off. */
  3511. rctl = E1000_READ_REG(hw, RCTL);
  3512. rctl &= ~E1000_RCTL_SBP;
  3513. E1000_WRITE_REG(hw, RCTL, rctl);
  3514. hw->tbi_compatibility_on = false;
  3515. }
  3516. } else {
  3517. /* If TBI compatibility is was previously off, turn it on. For
  3518. * compatibility with a TBI link partner, we will store bad
  3519. * packets. Some frames have an additional byte on the end and
  3520. * will look like CRC errors to to the hardware.
  3521. */
  3522. if (!hw->tbi_compatibility_on) {
  3523. hw->tbi_compatibility_on = true;
  3524. rctl = E1000_READ_REG(hw, RCTL);
  3525. rctl |= E1000_RCTL_SBP;
  3526. E1000_WRITE_REG(hw, RCTL, rctl);
  3527. }
  3528. }
  3529. }
  3530. }
  3531. /* If we don't have link (auto-negotiation failed or link partner cannot
  3532. * auto-negotiate), the cable is plugged in (we have signal), and our
  3533. * link partner is not trying to auto-negotiate with us (we are receiving
  3534. * idles or data), we need to force link up. We also need to give
  3535. * auto-negotiation time to complete, in case the cable was just plugged
  3536. * in. The autoneg_failed flag does this.
  3537. */
  3538. else if ((hw->media_type == e1000_media_type_fiber) &&
  3539. (!(status & E1000_STATUS_LU)) &&
  3540. ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
  3541. (!(rxcw & E1000_RXCW_C))) {
  3542. if (hw->autoneg_failed == 0) {
  3543. hw->autoneg_failed = 1;
  3544. return 0;
  3545. }
  3546. DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
  3547. /* Disable auto-negotiation in the TXCW register */
  3548. E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
  3549. /* Force link-up and also force full-duplex. */
  3550. ctrl = E1000_READ_REG(hw, CTRL);
  3551. ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
  3552. E1000_WRITE_REG(hw, CTRL, ctrl);
  3553. /* Configure Flow Control after forcing link up. */
  3554. ret_val = e1000_config_fc_after_link_up(hw);
  3555. if (ret_val < 0) {
  3556. DEBUGOUT("Error configuring flow control\n");
  3557. return ret_val;
  3558. }
  3559. }
  3560. /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
  3561. * auto-negotiation in the TXCW register and disable forced link in the
  3562. * Device Control register in an attempt to auto-negotiate with our link
  3563. * partner.
  3564. */
  3565. else if ((hw->media_type == e1000_media_type_fiber) &&
  3566. (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
  3567. DEBUGOUT
  3568. ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
  3569. E1000_WRITE_REG(hw, TXCW, hw->txcw);
  3570. E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
  3571. }
  3572. return 0;
  3573. }
  3574. /******************************************************************************
  3575. * Configure the MAC-to-PHY interface for 10/100Mbps
  3576. *
  3577. * hw - Struct containing variables accessed by shared code
  3578. ******************************************************************************/
  3579. static int32_t
  3580. e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
  3581. {
  3582. int32_t ret_val = E1000_SUCCESS;
  3583. uint32_t tipg;
  3584. uint16_t reg_data;
  3585. DEBUGFUNC();
  3586. reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
  3587. ret_val = e1000_write_kmrn_reg(hw,
  3588. E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
  3589. if (ret_val)
  3590. return ret_val;
  3591. /* Configure Transmit Inter-Packet Gap */
  3592. tipg = E1000_READ_REG(hw, TIPG);
  3593. tipg &= ~E1000_TIPG_IPGT_MASK;
  3594. tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
  3595. E1000_WRITE_REG(hw, TIPG, tipg);
  3596. ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
  3597. if (ret_val)
  3598. return ret_val;
  3599. if (duplex == HALF_DUPLEX)
  3600. reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
  3601. else
  3602. reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
  3603. ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
  3604. return ret_val;
  3605. }
  3606. static int32_t
  3607. e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
  3608. {
  3609. int32_t ret_val = E1000_SUCCESS;
  3610. uint16_t reg_data;
  3611. uint32_t tipg;
  3612. DEBUGFUNC();
  3613. reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
  3614. ret_val = e1000_write_kmrn_reg(hw,
  3615. E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
  3616. if (ret_val)
  3617. return ret_val;
  3618. /* Configure Transmit Inter-Packet Gap */
  3619. tipg = E1000_READ_REG(hw, TIPG);
  3620. tipg &= ~E1000_TIPG_IPGT_MASK;
  3621. tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
  3622. E1000_WRITE_REG(hw, TIPG, tipg);
  3623. ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
  3624. if (ret_val)
  3625. return ret_val;
  3626. reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
  3627. ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
  3628. return ret_val;
  3629. }
  3630. /******************************************************************************
  3631. * Detects the current speed and duplex settings of the hardware.
  3632. *
  3633. * hw - Struct containing variables accessed by shared code
  3634. * speed - Speed of the connection
  3635. * duplex - Duplex setting of the connection
  3636. *****************************************************************************/
  3637. static int
  3638. e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
  3639. uint16_t *duplex)
  3640. {
  3641. uint32_t status;
  3642. int32_t ret_val;
  3643. uint16_t phy_data;
  3644. DEBUGFUNC();
  3645. if (hw->mac_type >= e1000_82543) {
  3646. status = E1000_READ_REG(hw, STATUS);
  3647. if (status & E1000_STATUS_SPEED_1000) {
  3648. *speed = SPEED_1000;
  3649. DEBUGOUT("1000 Mbs, ");
  3650. } else if (status & E1000_STATUS_SPEED_100) {
  3651. *speed = SPEED_100;
  3652. DEBUGOUT("100 Mbs, ");
  3653. } else {
  3654. *speed = SPEED_10;
  3655. DEBUGOUT("10 Mbs, ");
  3656. }
  3657. if (status & E1000_STATUS_FD) {
  3658. *duplex = FULL_DUPLEX;
  3659. DEBUGOUT("Full Duplex\r\n");
  3660. } else {
  3661. *duplex = HALF_DUPLEX;
  3662. DEBUGOUT(" Half Duplex\r\n");
  3663. }
  3664. } else {
  3665. DEBUGOUT("1000 Mbs, Full Duplex\r\n");
  3666. *speed = SPEED_1000;
  3667. *duplex = FULL_DUPLEX;
  3668. }
  3669. /* IGP01 PHY may advertise full duplex operation after speed downgrade
  3670. * even if it is operating at half duplex. Here we set the duplex
  3671. * settings to match the duplex in the link partner's capabilities.
  3672. */
  3673. if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
  3674. ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
  3675. if (ret_val)
  3676. return ret_val;
  3677. if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
  3678. *duplex = HALF_DUPLEX;
  3679. else {
  3680. ret_val = e1000_read_phy_reg(hw,
  3681. PHY_LP_ABILITY, &phy_data);
  3682. if (ret_val)
  3683. return ret_val;
  3684. if ((*speed == SPEED_100 &&
  3685. !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
  3686. || (*speed == SPEED_10
  3687. && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
  3688. *duplex = HALF_DUPLEX;
  3689. }
  3690. }
  3691. if ((hw->mac_type == e1000_80003es2lan) &&
  3692. (hw->media_type == e1000_media_type_copper)) {
  3693. if (*speed == SPEED_1000)
  3694. ret_val = e1000_configure_kmrn_for_1000(hw);
  3695. else
  3696. ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
  3697. if (ret_val)
  3698. return ret_val;
  3699. }
  3700. return E1000_SUCCESS;
  3701. }
  3702. /******************************************************************************
  3703. * Blocks until autoneg completes or times out (~4.5 seconds)
  3704. *
  3705. * hw - Struct containing variables accessed by shared code
  3706. ******************************************************************************/
  3707. static int
  3708. e1000_wait_autoneg(struct e1000_hw *hw)
  3709. {
  3710. uint16_t i;
  3711. uint16_t phy_data;
  3712. DEBUGFUNC();
  3713. DEBUGOUT("Waiting for Auto-Neg to complete.\n");
  3714. /* We will wait for autoneg to complete or timeout to expire. */
  3715. for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
  3716. /* Read the MII Status Register and wait for Auto-Neg
  3717. * Complete bit to be set.
  3718. */
  3719. if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  3720. DEBUGOUT("PHY Read Error\n");
  3721. return -E1000_ERR_PHY;
  3722. }
  3723. if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  3724. DEBUGOUT("PHY Read Error\n");
  3725. return -E1000_ERR_PHY;
  3726. }
  3727. if (phy_data & MII_SR_AUTONEG_COMPLETE) {
  3728. DEBUGOUT("Auto-Neg complete.\n");
  3729. return 0;
  3730. }
  3731. mdelay(100);
  3732. }
  3733. DEBUGOUT("Auto-Neg timedout.\n");
  3734. return -E1000_ERR_TIMEOUT;
  3735. }
  3736. /******************************************************************************
  3737. * Raises the Management Data Clock
  3738. *
  3739. * hw - Struct containing variables accessed by shared code
  3740. * ctrl - Device control register's current value
  3741. ******************************************************************************/
  3742. static void
  3743. e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
  3744. {
  3745. /* Raise the clock input to the Management Data Clock (by setting the MDC
  3746. * bit), and then delay 2 microseconds.
  3747. */
  3748. E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
  3749. E1000_WRITE_FLUSH(hw);
  3750. udelay(2);
  3751. }
  3752. /******************************************************************************
  3753. * Lowers the Management Data Clock
  3754. *
  3755. * hw - Struct containing variables accessed by shared code
  3756. * ctrl - Device control register's current value
  3757. ******************************************************************************/
  3758. static void
  3759. e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
  3760. {
  3761. /* Lower the clock input to the Management Data Clock (by clearing the MDC
  3762. * bit), and then delay 2 microseconds.
  3763. */
  3764. E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
  3765. E1000_WRITE_FLUSH(hw);
  3766. udelay(2);
  3767. }
  3768. /******************************************************************************
  3769. * Shifts data bits out to the PHY
  3770. *
  3771. * hw - Struct containing variables accessed by shared code
  3772. * data - Data to send out to the PHY
  3773. * count - Number of bits to shift out
  3774. *
  3775. * Bits are shifted out in MSB to LSB order.
  3776. ******************************************************************************/
  3777. static void
  3778. e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
  3779. {
  3780. uint32_t ctrl;
  3781. uint32_t mask;
  3782. /* We need to shift "count" number of bits out to the PHY. So, the value
  3783. * in the "data" parameter will be shifted out to the PHY one bit at a
  3784. * time. In order to do this, "data" must be broken down into bits.
  3785. */
  3786. mask = 0x01;
  3787. mask <<= (count - 1);
  3788. ctrl = E1000_READ_REG(hw, CTRL);
  3789. /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
  3790. ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
  3791. while (mask) {
  3792. /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
  3793. * then raising and lowering the Management Data Clock. A "0" is
  3794. * shifted out to the PHY by setting the MDIO bit to "0" and then
  3795. * raising and lowering the clock.
  3796. */
  3797. if (data & mask)
  3798. ctrl |= E1000_CTRL_MDIO;
  3799. else
  3800. ctrl &= ~E1000_CTRL_MDIO;
  3801. E1000_WRITE_REG(hw, CTRL, ctrl);
  3802. E1000_WRITE_FLUSH(hw);
  3803. udelay(2);
  3804. e1000_raise_mdi_clk(hw, &ctrl);
  3805. e1000_lower_mdi_clk(hw, &ctrl);
  3806. mask = mask >> 1;
  3807. }
  3808. }
  3809. /******************************************************************************
  3810. * Shifts data bits in from the PHY
  3811. *
  3812. * hw - Struct containing variables accessed by shared code
  3813. *
  3814. * Bits are shifted in in MSB to LSB order.
  3815. ******************************************************************************/
  3816. static uint16_t
  3817. e1000_shift_in_mdi_bits(struct e1000_hw *hw)
  3818. {
  3819. uint32_t ctrl;
  3820. uint16_t data = 0;
  3821. uint8_t i;
  3822. /* In order to read a register from the PHY, we need to shift in a total
  3823. * of 18 bits from the PHY. The first two bit (turnaround) times are used
  3824. * to avoid contention on the MDIO pin when a read operation is performed.
  3825. * These two bits are ignored by us and thrown away. Bits are "shifted in"
  3826. * by raising the input to the Management Data Clock (setting the MDC bit),
  3827. * and then reading the value of the MDIO bit.
  3828. */
  3829. ctrl = E1000_READ_REG(hw, CTRL);
  3830. /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
  3831. ctrl &= ~E1000_CTRL_MDIO_DIR;
  3832. ctrl &= ~E1000_CTRL_MDIO;
  3833. E1000_WRITE_REG(hw, CTRL, ctrl);
  3834. E1000_WRITE_FLUSH(hw);
  3835. /* Raise and Lower the clock before reading in the data. This accounts for
  3836. * the turnaround bits. The first clock occurred when we clocked out the
  3837. * last bit of the Register Address.
  3838. */
  3839. e1000_raise_mdi_clk(hw, &ctrl);
  3840. e1000_lower_mdi_clk(hw, &ctrl);
  3841. for (data = 0, i = 0; i < 16; i++) {
  3842. data = data << 1;
  3843. e1000_raise_mdi_clk(hw, &ctrl);
  3844. ctrl = E1000_READ_REG(hw, CTRL);
  3845. /* Check to see if we shifted in a "1". */
  3846. if (ctrl & E1000_CTRL_MDIO)
  3847. data |= 1;
  3848. e1000_lower_mdi_clk(hw, &ctrl);
  3849. }
  3850. e1000_raise_mdi_clk(hw, &ctrl);
  3851. e1000_lower_mdi_clk(hw, &ctrl);
  3852. return data;
  3853. }
  3854. /*****************************************************************************
  3855. * Reads the value from a PHY register
  3856. *
  3857. * hw - Struct containing variables accessed by shared code
  3858. * reg_addr - address of the PHY register to read
  3859. ******************************************************************************/
  3860. static int
  3861. e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
  3862. {
  3863. uint32_t i;
  3864. uint32_t mdic = 0;
  3865. const uint32_t phy_addr = 1;
  3866. if (reg_addr > MAX_PHY_REG_ADDRESS) {
  3867. DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
  3868. return -E1000_ERR_PARAM;
  3869. }
  3870. if (hw->mac_type > e1000_82543) {
  3871. /* Set up Op-code, Phy Address, and register address in the MDI
  3872. * Control register. The MAC will take care of interfacing with the
  3873. * PHY to retrieve the desired data.
  3874. */
  3875. mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
  3876. (phy_addr << E1000_MDIC_PHY_SHIFT) |
  3877. (E1000_MDIC_OP_READ));
  3878. E1000_WRITE_REG(hw, MDIC, mdic);
  3879. /* Poll the ready bit to see if the MDI read completed */
  3880. for (i = 0; i < 64; i++) {
  3881. udelay(10);
  3882. mdic = E1000_READ_REG(hw, MDIC);
  3883. if (mdic & E1000_MDIC_READY)
  3884. break;
  3885. }
  3886. if (!(mdic & E1000_MDIC_READY)) {
  3887. DEBUGOUT("MDI Read did not complete\n");
  3888. return -E1000_ERR_PHY;
  3889. }
  3890. if (mdic & E1000_MDIC_ERROR) {
  3891. DEBUGOUT("MDI Error\n");
  3892. return -E1000_ERR_PHY;
  3893. }
  3894. *phy_data = (uint16_t) mdic;
  3895. } else {
  3896. /* We must first send a preamble through the MDIO pin to signal the
  3897. * beginning of an MII instruction. This is done by sending 32
  3898. * consecutive "1" bits.
  3899. */
  3900. e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
  3901. /* Now combine the next few fields that are required for a read
  3902. * operation. We use this method instead of calling the
  3903. * e1000_shift_out_mdi_bits routine five different times. The format of
  3904. * a MII read instruction consists of a shift out of 14 bits and is
  3905. * defined as follows:
  3906. * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
  3907. * followed by a shift in of 18 bits. This first two bits shifted in
  3908. * are TurnAround bits used to avoid contention on the MDIO pin when a
  3909. * READ operation is performed. These two bits are thrown away
  3910. * followed by a shift in of 16 bits which contains the desired data.
  3911. */
  3912. mdic = ((reg_addr) | (phy_addr << 5) |
  3913. (PHY_OP_READ << 10) | (PHY_SOF << 12));
  3914. e1000_shift_out_mdi_bits(hw, mdic, 14);
  3915. /* Now that we've shifted out the read command to the MII, we need to
  3916. * "shift in" the 16-bit value (18 total bits) of the requested PHY
  3917. * register address.
  3918. */
  3919. *phy_data = e1000_shift_in_mdi_bits(hw);
  3920. }
  3921. return 0;
  3922. }
  3923. /******************************************************************************
  3924. * Writes a value to a PHY register
  3925. *
  3926. * hw - Struct containing variables accessed by shared code
  3927. * reg_addr - address of the PHY register to write
  3928. * data - data to write to the PHY
  3929. ******************************************************************************/
  3930. static int
  3931. e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
  3932. {
  3933. uint32_t i;
  3934. uint32_t mdic = 0;
  3935. const uint32_t phy_addr = 1;
  3936. if (reg_addr > MAX_PHY_REG_ADDRESS) {
  3937. DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
  3938. return -E1000_ERR_PARAM;
  3939. }
  3940. if (hw->mac_type > e1000_82543) {
  3941. /* Set up Op-code, Phy Address, register address, and data intended
  3942. * for the PHY register in the MDI Control register. The MAC will take
  3943. * care of interfacing with the PHY to send the desired data.
  3944. */
  3945. mdic = (((uint32_t) phy_data) |
  3946. (reg_addr << E1000_MDIC_REG_SHIFT) |
  3947. (phy_addr << E1000_MDIC_PHY_SHIFT) |
  3948. (E1000_MDIC_OP_WRITE));
  3949. E1000_WRITE_REG(hw, MDIC, mdic);
  3950. /* Poll the ready bit to see if the MDI read completed */
  3951. for (i = 0; i < 64; i++) {
  3952. udelay(10);
  3953. mdic = E1000_READ_REG(hw, MDIC);
  3954. if (mdic & E1000_MDIC_READY)
  3955. break;
  3956. }
  3957. if (!(mdic & E1000_MDIC_READY)) {
  3958. DEBUGOUT("MDI Write did not complete\n");
  3959. return -E1000_ERR_PHY;
  3960. }
  3961. } else {
  3962. /* We'll need to use the SW defined pins to shift the write command
  3963. * out to the PHY. We first send a preamble to the PHY to signal the
  3964. * beginning of the MII instruction. This is done by sending 32
  3965. * consecutive "1" bits.
  3966. */
  3967. e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
  3968. /* Now combine the remaining required fields that will indicate a
  3969. * write operation. We use this method instead of calling the
  3970. * e1000_shift_out_mdi_bits routine for each field in the command. The
  3971. * format of a MII write instruction is as follows:
  3972. * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
  3973. */
  3974. mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
  3975. (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
  3976. mdic <<= 16;
  3977. mdic |= (uint32_t) phy_data;
  3978. e1000_shift_out_mdi_bits(hw, mdic, 32);
  3979. }
  3980. return 0;
  3981. }
  3982. /******************************************************************************
  3983. * Checks if PHY reset is blocked due to SOL/IDER session, for example.
  3984. * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
  3985. * the caller to figure out how to deal with it.
  3986. *
  3987. * hw - Struct containing variables accessed by shared code
  3988. *
  3989. * returns: - E1000_BLK_PHY_RESET
  3990. * E1000_SUCCESS
  3991. *
  3992. *****************************************************************************/
  3993. int32_t
  3994. e1000_check_phy_reset_block(struct e1000_hw *hw)
  3995. {
  3996. uint32_t manc = 0;
  3997. uint32_t fwsm = 0;
  3998. if (hw->mac_type == e1000_ich8lan) {
  3999. fwsm = E1000_READ_REG(hw, FWSM);
  4000. return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
  4001. : E1000_BLK_PHY_RESET;
  4002. }
  4003. if (hw->mac_type > e1000_82547_rev_2)
  4004. manc = E1000_READ_REG(hw, MANC);
  4005. return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
  4006. E1000_BLK_PHY_RESET : E1000_SUCCESS;
  4007. }
  4008. /***************************************************************************
  4009. * Checks if the PHY configuration is done
  4010. *
  4011. * hw: Struct containing variables accessed by shared code
  4012. *
  4013. * returns: - E1000_ERR_RESET if fail to reset MAC
  4014. * E1000_SUCCESS at any other case.
  4015. *
  4016. ***************************************************************************/
  4017. static int32_t
  4018. e1000_get_phy_cfg_done(struct e1000_hw *hw)
  4019. {
  4020. int32_t timeout = PHY_CFG_TIMEOUT;
  4021. uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
  4022. DEBUGFUNC();
  4023. switch (hw->mac_type) {
  4024. default:
  4025. mdelay(10);
  4026. break;
  4027. case e1000_80003es2lan:
  4028. /* Separate *_CFG_DONE_* bit for each port */
  4029. if (e1000_is_second_port(hw))
  4030. cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
  4031. /* Fall Through */
  4032. case e1000_82571:
  4033. case e1000_82572:
  4034. case e1000_igb:
  4035. while (timeout) {
  4036. if (hw->mac_type == e1000_igb) {
  4037. if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask)
  4038. break;
  4039. } else {
  4040. if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
  4041. break;
  4042. }
  4043. mdelay(1);
  4044. timeout--;
  4045. }
  4046. if (!timeout) {
  4047. DEBUGOUT("MNG configuration cycle has not "
  4048. "completed.\n");
  4049. return -E1000_ERR_RESET;
  4050. }
  4051. break;
  4052. }
  4053. return E1000_SUCCESS;
  4054. }
  4055. /******************************************************************************
  4056. * Returns the PHY to the power-on reset state
  4057. *
  4058. * hw - Struct containing variables accessed by shared code
  4059. ******************************************************************************/
  4060. int32_t
  4061. e1000_phy_hw_reset(struct e1000_hw *hw)
  4062. {
  4063. uint16_t swfw = E1000_SWFW_PHY0_SM;
  4064. uint32_t ctrl, ctrl_ext;
  4065. uint32_t led_ctrl;
  4066. int32_t ret_val;
  4067. DEBUGFUNC();
  4068. /* In the case of the phy reset being blocked, it's not an error, we
  4069. * simply return success without performing the reset. */
  4070. ret_val = e1000_check_phy_reset_block(hw);
  4071. if (ret_val)
  4072. return E1000_SUCCESS;
  4073. DEBUGOUT("Resetting Phy...\n");
  4074. if (hw->mac_type > e1000_82543) {
  4075. if (e1000_is_second_port(hw))
  4076. swfw = E1000_SWFW_PHY1_SM;
  4077. if (e1000_swfw_sync_acquire(hw, swfw)) {
  4078. DEBUGOUT("Unable to acquire swfw sync\n");
  4079. return -E1000_ERR_SWFW_SYNC;
  4080. }
  4081. /* Read the device control register and assert the E1000_CTRL_PHY_RST
  4082. * bit. Then, take it out of reset.
  4083. */
  4084. ctrl = E1000_READ_REG(hw, CTRL);
  4085. E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
  4086. E1000_WRITE_FLUSH(hw);
  4087. if (hw->mac_type < e1000_82571)
  4088. udelay(10);
  4089. else
  4090. udelay(100);
  4091. E1000_WRITE_REG(hw, CTRL, ctrl);
  4092. E1000_WRITE_FLUSH(hw);
  4093. if (hw->mac_type >= e1000_82571)
  4094. mdelay(10);
  4095. } else {
  4096. /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
  4097. * bit to put the PHY into reset. Then, take it out of reset.
  4098. */
  4099. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  4100. ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
  4101. ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
  4102. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  4103. E1000_WRITE_FLUSH(hw);
  4104. mdelay(10);
  4105. ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
  4106. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  4107. E1000_WRITE_FLUSH(hw);
  4108. }
  4109. udelay(150);
  4110. if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
  4111. /* Configure activity LED after PHY reset */
  4112. led_ctrl = E1000_READ_REG(hw, LEDCTL);
  4113. led_ctrl &= IGP_ACTIVITY_LED_MASK;
  4114. led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
  4115. E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
  4116. }
  4117. e1000_swfw_sync_release(hw, swfw);
  4118. /* Wait for FW to finish PHY configuration. */
  4119. ret_val = e1000_get_phy_cfg_done(hw);
  4120. if (ret_val != E1000_SUCCESS)
  4121. return ret_val;
  4122. return ret_val;
  4123. }
  4124. /******************************************************************************
  4125. * IGP phy init script - initializes the GbE PHY
  4126. *
  4127. * hw - Struct containing variables accessed by shared code
  4128. *****************************************************************************/
  4129. static void
  4130. e1000_phy_init_script(struct e1000_hw *hw)
  4131. {
  4132. uint32_t ret_val;
  4133. uint16_t phy_saved_data;
  4134. DEBUGFUNC();
  4135. if (hw->phy_init_script) {
  4136. mdelay(20);
  4137. /* Save off the current value of register 0x2F5B to be
  4138. * restored at the end of this routine. */
  4139. ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
  4140. /* Disabled the PHY transmitter */
  4141. e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
  4142. mdelay(20);
  4143. e1000_write_phy_reg(hw, 0x0000, 0x0140);
  4144. mdelay(5);
  4145. switch (hw->mac_type) {
  4146. case e1000_82541:
  4147. case e1000_82547:
  4148. e1000_write_phy_reg(hw, 0x1F95, 0x0001);
  4149. e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
  4150. e1000_write_phy_reg(hw, 0x1F79, 0x0018);
  4151. e1000_write_phy_reg(hw, 0x1F30, 0x1600);
  4152. e1000_write_phy_reg(hw, 0x1F31, 0x0014);
  4153. e1000_write_phy_reg(hw, 0x1F32, 0x161C);
  4154. e1000_write_phy_reg(hw, 0x1F94, 0x0003);
  4155. e1000_write_phy_reg(hw, 0x1F96, 0x003F);
  4156. e1000_write_phy_reg(hw, 0x2010, 0x0008);
  4157. break;
  4158. case e1000_82541_rev_2:
  4159. case e1000_82547_rev_2:
  4160. e1000_write_phy_reg(hw, 0x1F73, 0x0099);
  4161. break;
  4162. default:
  4163. break;
  4164. }
  4165. e1000_write_phy_reg(hw, 0x0000, 0x3300);
  4166. mdelay(20);
  4167. /* Now enable the transmitter */
  4168. if (!ret_val)
  4169. e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
  4170. if (hw->mac_type == e1000_82547) {
  4171. uint16_t fused, fine, coarse;
  4172. /* Move to analog registers page */
  4173. e1000_read_phy_reg(hw,
  4174. IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
  4175. if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
  4176. e1000_read_phy_reg(hw,
  4177. IGP01E1000_ANALOG_FUSE_STATUS, &fused);
  4178. fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
  4179. coarse = fused
  4180. & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
  4181. if (coarse >
  4182. IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
  4183. coarse -=
  4184. IGP01E1000_ANALOG_FUSE_COARSE_10;
  4185. fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
  4186. } else if (coarse
  4187. == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
  4188. fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
  4189. fused = (fused
  4190. & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
  4191. (fine
  4192. & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
  4193. (coarse
  4194. & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
  4195. e1000_write_phy_reg(hw,
  4196. IGP01E1000_ANALOG_FUSE_CONTROL, fused);
  4197. e1000_write_phy_reg(hw,
  4198. IGP01E1000_ANALOG_FUSE_BYPASS,
  4199. IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
  4200. }
  4201. }
  4202. }
  4203. }
  4204. /******************************************************************************
  4205. * Resets the PHY
  4206. *
  4207. * hw - Struct containing variables accessed by shared code
  4208. *
  4209. * Sets bit 15 of the MII Control register
  4210. ******************************************************************************/
  4211. int32_t
  4212. e1000_phy_reset(struct e1000_hw *hw)
  4213. {
  4214. int32_t ret_val;
  4215. uint16_t phy_data;
  4216. DEBUGFUNC();
  4217. /* In the case of the phy reset being blocked, it's not an error, we
  4218. * simply return success without performing the reset. */
  4219. ret_val = e1000_check_phy_reset_block(hw);
  4220. if (ret_val)
  4221. return E1000_SUCCESS;
  4222. switch (hw->phy_type) {
  4223. case e1000_phy_igp:
  4224. case e1000_phy_igp_2:
  4225. case e1000_phy_igp_3:
  4226. case e1000_phy_ife:
  4227. case e1000_phy_igb:
  4228. ret_val = e1000_phy_hw_reset(hw);
  4229. if (ret_val)
  4230. return ret_val;
  4231. break;
  4232. default:
  4233. ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
  4234. if (ret_val)
  4235. return ret_val;
  4236. phy_data |= MII_CR_RESET;
  4237. ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
  4238. if (ret_val)
  4239. return ret_val;
  4240. udelay(1);
  4241. break;
  4242. }
  4243. if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
  4244. e1000_phy_init_script(hw);
  4245. return E1000_SUCCESS;
  4246. }
  4247. static int e1000_set_phy_type (struct e1000_hw *hw)
  4248. {
  4249. DEBUGFUNC ();
  4250. if (hw->mac_type == e1000_undefined)
  4251. return -E1000_ERR_PHY_TYPE;
  4252. switch (hw->phy_id) {
  4253. case M88E1000_E_PHY_ID:
  4254. case M88E1000_I_PHY_ID:
  4255. case M88E1011_I_PHY_ID:
  4256. case M88E1111_I_PHY_ID:
  4257. hw->phy_type = e1000_phy_m88;
  4258. break;
  4259. case IGP01E1000_I_PHY_ID:
  4260. if (hw->mac_type == e1000_82541 ||
  4261. hw->mac_type == e1000_82541_rev_2 ||
  4262. hw->mac_type == e1000_82547 ||
  4263. hw->mac_type == e1000_82547_rev_2) {
  4264. hw->phy_type = e1000_phy_igp;
  4265. break;
  4266. }
  4267. case IGP03E1000_E_PHY_ID:
  4268. hw->phy_type = e1000_phy_igp_3;
  4269. break;
  4270. case IFE_E_PHY_ID:
  4271. case IFE_PLUS_E_PHY_ID:
  4272. case IFE_C_E_PHY_ID:
  4273. hw->phy_type = e1000_phy_ife;
  4274. break;
  4275. case GG82563_E_PHY_ID:
  4276. if (hw->mac_type == e1000_80003es2lan) {
  4277. hw->phy_type = e1000_phy_gg82563;
  4278. break;
  4279. }
  4280. case BME1000_E_PHY_ID:
  4281. hw->phy_type = e1000_phy_bm;
  4282. break;
  4283. case I210_I_PHY_ID:
  4284. hw->phy_type = e1000_phy_igb;
  4285. break;
  4286. /* Fall Through */
  4287. default:
  4288. /* Should never have loaded on this device */
  4289. hw->phy_type = e1000_phy_undefined;
  4290. return -E1000_ERR_PHY_TYPE;
  4291. }
  4292. return E1000_SUCCESS;
  4293. }
  4294. /******************************************************************************
  4295. * Probes the expected PHY address for known PHY IDs
  4296. *
  4297. * hw - Struct containing variables accessed by shared code
  4298. ******************************************************************************/
  4299. static int32_t
  4300. e1000_detect_gig_phy(struct e1000_hw *hw)
  4301. {
  4302. int32_t phy_init_status, ret_val;
  4303. uint16_t phy_id_high, phy_id_low;
  4304. bool match = false;
  4305. DEBUGFUNC();
  4306. /* The 82571 firmware may still be configuring the PHY. In this
  4307. * case, we cannot access the PHY until the configuration is done. So
  4308. * we explicitly set the PHY values. */
  4309. if (hw->mac_type == e1000_82571 ||
  4310. hw->mac_type == e1000_82572) {
  4311. hw->phy_id = IGP01E1000_I_PHY_ID;
  4312. hw->phy_type = e1000_phy_igp_2;
  4313. return E1000_SUCCESS;
  4314. }
  4315. /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
  4316. * work- around that forces PHY page 0 to be set or the reads fail.
  4317. * The rest of the code in this routine uses e1000_read_phy_reg to
  4318. * read the PHY ID. So for ESB-2 we need to have this set so our
  4319. * reads won't fail. If the attached PHY is not a e1000_phy_gg82563,
  4320. * the routines below will figure this out as well. */
  4321. if (hw->mac_type == e1000_80003es2lan)
  4322. hw->phy_type = e1000_phy_gg82563;
  4323. /* Read the PHY ID Registers to identify which PHY is onboard. */
  4324. ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
  4325. if (ret_val)
  4326. return ret_val;
  4327. hw->phy_id = (uint32_t) (phy_id_high << 16);
  4328. udelay(20);
  4329. ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
  4330. if (ret_val)
  4331. return ret_val;
  4332. hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
  4333. hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
  4334. switch (hw->mac_type) {
  4335. case e1000_82543:
  4336. if (hw->phy_id == M88E1000_E_PHY_ID)
  4337. match = true;
  4338. break;
  4339. case e1000_82544:
  4340. if (hw->phy_id == M88E1000_I_PHY_ID)
  4341. match = true;
  4342. break;
  4343. case e1000_82540:
  4344. case e1000_82545:
  4345. case e1000_82545_rev_3:
  4346. case e1000_82546:
  4347. case e1000_82546_rev_3:
  4348. if (hw->phy_id == M88E1011_I_PHY_ID)
  4349. match = true;
  4350. break;
  4351. case e1000_82541:
  4352. case e1000_82541_rev_2:
  4353. case e1000_82547:
  4354. case e1000_82547_rev_2:
  4355. if(hw->phy_id == IGP01E1000_I_PHY_ID)
  4356. match = true;
  4357. break;
  4358. case e1000_82573:
  4359. if (hw->phy_id == M88E1111_I_PHY_ID)
  4360. match = true;
  4361. break;
  4362. case e1000_82574:
  4363. if (hw->phy_id == BME1000_E_PHY_ID)
  4364. match = true;
  4365. break;
  4366. case e1000_80003es2lan:
  4367. if (hw->phy_id == GG82563_E_PHY_ID)
  4368. match = true;
  4369. break;
  4370. case e1000_ich8lan:
  4371. if (hw->phy_id == IGP03E1000_E_PHY_ID)
  4372. match = true;
  4373. if (hw->phy_id == IFE_E_PHY_ID)
  4374. match = true;
  4375. if (hw->phy_id == IFE_PLUS_E_PHY_ID)
  4376. match = true;
  4377. if (hw->phy_id == IFE_C_E_PHY_ID)
  4378. match = true;
  4379. break;
  4380. case e1000_igb:
  4381. if (hw->phy_id == I210_I_PHY_ID)
  4382. match = true;
  4383. break;
  4384. default:
  4385. DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
  4386. return -E1000_ERR_CONFIG;
  4387. }
  4388. phy_init_status = e1000_set_phy_type(hw);
  4389. if ((match) && (phy_init_status == E1000_SUCCESS)) {
  4390. DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
  4391. return 0;
  4392. }
  4393. DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
  4394. return -E1000_ERR_PHY;
  4395. }
  4396. /*****************************************************************************
  4397. * Set media type and TBI compatibility.
  4398. *
  4399. * hw - Struct containing variables accessed by shared code
  4400. * **************************************************************************/
  4401. void
  4402. e1000_set_media_type(struct e1000_hw *hw)
  4403. {
  4404. uint32_t status;
  4405. DEBUGFUNC();
  4406. if (hw->mac_type != e1000_82543) {
  4407. /* tbi_compatibility is only valid on 82543 */
  4408. hw->tbi_compatibility_en = false;
  4409. }
  4410. switch (hw->device_id) {
  4411. case E1000_DEV_ID_82545GM_SERDES:
  4412. case E1000_DEV_ID_82546GB_SERDES:
  4413. case E1000_DEV_ID_82571EB_SERDES:
  4414. case E1000_DEV_ID_82571EB_SERDES_DUAL:
  4415. case E1000_DEV_ID_82571EB_SERDES_QUAD:
  4416. case E1000_DEV_ID_82572EI_SERDES:
  4417. case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
  4418. hw->media_type = e1000_media_type_internal_serdes;
  4419. break;
  4420. default:
  4421. switch (hw->mac_type) {
  4422. case e1000_82542_rev2_0:
  4423. case e1000_82542_rev2_1:
  4424. hw->media_type = e1000_media_type_fiber;
  4425. break;
  4426. case e1000_ich8lan:
  4427. case e1000_82573:
  4428. case e1000_82574:
  4429. case e1000_igb:
  4430. /* The STATUS_TBIMODE bit is reserved or reused
  4431. * for the this device.
  4432. */
  4433. hw->media_type = e1000_media_type_copper;
  4434. break;
  4435. default:
  4436. status = E1000_READ_REG(hw, STATUS);
  4437. if (status & E1000_STATUS_TBIMODE) {
  4438. hw->media_type = e1000_media_type_fiber;
  4439. /* tbi_compatibility not valid on fiber */
  4440. hw->tbi_compatibility_en = false;
  4441. } else {
  4442. hw->media_type = e1000_media_type_copper;
  4443. }
  4444. break;
  4445. }
  4446. }
  4447. }
  4448. /**
  4449. * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
  4450. *
  4451. * e1000_sw_init initializes the Adapter private data structure.
  4452. * Fields are initialized based on PCI device information and
  4453. * OS network device settings (MTU size).
  4454. **/
  4455. static int
  4456. e1000_sw_init(struct e1000_hw *hw)
  4457. {
  4458. int result;
  4459. /* PCI config space info */
  4460. #ifdef CONFIG_DM_ETH
  4461. dm_pci_read_config16(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
  4462. dm_pci_read_config16(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
  4463. dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
  4464. &hw->subsystem_vendor_id);
  4465. dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
  4466. dm_pci_read_config8(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
  4467. dm_pci_read_config16(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
  4468. #else
  4469. pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
  4470. pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
  4471. pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
  4472. &hw->subsystem_vendor_id);
  4473. pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
  4474. pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
  4475. pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
  4476. #endif
  4477. /* identify the MAC */
  4478. result = e1000_set_mac_type(hw);
  4479. if (result) {
  4480. E1000_ERR(hw, "Unknown MAC Type\n");
  4481. return result;
  4482. }
  4483. switch (hw->mac_type) {
  4484. default:
  4485. break;
  4486. case e1000_82541:
  4487. case e1000_82547:
  4488. case e1000_82541_rev_2:
  4489. case e1000_82547_rev_2:
  4490. hw->phy_init_script = 1;
  4491. break;
  4492. }
  4493. /* flow control settings */
  4494. hw->fc_high_water = E1000_FC_HIGH_THRESH;
  4495. hw->fc_low_water = E1000_FC_LOW_THRESH;
  4496. hw->fc_pause_time = E1000_FC_PAUSE_TIME;
  4497. hw->fc_send_xon = 1;
  4498. /* Media type - copper or fiber */
  4499. hw->tbi_compatibility_en = true;
  4500. e1000_set_media_type(hw);
  4501. if (hw->mac_type >= e1000_82543) {
  4502. uint32_t status = E1000_READ_REG(hw, STATUS);
  4503. if (status & E1000_STATUS_TBIMODE) {
  4504. DEBUGOUT("fiber interface\n");
  4505. hw->media_type = e1000_media_type_fiber;
  4506. } else {
  4507. DEBUGOUT("copper interface\n");
  4508. hw->media_type = e1000_media_type_copper;
  4509. }
  4510. } else {
  4511. hw->media_type = e1000_media_type_fiber;
  4512. }
  4513. hw->wait_autoneg_complete = true;
  4514. if (hw->mac_type < e1000_82543)
  4515. hw->report_tx_early = 0;
  4516. else
  4517. hw->report_tx_early = 1;
  4518. return E1000_SUCCESS;
  4519. }
  4520. void
  4521. fill_rx(struct e1000_hw *hw)
  4522. {
  4523. struct e1000_rx_desc *rd;
  4524. unsigned long flush_start, flush_end;
  4525. rx_last = rx_tail;
  4526. rd = rx_base + rx_tail;
  4527. rx_tail = (rx_tail + 1) % 8;
  4528. memset(rd, 0, 16);
  4529. rd->buffer_addr = cpu_to_le64((unsigned long)packet);
  4530. /*
  4531. * Make sure there are no stale data in WB over this area, which
  4532. * might get written into the memory while the e1000 also writes
  4533. * into the same memory area.
  4534. */
  4535. invalidate_dcache_range((unsigned long)packet,
  4536. (unsigned long)packet + 4096);
  4537. /* Dump the DMA descriptor into RAM. */
  4538. flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
  4539. flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
  4540. flush_dcache_range(flush_start, flush_end);
  4541. E1000_WRITE_REG(hw, RDT, rx_tail);
  4542. }
  4543. /**
  4544. * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
  4545. * @adapter: board private structure
  4546. *
  4547. * Configure the Tx unit of the MAC after a reset.
  4548. **/
  4549. static void
  4550. e1000_configure_tx(struct e1000_hw *hw)
  4551. {
  4552. unsigned long tctl;
  4553. unsigned long tipg, tarc;
  4554. uint32_t ipgr1, ipgr2;
  4555. E1000_WRITE_REG(hw, TDBAL, lower_32_bits((unsigned long)tx_base));
  4556. E1000_WRITE_REG(hw, TDBAH, upper_32_bits((unsigned long)tx_base));
  4557. E1000_WRITE_REG(hw, TDLEN, 128);
  4558. /* Setup the HW Tx Head and Tail descriptor pointers */
  4559. E1000_WRITE_REG(hw, TDH, 0);
  4560. E1000_WRITE_REG(hw, TDT, 0);
  4561. tx_tail = 0;
  4562. /* Set the default values for the Tx Inter Packet Gap timer */
  4563. if (hw->mac_type <= e1000_82547_rev_2 &&
  4564. (hw->media_type == e1000_media_type_fiber ||
  4565. hw->media_type == e1000_media_type_internal_serdes))
  4566. tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
  4567. else
  4568. tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
  4569. /* Set the default values for the Tx Inter Packet Gap timer */
  4570. switch (hw->mac_type) {
  4571. case e1000_82542_rev2_0:
  4572. case e1000_82542_rev2_1:
  4573. tipg = DEFAULT_82542_TIPG_IPGT;
  4574. ipgr1 = DEFAULT_82542_TIPG_IPGR1;
  4575. ipgr2 = DEFAULT_82542_TIPG_IPGR2;
  4576. break;
  4577. case e1000_80003es2lan:
  4578. ipgr1 = DEFAULT_82543_TIPG_IPGR1;
  4579. ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
  4580. break;
  4581. default:
  4582. ipgr1 = DEFAULT_82543_TIPG_IPGR1;
  4583. ipgr2 = DEFAULT_82543_TIPG_IPGR2;
  4584. break;
  4585. }
  4586. tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
  4587. tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
  4588. E1000_WRITE_REG(hw, TIPG, tipg);
  4589. /* Program the Transmit Control Register */
  4590. tctl = E1000_READ_REG(hw, TCTL);
  4591. tctl &= ~E1000_TCTL_CT;
  4592. tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
  4593. (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
  4594. if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
  4595. tarc = E1000_READ_REG(hw, TARC0);
  4596. /* set the speed mode bit, we'll clear it if we're not at
  4597. * gigabit link later */
  4598. /* git bit can be set to 1*/
  4599. } else if (hw->mac_type == e1000_80003es2lan) {
  4600. tarc = E1000_READ_REG(hw, TARC0);
  4601. tarc |= 1;
  4602. E1000_WRITE_REG(hw, TARC0, tarc);
  4603. tarc = E1000_READ_REG(hw, TARC1);
  4604. tarc |= 1;
  4605. E1000_WRITE_REG(hw, TARC1, tarc);
  4606. }
  4607. e1000_config_collision_dist(hw);
  4608. /* Setup Transmit Descriptor Settings for eop descriptor */
  4609. hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
  4610. /* Need to set up RS bit */
  4611. if (hw->mac_type < e1000_82543)
  4612. hw->txd_cmd |= E1000_TXD_CMD_RPS;
  4613. else
  4614. hw->txd_cmd |= E1000_TXD_CMD_RS;
  4615. if (hw->mac_type == e1000_igb) {
  4616. E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10);
  4617. uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL);
  4618. reg_txdctl |= 1 << 25;
  4619. E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
  4620. mdelay(20);
  4621. }
  4622. E1000_WRITE_REG(hw, TCTL, tctl);
  4623. }
  4624. /**
  4625. * e1000_setup_rctl - configure the receive control register
  4626. * @adapter: Board private structure
  4627. **/
  4628. static void
  4629. e1000_setup_rctl(struct e1000_hw *hw)
  4630. {
  4631. uint32_t rctl;
  4632. rctl = E1000_READ_REG(hw, RCTL);
  4633. rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
  4634. rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
  4635. | E1000_RCTL_RDMTS_HALF; /* |
  4636. (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
  4637. if (hw->tbi_compatibility_on == 1)
  4638. rctl |= E1000_RCTL_SBP;
  4639. else
  4640. rctl &= ~E1000_RCTL_SBP;
  4641. rctl &= ~(E1000_RCTL_SZ_4096);
  4642. rctl |= E1000_RCTL_SZ_2048;
  4643. rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
  4644. E1000_WRITE_REG(hw, RCTL, rctl);
  4645. }
  4646. /**
  4647. * e1000_configure_rx - Configure 8254x Receive Unit after Reset
  4648. * @adapter: board private structure
  4649. *
  4650. * Configure the Rx unit of the MAC after a reset.
  4651. **/
  4652. static void
  4653. e1000_configure_rx(struct e1000_hw *hw)
  4654. {
  4655. unsigned long rctl, ctrl_ext;
  4656. rx_tail = 0;
  4657. /* make sure receives are disabled while setting up the descriptors */
  4658. rctl = E1000_READ_REG(hw, RCTL);
  4659. E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
  4660. if (hw->mac_type >= e1000_82540) {
  4661. /* Set the interrupt throttling rate. Value is calculated
  4662. * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
  4663. #define MAX_INTS_PER_SEC 8000
  4664. #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
  4665. E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
  4666. }
  4667. if (hw->mac_type >= e1000_82571) {
  4668. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  4669. /* Reset delay timers after every interrupt */
  4670. ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
  4671. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  4672. E1000_WRITE_FLUSH(hw);
  4673. }
  4674. /* Setup the Base and Length of the Rx Descriptor Ring */
  4675. E1000_WRITE_REG(hw, RDBAL, lower_32_bits((unsigned long)rx_base));
  4676. E1000_WRITE_REG(hw, RDBAH, upper_32_bits((unsigned long)rx_base));
  4677. E1000_WRITE_REG(hw, RDLEN, 128);
  4678. /* Setup the HW Rx Head and Tail Descriptor Pointers */
  4679. E1000_WRITE_REG(hw, RDH, 0);
  4680. E1000_WRITE_REG(hw, RDT, 0);
  4681. /* Enable Receives */
  4682. if (hw->mac_type == e1000_igb) {
  4683. uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL);
  4684. reg_rxdctl |= 1 << 25;
  4685. E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl);
  4686. mdelay(20);
  4687. }
  4688. E1000_WRITE_REG(hw, RCTL, rctl);
  4689. fill_rx(hw);
  4690. }
  4691. /**************************************************************************
  4692. POLL - Wait for a frame
  4693. ***************************************************************************/
  4694. static int
  4695. _e1000_poll(struct e1000_hw *hw)
  4696. {
  4697. struct e1000_rx_desc *rd;
  4698. unsigned long inval_start, inval_end;
  4699. uint32_t len;
  4700. /* return true if there's an ethernet packet ready to read */
  4701. rd = rx_base + rx_last;
  4702. /* Re-load the descriptor from RAM. */
  4703. inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
  4704. inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
  4705. invalidate_dcache_range(inval_start, inval_end);
  4706. if (!(rd->status & E1000_RXD_STAT_DD))
  4707. return 0;
  4708. /* DEBUGOUT("recv: packet len=%d\n", rd->length); */
  4709. /* Packet received, make sure the data are re-loaded from RAM. */
  4710. len = le16_to_cpu(rd->length);
  4711. invalidate_dcache_range((unsigned long)packet,
  4712. (unsigned long)packet +
  4713. roundup(len, ARCH_DMA_MINALIGN));
  4714. return len;
  4715. }
  4716. static int _e1000_transmit(struct e1000_hw *hw, void *txpacket, int length)
  4717. {
  4718. void *nv_packet = (void *)txpacket;
  4719. struct e1000_tx_desc *txp;
  4720. int i = 0;
  4721. unsigned long flush_start, flush_end;
  4722. txp = tx_base + tx_tail;
  4723. tx_tail = (tx_tail + 1) % 8;
  4724. txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
  4725. txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
  4726. txp->upper.data = 0;
  4727. /* Dump the packet into RAM so e1000 can pick them. */
  4728. flush_dcache_range((unsigned long)nv_packet,
  4729. (unsigned long)nv_packet +
  4730. roundup(length, ARCH_DMA_MINALIGN));
  4731. /* Dump the descriptor into RAM as well. */
  4732. flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1);
  4733. flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN);
  4734. flush_dcache_range(flush_start, flush_end);
  4735. E1000_WRITE_REG(hw, TDT, tx_tail);
  4736. E1000_WRITE_FLUSH(hw);
  4737. while (1) {
  4738. invalidate_dcache_range(flush_start, flush_end);
  4739. if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)
  4740. break;
  4741. if (i++ > TOUT_LOOP) {
  4742. DEBUGOUT("e1000: tx timeout\n");
  4743. return 0;
  4744. }
  4745. udelay(10); /* give the nic a chance to write to the register */
  4746. }
  4747. return 1;
  4748. }
  4749. static void
  4750. _e1000_disable(struct e1000_hw *hw)
  4751. {
  4752. /* Turn off the ethernet interface */
  4753. E1000_WRITE_REG(hw, RCTL, 0);
  4754. E1000_WRITE_REG(hw, TCTL, 0);
  4755. /* Clear the transmit ring */
  4756. E1000_WRITE_REG(hw, TDH, 0);
  4757. E1000_WRITE_REG(hw, TDT, 0);
  4758. /* Clear the receive ring */
  4759. E1000_WRITE_REG(hw, RDH, 0);
  4760. E1000_WRITE_REG(hw, RDT, 0);
  4761. mdelay(10);
  4762. }
  4763. /*reset function*/
  4764. static inline int
  4765. e1000_reset(struct e1000_hw *hw, unsigned char enetaddr[6])
  4766. {
  4767. e1000_reset_hw(hw);
  4768. if (hw->mac_type >= e1000_82544)
  4769. E1000_WRITE_REG(hw, WUC, 0);
  4770. return e1000_init_hw(hw, enetaddr);
  4771. }
  4772. static int
  4773. _e1000_init(struct e1000_hw *hw, unsigned char enetaddr[6])
  4774. {
  4775. int ret_val = 0;
  4776. ret_val = e1000_reset(hw, enetaddr);
  4777. if (ret_val < 0) {
  4778. if ((ret_val == -E1000_ERR_NOLINK) ||
  4779. (ret_val == -E1000_ERR_TIMEOUT)) {
  4780. E1000_ERR(hw, "Valid Link not detected: %d\n", ret_val);
  4781. } else {
  4782. E1000_ERR(hw, "Hardware Initialization Failed\n");
  4783. }
  4784. return ret_val;
  4785. }
  4786. e1000_configure_tx(hw);
  4787. e1000_setup_rctl(hw);
  4788. e1000_configure_rx(hw);
  4789. return 0;
  4790. }
  4791. /******************************************************************************
  4792. * Gets the current PCI bus type of hardware
  4793. *
  4794. * hw - Struct containing variables accessed by shared code
  4795. *****************************************************************************/
  4796. void e1000_get_bus_type(struct e1000_hw *hw)
  4797. {
  4798. uint32_t status;
  4799. switch (hw->mac_type) {
  4800. case e1000_82542_rev2_0:
  4801. case e1000_82542_rev2_1:
  4802. hw->bus_type = e1000_bus_type_pci;
  4803. break;
  4804. case e1000_82571:
  4805. case e1000_82572:
  4806. case e1000_82573:
  4807. case e1000_82574:
  4808. case e1000_80003es2lan:
  4809. case e1000_ich8lan:
  4810. case e1000_igb:
  4811. hw->bus_type = e1000_bus_type_pci_express;
  4812. break;
  4813. default:
  4814. status = E1000_READ_REG(hw, STATUS);
  4815. hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
  4816. e1000_bus_type_pcix : e1000_bus_type_pci;
  4817. break;
  4818. }
  4819. }
  4820. #ifndef CONFIG_DM_ETH
  4821. /* A list of all registered e1000 devices */
  4822. static LIST_HEAD(e1000_hw_list);
  4823. #endif
  4824. #ifdef CONFIG_DM_ETH
  4825. static int e1000_init_one(struct e1000_hw *hw, int cardnum,
  4826. struct udevice *devno, unsigned char enetaddr[6])
  4827. #else
  4828. static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno,
  4829. unsigned char enetaddr[6])
  4830. #endif
  4831. {
  4832. u32 val;
  4833. /* Assign the passed-in values */
  4834. #ifdef CONFIG_DM_ETH
  4835. hw->pdev = devno;
  4836. #else
  4837. hw->pdev = devno;
  4838. #endif
  4839. hw->cardnum = cardnum;
  4840. /* Print a debug message with the IO base address */
  4841. #ifdef CONFIG_DM_ETH
  4842. dm_pci_read_config32(devno, PCI_BASE_ADDRESS_0, &val);
  4843. #else
  4844. pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
  4845. #endif
  4846. E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0);
  4847. /* Try to enable I/O accesses and bus-mastering */
  4848. val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
  4849. #ifdef CONFIG_DM_ETH
  4850. dm_pci_write_config32(devno, PCI_COMMAND, val);
  4851. #else
  4852. pci_write_config_dword(devno, PCI_COMMAND, val);
  4853. #endif
  4854. /* Make sure it worked */
  4855. #ifdef CONFIG_DM_ETH
  4856. dm_pci_read_config32(devno, PCI_COMMAND, &val);
  4857. #else
  4858. pci_read_config_dword(devno, PCI_COMMAND, &val);
  4859. #endif
  4860. if (!(val & PCI_COMMAND_MEMORY)) {
  4861. E1000_ERR(hw, "Can't enable I/O memory\n");
  4862. return -ENOSPC;
  4863. }
  4864. if (!(val & PCI_COMMAND_MASTER)) {
  4865. E1000_ERR(hw, "Can't enable bus-mastering\n");
  4866. return -EPERM;
  4867. }
  4868. /* Are these variables needed? */
  4869. hw->fc = e1000_fc_default;
  4870. hw->original_fc = e1000_fc_default;
  4871. hw->autoneg_failed = 0;
  4872. hw->autoneg = 1;
  4873. hw->get_link_status = true;
  4874. #ifndef CONFIG_E1000_NO_NVM
  4875. hw->eeprom_semaphore_present = true;
  4876. #endif
  4877. #ifdef CONFIG_DM_ETH
  4878. hw->hw_addr = dm_pci_map_bar(devno, PCI_BASE_ADDRESS_0,
  4879. PCI_REGION_MEM);
  4880. #else
  4881. hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
  4882. PCI_REGION_MEM);
  4883. #endif
  4884. hw->mac_type = e1000_undefined;
  4885. /* MAC and Phy settings */
  4886. if (e1000_sw_init(hw) < 0) {
  4887. E1000_ERR(hw, "Software init failed\n");
  4888. return -EIO;
  4889. }
  4890. if (e1000_check_phy_reset_block(hw))
  4891. E1000_ERR(hw, "PHY Reset is blocked!\n");
  4892. /* Basic init was OK, reset the hardware and allow SPI access */
  4893. e1000_reset_hw(hw);
  4894. #ifndef CONFIG_E1000_NO_NVM
  4895. /* Validate the EEPROM and get chipset information */
  4896. if (e1000_init_eeprom_params(hw)) {
  4897. E1000_ERR(hw, "EEPROM is invalid!\n");
  4898. return -EINVAL;
  4899. }
  4900. if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) &&
  4901. e1000_validate_eeprom_checksum(hw))
  4902. return -ENXIO;
  4903. e1000_read_mac_addr(hw, enetaddr);
  4904. #endif
  4905. e1000_get_bus_type(hw);
  4906. #ifndef CONFIG_E1000_NO_NVM
  4907. printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ",
  4908. enetaddr[0], enetaddr[1], enetaddr[2],
  4909. enetaddr[3], enetaddr[4], enetaddr[5]);
  4910. #else
  4911. memset(enetaddr, 0, 6);
  4912. printf("e1000: no NVM\n");
  4913. #endif
  4914. return 0;
  4915. }
  4916. /* Put the name of a device in a string */
  4917. static void e1000_name(char *str, int cardnum)
  4918. {
  4919. sprintf(str, "e1000#%u", cardnum);
  4920. }
  4921. #ifndef CONFIG_DM_ETH
  4922. /**************************************************************************
  4923. TRANSMIT - Transmit a frame
  4924. ***************************************************************************/
  4925. static int e1000_transmit(struct eth_device *nic, void *txpacket, int length)
  4926. {
  4927. struct e1000_hw *hw = nic->priv;
  4928. return _e1000_transmit(hw, txpacket, length);
  4929. }
  4930. /**************************************************************************
  4931. DISABLE - Turn off ethernet interface
  4932. ***************************************************************************/
  4933. static void
  4934. e1000_disable(struct eth_device *nic)
  4935. {
  4936. struct e1000_hw *hw = nic->priv;
  4937. _e1000_disable(hw);
  4938. }
  4939. /**************************************************************************
  4940. INIT - set up ethernet interface(s)
  4941. ***************************************************************************/
  4942. static int
  4943. e1000_init(struct eth_device *nic, bd_t *bis)
  4944. {
  4945. struct e1000_hw *hw = nic->priv;
  4946. return _e1000_init(hw, nic->enetaddr);
  4947. }
  4948. static int
  4949. e1000_poll(struct eth_device *nic)
  4950. {
  4951. struct e1000_hw *hw = nic->priv;
  4952. int len;
  4953. len = _e1000_poll(hw);
  4954. if (len) {
  4955. net_process_received_packet((uchar *)packet, len);
  4956. fill_rx(hw);
  4957. }
  4958. return len ? 1 : 0;
  4959. }
  4960. static int e1000_write_hwaddr(struct eth_device *dev)
  4961. {
  4962. #ifndef CONFIG_E1000_NO_NVM
  4963. unsigned char *mac = dev->enetaddr;
  4964. unsigned char current_mac[6];
  4965. struct e1000_hw *hw = dev->priv;
  4966. uint16_t data[3];
  4967. int ret_val, i;
  4968. DEBUGOUT("%s: mac=%pM\n", __func__, mac);
  4969. memset(current_mac, 0, 6);
  4970. /* Read from EEPROM, not from registers, to make sure
  4971. * the address is persistently configured
  4972. */
  4973. ret_val = e1000_read_mac_addr_from_eeprom(hw, current_mac);
  4974. DEBUGOUT("%s: current mac=%pM\n", __func__, current_mac);
  4975. /* Only write to EEPROM if the given address is different or
  4976. * reading the current address failed
  4977. */
  4978. if (!ret_val && memcmp(current_mac, mac, 6) == 0)
  4979. return 0;
  4980. for (i = 0; i < 3; ++i)
  4981. data[i] = mac[i * 2 + 1] << 8 | mac[i * 2];
  4982. ret_val = e1000_write_eeprom_srwr(hw, 0x0, 3, data);
  4983. if (!ret_val)
  4984. ret_val = e1000_update_eeprom_checksum_i210(hw);
  4985. return ret_val;
  4986. #else
  4987. return 0;
  4988. #endif
  4989. }
  4990. /**************************************************************************
  4991. PROBE - Look for an adapter, this routine's visible to the outside
  4992. You should omit the last argument struct pci_device * for a non-PCI NIC
  4993. ***************************************************************************/
  4994. int
  4995. e1000_initialize(bd_t * bis)
  4996. {
  4997. unsigned int i;
  4998. pci_dev_t devno;
  4999. int ret;
  5000. DEBUGFUNC();
  5001. /* Find and probe all the matching PCI devices */
  5002. for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
  5003. /*
  5004. * These will never get freed due to errors, this allows us to
  5005. * perform SPI EEPROM programming from U-Boot, for example.
  5006. */
  5007. struct eth_device *nic = malloc(sizeof(*nic));
  5008. struct e1000_hw *hw = malloc(sizeof(*hw));
  5009. if (!nic || !hw) {
  5010. printf("e1000#%u: Out of Memory!\n", i);
  5011. free(nic);
  5012. free(hw);
  5013. continue;
  5014. }
  5015. /* Make sure all of the fields are initially zeroed */
  5016. memset(nic, 0, sizeof(*nic));
  5017. memset(hw, 0, sizeof(*hw));
  5018. nic->priv = hw;
  5019. /* Generate a card name */
  5020. e1000_name(nic->name, i);
  5021. hw->name = nic->name;
  5022. ret = e1000_init_one(hw, i, devno, nic->enetaddr);
  5023. if (ret)
  5024. continue;
  5025. list_add_tail(&hw->list_node, &e1000_hw_list);
  5026. hw->nic = nic;
  5027. /* Set up the function pointers and register the device */
  5028. nic->init = e1000_init;
  5029. nic->recv = e1000_poll;
  5030. nic->send = e1000_transmit;
  5031. nic->halt = e1000_disable;
  5032. nic->write_hwaddr = e1000_write_hwaddr;
  5033. eth_register(nic);
  5034. }
  5035. return i;
  5036. }
  5037. struct e1000_hw *e1000_find_card(unsigned int cardnum)
  5038. {
  5039. struct e1000_hw *hw;
  5040. list_for_each_entry(hw, &e1000_hw_list, list_node)
  5041. if (hw->cardnum == cardnum)
  5042. return hw;
  5043. return NULL;
  5044. }
  5045. #endif /* !CONFIG_DM_ETH */
  5046. #ifdef CONFIG_CMD_E1000
  5047. static int do_e1000(cmd_tbl_t *cmdtp, int flag,
  5048. int argc, char * const argv[])
  5049. {
  5050. unsigned char *mac = NULL;
  5051. #ifdef CONFIG_DM_ETH
  5052. struct eth_pdata *plat;
  5053. struct udevice *dev;
  5054. char name[30];
  5055. int ret;
  5056. #endif
  5057. #if !defined(CONFIG_DM_ETH) || defined(CONFIG_E1000_SPI)
  5058. struct e1000_hw *hw;
  5059. #endif
  5060. int cardnum;
  5061. if (argc < 3) {
  5062. cmd_usage(cmdtp);
  5063. return 1;
  5064. }
  5065. /* Make sure we can find the requested e1000 card */
  5066. cardnum = simple_strtoul(argv[1], NULL, 10);
  5067. #ifdef CONFIG_DM_ETH
  5068. e1000_name(name, cardnum);
  5069. ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev);
  5070. if (!ret) {
  5071. plat = dev_get_platdata(dev);
  5072. mac = plat->enetaddr;
  5073. }
  5074. #else
  5075. hw = e1000_find_card(cardnum);
  5076. if (hw)
  5077. mac = hw->nic->enetaddr;
  5078. #endif
  5079. if (!mac) {
  5080. printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
  5081. return 1;
  5082. }
  5083. if (!strcmp(argv[2], "print-mac-address")) {
  5084. printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
  5085. mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
  5086. return 0;
  5087. }
  5088. #ifdef CONFIG_E1000_SPI
  5089. #ifdef CONFIG_DM_ETH
  5090. hw = dev_get_priv(dev);
  5091. #endif
  5092. /* Handle the "SPI" subcommand */
  5093. if (!strcmp(argv[2], "spi"))
  5094. return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
  5095. #endif
  5096. cmd_usage(cmdtp);
  5097. return 1;
  5098. }
  5099. U_BOOT_CMD(
  5100. e1000, 7, 0, do_e1000,
  5101. "Intel e1000 controller management",
  5102. /* */"<card#> print-mac-address\n"
  5103. #ifdef CONFIG_E1000_SPI
  5104. "e1000 <card#> spi show [<offset> [<length>]]\n"
  5105. "e1000 <card#> spi dump <addr> <offset> <length>\n"
  5106. "e1000 <card#> spi program <addr> <offset> <length>\n"
  5107. "e1000 <card#> spi checksum [update]\n"
  5108. #endif
  5109. " - Manage the Intel E1000 PCI device"
  5110. );
  5111. #endif /* not CONFIG_CMD_E1000 */
  5112. #ifdef CONFIG_DM_ETH
  5113. static int e1000_eth_start(struct udevice *dev)
  5114. {
  5115. struct eth_pdata *plat = dev_get_platdata(dev);
  5116. struct e1000_hw *hw = dev_get_priv(dev);
  5117. return _e1000_init(hw, plat->enetaddr);
  5118. }
  5119. static void e1000_eth_stop(struct udevice *dev)
  5120. {
  5121. struct e1000_hw *hw = dev_get_priv(dev);
  5122. _e1000_disable(hw);
  5123. }
  5124. static int e1000_eth_send(struct udevice *dev, void *packet, int length)
  5125. {
  5126. struct e1000_hw *hw = dev_get_priv(dev);
  5127. int ret;
  5128. ret = _e1000_transmit(hw, packet, length);
  5129. return ret ? 0 : -ETIMEDOUT;
  5130. }
  5131. static int e1000_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  5132. {
  5133. struct e1000_hw *hw = dev_get_priv(dev);
  5134. int len;
  5135. len = _e1000_poll(hw);
  5136. if (len)
  5137. *packetp = packet;
  5138. return len ? len : -EAGAIN;
  5139. }
  5140. static int e1000_free_pkt(struct udevice *dev, uchar *packet, int length)
  5141. {
  5142. struct e1000_hw *hw = dev_get_priv(dev);
  5143. fill_rx(hw);
  5144. return 0;
  5145. }
  5146. static int e1000_eth_probe(struct udevice *dev)
  5147. {
  5148. struct eth_pdata *plat = dev_get_platdata(dev);
  5149. struct e1000_hw *hw = dev_get_priv(dev);
  5150. int ret;
  5151. hw->name = dev->name;
  5152. ret = e1000_init_one(hw, trailing_strtol(dev->name),
  5153. dev, plat->enetaddr);
  5154. if (ret < 0) {
  5155. printf(pr_fmt("failed to initialize card: %d\n"), ret);
  5156. return ret;
  5157. }
  5158. return 0;
  5159. }
  5160. static int e1000_eth_bind(struct udevice *dev)
  5161. {
  5162. char name[20];
  5163. /*
  5164. * A simple way to number the devices. When device tree is used this
  5165. * is unnecessary, but when the device is just discovered on the PCI
  5166. * bus we need a name. We could instead have the uclass figure out
  5167. * which devices are different and number them.
  5168. */
  5169. e1000_name(name, num_cards++);
  5170. return device_set_name(dev, name);
  5171. }
  5172. static const struct eth_ops e1000_eth_ops = {
  5173. .start = e1000_eth_start,
  5174. .send = e1000_eth_send,
  5175. .recv = e1000_eth_recv,
  5176. .stop = e1000_eth_stop,
  5177. .free_pkt = e1000_free_pkt,
  5178. };
  5179. static const struct udevice_id e1000_eth_ids[] = {
  5180. { .compatible = "intel,e1000" },
  5181. { }
  5182. };
  5183. U_BOOT_DRIVER(eth_e1000) = {
  5184. .name = "eth_e1000",
  5185. .id = UCLASS_ETH,
  5186. .of_match = e1000_eth_ids,
  5187. .bind = e1000_eth_bind,
  5188. .probe = e1000_eth_probe,
  5189. .ops = &e1000_eth_ops,
  5190. .priv_auto_alloc_size = sizeof(struct e1000_hw),
  5191. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  5192. };
  5193. U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported);
  5194. #endif