cache-cp15.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <asm/system.h>
  9. #include <asm/cache.h>
  10. #include <linux/compiler.h>
  11. #include <asm/armv7_mpu.h>
  12. #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
  13. DECLARE_GLOBAL_DATA_PTR;
  14. #ifdef CONFIG_SYS_ARM_MMU
  15. __weak void arm_init_before_mmu(void)
  16. {
  17. }
  18. __weak void arm_init_domains(void)
  19. {
  20. }
  21. void set_section_dcache(int section, enum dcache_option option)
  22. {
  23. #ifdef CONFIG_ARMV7_LPAE
  24. u64 *page_table = (u64 *)gd->arch.tlb_addr;
  25. /* Need to set the access flag to not fault */
  26. u64 value = TTB_SECT_AP | TTB_SECT_AF;
  27. #else
  28. u32 *page_table = (u32 *)gd->arch.tlb_addr;
  29. u32 value = TTB_SECT_AP;
  30. #endif
  31. /* Add the page offset */
  32. value |= ((u32)section << MMU_SECTION_SHIFT);
  33. /* Add caching bits */
  34. value |= option;
  35. /* Set PTE */
  36. page_table[section] = value;
  37. }
  38. __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
  39. {
  40. debug("%s: Warning: not implemented\n", __func__);
  41. }
  42. void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
  43. enum dcache_option option)
  44. {
  45. #ifdef CONFIG_ARMV7_LPAE
  46. u64 *page_table = (u64 *)gd->arch.tlb_addr;
  47. #else
  48. u32 *page_table = (u32 *)gd->arch.tlb_addr;
  49. #endif
  50. unsigned long startpt, stoppt;
  51. unsigned long upto, end;
  52. /* div by 2 before start + size to avoid phys_addr_t overflow */
  53. end = ALIGN((start / 2) + (size / 2), MMU_SECTION_SIZE / 2)
  54. >> (MMU_SECTION_SHIFT - 1);
  55. start = start >> MMU_SECTION_SHIFT;
  56. #ifdef CONFIG_ARMV7_LPAE
  57. debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
  58. option);
  59. #else
  60. debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
  61. option);
  62. #endif
  63. for (upto = start; upto < end; upto++)
  64. set_section_dcache(upto, option);
  65. /*
  66. * Make sure range is cache line aligned
  67. * Only CPU maintains page tables, hence it is safe to always
  68. * flush complete cache lines...
  69. */
  70. startpt = (unsigned long)&page_table[start];
  71. startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
  72. stoppt = (unsigned long)&page_table[end];
  73. stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE);
  74. mmu_page_table_flush(startpt, stoppt);
  75. }
  76. __weak void dram_bank_mmu_setup(int bank)
  77. {
  78. bd_t *bd = gd->bd;
  79. int i;
  80. /* bd->bi_dram is available only after relocation */
  81. if ((gd->flags & GD_FLG_RELOC) == 0)
  82. return;
  83. debug("%s: bank: %d\n", __func__, bank);
  84. for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
  85. i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
  86. (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
  87. i++)
  88. set_section_dcache(i, DCACHE_DEFAULT_OPTION);
  89. }
  90. /* to activate the MMU we need to set up virtual memory: use 1M areas */
  91. static inline void mmu_setup(void)
  92. {
  93. int i;
  94. u32 reg;
  95. arm_init_before_mmu();
  96. /* Set up an identity-mapping for all 4GB, rw for everyone */
  97. for (i = 0; i < ((4096ULL * 1024 * 1024) >> MMU_SECTION_SHIFT); i++)
  98. set_section_dcache(i, DCACHE_OFF);
  99. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  100. dram_bank_mmu_setup(i);
  101. }
  102. #if defined(CONFIG_ARMV7_LPAE) && __LINUX_ARM_ARCH__ != 4
  103. /* Set up 4 PTE entries pointing to our 4 1GB page tables */
  104. for (i = 0; i < 4; i++) {
  105. u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4));
  106. u64 tpt = gd->arch.tlb_addr + (4096 * i);
  107. page_table[i] = tpt | TTB_PAGETABLE;
  108. }
  109. reg = TTBCR_EAE;
  110. #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
  111. reg |= TTBCR_ORGN0_WT | TTBCR_IRGN0_WT;
  112. #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
  113. reg |= TTBCR_ORGN0_WBWA | TTBCR_IRGN0_WBWA;
  114. #else
  115. reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA;
  116. #endif
  117. if (is_hyp()) {
  118. /* Set HTCR to enable LPAE */
  119. asm volatile("mcr p15, 4, %0, c2, c0, 2"
  120. : : "r" (reg) : "memory");
  121. /* Set HTTBR0 */
  122. asm volatile("mcrr p15, 4, %0, %1, c2"
  123. :
  124. : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
  125. : "memory");
  126. /* Set HMAIR */
  127. asm volatile("mcr p15, 4, %0, c10, c2, 0"
  128. : : "r" (MEMORY_ATTRIBUTES) : "memory");
  129. } else {
  130. /* Set TTBCR to enable LPAE */
  131. asm volatile("mcr p15, 0, %0, c2, c0, 2"
  132. : : "r" (reg) : "memory");
  133. /* Set 64-bit TTBR0 */
  134. asm volatile("mcrr p15, 0, %0, %1, c2"
  135. :
  136. : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
  137. : "memory");
  138. /* Set MAIR */
  139. asm volatile("mcr p15, 0, %0, c10, c2, 0"
  140. : : "r" (MEMORY_ATTRIBUTES) : "memory");
  141. }
  142. #elif defined(CONFIG_CPU_V7A)
  143. if (is_hyp()) {
  144. /* Set HTCR to disable LPAE */
  145. asm volatile("mcr p15, 4, %0, c2, c0, 2"
  146. : : "r" (0) : "memory");
  147. } else {
  148. /* Set TTBCR to disable LPAE */
  149. asm volatile("mcr p15, 0, %0, c2, c0, 2"
  150. : : "r" (0) : "memory");
  151. }
  152. /* Set TTBR0 */
  153. reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
  154. #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
  155. reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT;
  156. #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
  157. reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA;
  158. #else
  159. reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB;
  160. #endif
  161. asm volatile("mcr p15, 0, %0, c2, c0, 0"
  162. : : "r" (reg) : "memory");
  163. #else
  164. /* Copy the page table address to cp15 */
  165. asm volatile("mcr p15, 0, %0, c2, c0, 0"
  166. : : "r" (gd->arch.tlb_addr) : "memory");
  167. #endif
  168. /* Set the access control to all-supervisor */
  169. asm volatile("mcr p15, 0, %0, c3, c0, 0"
  170. : : "r" (~0));
  171. arm_init_domains();
  172. /* and enable the mmu */
  173. reg = get_cr(); /* get control reg. */
  174. set_cr(reg | CR_M);
  175. }
  176. static int mmu_enabled(void)
  177. {
  178. return get_cr() & CR_M;
  179. }
  180. #endif /* CONFIG_SYS_ARM_MMU */
  181. /* cache_bit must be either CR_I or CR_C */
  182. static void cache_enable(uint32_t cache_bit)
  183. {
  184. uint32_t reg;
  185. /* The data cache is not active unless the mmu/mpu is enabled too */
  186. #ifdef CONFIG_SYS_ARM_MMU
  187. if ((cache_bit == CR_C) && !mmu_enabled())
  188. mmu_setup();
  189. #elif defined(CONFIG_SYS_ARM_MPU)
  190. if ((cache_bit == CR_C) && !mpu_enabled()) {
  191. printf("Consider enabling MPU before enabling caches\n");
  192. return;
  193. }
  194. #endif
  195. reg = get_cr(); /* get control reg. */
  196. set_cr(reg | cache_bit);
  197. }
  198. /* cache_bit must be either CR_I or CR_C */
  199. static void cache_disable(uint32_t cache_bit)
  200. {
  201. uint32_t reg;
  202. reg = get_cr();
  203. if (cache_bit == CR_C) {
  204. /* if cache isn;t enabled no need to disable */
  205. if ((reg & CR_C) != CR_C)
  206. return;
  207. #ifdef CONFIG_SYS_ARM_MMU
  208. /* if disabling data cache, disable mmu too */
  209. cache_bit |= CR_M;
  210. #endif
  211. }
  212. reg = get_cr();
  213. #ifdef CONFIG_SYS_ARM_MMU
  214. if (cache_bit == (CR_C | CR_M))
  215. #elif defined(CONFIG_SYS_ARM_MPU)
  216. if (cache_bit == CR_C)
  217. #endif
  218. flush_dcache_all();
  219. set_cr(reg & ~cache_bit);
  220. }
  221. #endif
  222. #if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  223. void icache_enable(void)
  224. {
  225. return;
  226. }
  227. void icache_disable(void)
  228. {
  229. return;
  230. }
  231. int icache_status(void)
  232. {
  233. return 0; /* always off */
  234. }
  235. #else
  236. void icache_enable(void)
  237. {
  238. cache_enable(CR_I);
  239. }
  240. void icache_disable(void)
  241. {
  242. cache_disable(CR_I);
  243. }
  244. int icache_status(void)
  245. {
  246. return (get_cr() & CR_I) != 0;
  247. }
  248. #endif
  249. #if CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  250. void dcache_enable(void)
  251. {
  252. return;
  253. }
  254. void dcache_disable(void)
  255. {
  256. return;
  257. }
  258. int dcache_status(void)
  259. {
  260. return 0; /* always off */
  261. }
  262. #else
  263. void dcache_enable(void)
  264. {
  265. cache_enable(CR_C);
  266. }
  267. void dcache_disable(void)
  268. {
  269. cache_disable(CR_C);
  270. }
  271. int dcache_status(void)
  272. {
  273. return (get_cr() & CR_C) != 0;
  274. }
  275. #endif