dwc_eth_qos.c 50 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2016, NVIDIA CORPORATION.
  4. *
  5. * Portions based on U-Boot's rtl8169.c.
  6. */
  7. /*
  8. * This driver supports the Synopsys Designware Ethernet QOS (Quality Of
  9. * Service) IP block. The IP supports multiple options for bus type, clocking/
  10. * reset structure, and feature list.
  11. *
  12. * The driver is written such that generic core logic is kept separate from
  13. * configuration-specific logic. Code that interacts with configuration-
  14. * specific resources is split out into separate functions to avoid polluting
  15. * common code. If/when this driver is enhanced to support multiple
  16. * configurations, the core code should be adapted to call all configuration-
  17. * specific functions through function pointers, with the definition of those
  18. * function pointers being supplied by struct udevice_id eqos_ids[]'s .data
  19. * field.
  20. *
  21. * The following configurations are currently supported:
  22. * tegra186:
  23. * NVIDIA's Tegra186 chip. This configuration uses an AXI master/DMA bus, an
  24. * AHB slave/register bus, contains the DMA, MTL, and MAC sub-blocks, and
  25. * supports a single RGMII PHY. This configuration also has SW control over
  26. * all clock and reset signals to the HW block.
  27. */
  28. #include <common.h>
  29. #include <clk.h>
  30. #include <dm.h>
  31. #include <errno.h>
  32. #include <memalign.h>
  33. #include <miiphy.h>
  34. #include <net.h>
  35. #include <netdev.h>
  36. #include <phy.h>
  37. #include <reset.h>
  38. #include <wait_bit.h>
  39. #include <asm/gpio.h>
  40. #include <asm/io.h>
  41. /* Core registers */
  42. #define EQOS_MAC_REGS_BASE 0x000
  43. struct eqos_mac_regs {
  44. uint32_t configuration; /* 0x000 */
  45. uint32_t unused_004[(0x070 - 0x004) / 4]; /* 0x004 */
  46. uint32_t q0_tx_flow_ctrl; /* 0x070 */
  47. uint32_t unused_070[(0x090 - 0x074) / 4]; /* 0x074 */
  48. uint32_t rx_flow_ctrl; /* 0x090 */
  49. uint32_t unused_094; /* 0x094 */
  50. uint32_t txq_prty_map0; /* 0x098 */
  51. uint32_t unused_09c; /* 0x09c */
  52. uint32_t rxq_ctrl0; /* 0x0a0 */
  53. uint32_t unused_0a4; /* 0x0a4 */
  54. uint32_t rxq_ctrl2; /* 0x0a8 */
  55. uint32_t unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */
  56. uint32_t us_tic_counter; /* 0x0dc */
  57. uint32_t unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */
  58. uint32_t hw_feature0; /* 0x11c */
  59. uint32_t hw_feature1; /* 0x120 */
  60. uint32_t hw_feature2; /* 0x124 */
  61. uint32_t unused_128[(0x200 - 0x128) / 4]; /* 0x128 */
  62. uint32_t mdio_address; /* 0x200 */
  63. uint32_t mdio_data; /* 0x204 */
  64. uint32_t unused_208[(0x300 - 0x208) / 4]; /* 0x208 */
  65. uint32_t address0_high; /* 0x300 */
  66. uint32_t address0_low; /* 0x304 */
  67. };
  68. #define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23)
  69. #define EQOS_MAC_CONFIGURATION_CST BIT(21)
  70. #define EQOS_MAC_CONFIGURATION_ACS BIT(20)
  71. #define EQOS_MAC_CONFIGURATION_WD BIT(19)
  72. #define EQOS_MAC_CONFIGURATION_JD BIT(17)
  73. #define EQOS_MAC_CONFIGURATION_JE BIT(16)
  74. #define EQOS_MAC_CONFIGURATION_PS BIT(15)
  75. #define EQOS_MAC_CONFIGURATION_FES BIT(14)
  76. #define EQOS_MAC_CONFIGURATION_DM BIT(13)
  77. #define EQOS_MAC_CONFIGURATION_TE BIT(1)
  78. #define EQOS_MAC_CONFIGURATION_RE BIT(0)
  79. #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
  80. #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff
  81. #define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1)
  82. #define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0)
  83. #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0
  84. #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff
  85. #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0
  86. #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
  87. #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
  88. #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
  89. #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
  90. #define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
  91. #define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
  92. #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6
  93. #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f
  94. #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0
  95. #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f
  96. #define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
  97. #define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16
  98. #define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
  99. #define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
  100. #define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
  101. #define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
  102. #define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2
  103. #define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3
  104. #define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1
  105. #define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1)
  106. #define EQOS_MAC_MDIO_ADDRESS_GB BIT(0)
  107. #define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff
  108. #define EQOS_MTL_REGS_BASE 0xd00
  109. struct eqos_mtl_regs {
  110. uint32_t txq0_operation_mode; /* 0xd00 */
  111. uint32_t unused_d04; /* 0xd04 */
  112. uint32_t txq0_debug; /* 0xd08 */
  113. uint32_t unused_d0c[(0xd18 - 0xd0c) / 4]; /* 0xd0c */
  114. uint32_t txq0_quantum_weight; /* 0xd18 */
  115. uint32_t unused_d1c[(0xd30 - 0xd1c) / 4]; /* 0xd1c */
  116. uint32_t rxq0_operation_mode; /* 0xd30 */
  117. uint32_t unused_d34; /* 0xd34 */
  118. uint32_t rxq0_debug; /* 0xd38 */
  119. };
  120. #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16
  121. #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff
  122. #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2
  123. #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3
  124. #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2
  125. #define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1)
  126. #define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0)
  127. #define EQOS_MTL_TXQ0_DEBUG_TXQSTS BIT(4)
  128. #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1
  129. #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK 3
  130. #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20
  131. #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff
  132. #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14
  133. #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f
  134. #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8
  135. #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f
  136. #define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7)
  137. #define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5)
  138. #define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16
  139. #define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff
  140. #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4
  141. #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK 3
  142. #define EQOS_DMA_REGS_BASE 0x1000
  143. struct eqos_dma_regs {
  144. uint32_t mode; /* 0x1000 */
  145. uint32_t sysbus_mode; /* 0x1004 */
  146. uint32_t unused_1008[(0x1100 - 0x1008) / 4]; /* 0x1008 */
  147. uint32_t ch0_control; /* 0x1100 */
  148. uint32_t ch0_tx_control; /* 0x1104 */
  149. uint32_t ch0_rx_control; /* 0x1108 */
  150. uint32_t unused_110c; /* 0x110c */
  151. uint32_t ch0_txdesc_list_haddress; /* 0x1110 */
  152. uint32_t ch0_txdesc_list_address; /* 0x1114 */
  153. uint32_t ch0_rxdesc_list_haddress; /* 0x1118 */
  154. uint32_t ch0_rxdesc_list_address; /* 0x111c */
  155. uint32_t ch0_txdesc_tail_pointer; /* 0x1120 */
  156. uint32_t unused_1124; /* 0x1124 */
  157. uint32_t ch0_rxdesc_tail_pointer; /* 0x1128 */
  158. uint32_t ch0_txdesc_ring_length; /* 0x112c */
  159. uint32_t ch0_rxdesc_ring_length; /* 0x1130 */
  160. };
  161. #define EQOS_DMA_MODE_SWR BIT(0)
  162. #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16
  163. #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf
  164. #define EQOS_DMA_SYSBUS_MODE_EAME BIT(11)
  165. #define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3)
  166. #define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2)
  167. #define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1)
  168. #define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16)
  169. #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16
  170. #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f
  171. #define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4)
  172. #define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0)
  173. #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16
  174. #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f
  175. #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1
  176. #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff
  177. #define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0)
  178. /* These registers are Tegra186-specific */
  179. #define EQOS_TEGRA186_REGS_BASE 0x8800
  180. struct eqos_tegra186_regs {
  181. uint32_t sdmemcomppadctrl; /* 0x8800 */
  182. uint32_t auto_cal_config; /* 0x8804 */
  183. uint32_t unused_8808; /* 0x8808 */
  184. uint32_t auto_cal_status; /* 0x880c */
  185. };
  186. #define EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31)
  187. #define EQOS_AUTO_CAL_CONFIG_START BIT(31)
  188. #define EQOS_AUTO_CAL_CONFIG_ENABLE BIT(29)
  189. #define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31)
  190. /* Descriptors */
  191. #define EQOS_DESCRIPTOR_WORDS 4
  192. #define EQOS_DESCRIPTOR_SIZE (EQOS_DESCRIPTOR_WORDS * 4)
  193. /* We assume ARCH_DMA_MINALIGN >= 16; 16 is the EQOS HW minimum */
  194. #define EQOS_DESCRIPTOR_ALIGN ARCH_DMA_MINALIGN
  195. #define EQOS_DESCRIPTORS_TX 4
  196. #define EQOS_DESCRIPTORS_RX 4
  197. #define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX)
  198. #define EQOS_DESCRIPTORS_SIZE ALIGN(EQOS_DESCRIPTORS_NUM * \
  199. EQOS_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN)
  200. #define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN
  201. #define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN)
  202. #define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE)
  203. /*
  204. * Warn if the cache-line size is larger than the descriptor size. In such
  205. * cases the driver will likely fail because the CPU needs to flush the cache
  206. * when requeuing RX buffers, therefore descriptors written by the hardware
  207. * may be discarded. Architectures with full IO coherence, such as x86, do not
  208. * experience this issue, and hence are excluded from this condition.
  209. *
  210. * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
  211. * the driver to allocate descriptors from a pool of non-cached memory.
  212. */
  213. #if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN
  214. #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
  215. !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
  216. #warning Cache line size is larger than descriptor size
  217. #endif
  218. #endif
  219. struct eqos_desc {
  220. u32 des0;
  221. u32 des1;
  222. u32 des2;
  223. u32 des3;
  224. };
  225. #define EQOS_DESC3_OWN BIT(31)
  226. #define EQOS_DESC3_FD BIT(29)
  227. #define EQOS_DESC3_LD BIT(28)
  228. #define EQOS_DESC3_BUF1V BIT(24)
  229. struct eqos_config {
  230. bool reg_access_always_ok;
  231. int mdio_wait;
  232. int swr_wait;
  233. int config_mac;
  234. int config_mac_mdio;
  235. phy_interface_t (*interface)(struct udevice *dev);
  236. struct eqos_ops *ops;
  237. };
  238. struct eqos_ops {
  239. void (*eqos_inval_desc)(void *desc);
  240. void (*eqos_flush_desc)(void *desc);
  241. void (*eqos_inval_buffer)(void *buf, size_t size);
  242. void (*eqos_flush_buffer)(void *buf, size_t size);
  243. int (*eqos_probe_resources)(struct udevice *dev);
  244. int (*eqos_remove_resources)(struct udevice *dev);
  245. int (*eqos_stop_resets)(struct udevice *dev);
  246. int (*eqos_start_resets)(struct udevice *dev);
  247. void (*eqos_stop_clks)(struct udevice *dev);
  248. int (*eqos_start_clks)(struct udevice *dev);
  249. int (*eqos_calibrate_pads)(struct udevice *dev);
  250. int (*eqos_disable_calibration)(struct udevice *dev);
  251. int (*eqos_set_tx_clk_speed)(struct udevice *dev);
  252. ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
  253. };
  254. struct eqos_priv {
  255. struct udevice *dev;
  256. const struct eqos_config *config;
  257. fdt_addr_t regs;
  258. struct eqos_mac_regs *mac_regs;
  259. struct eqos_mtl_regs *mtl_regs;
  260. struct eqos_dma_regs *dma_regs;
  261. struct eqos_tegra186_regs *tegra186_regs;
  262. struct reset_ctl reset_ctl;
  263. struct gpio_desc phy_reset_gpio;
  264. struct clk clk_master_bus;
  265. struct clk clk_rx;
  266. struct clk clk_ptp_ref;
  267. struct clk clk_tx;
  268. struct clk clk_ck;
  269. struct clk clk_slave_bus;
  270. struct mii_dev *mii;
  271. struct phy_device *phy;
  272. void *descs;
  273. struct eqos_desc *tx_descs;
  274. struct eqos_desc *rx_descs;
  275. int tx_desc_idx, rx_desc_idx;
  276. void *tx_dma_buf;
  277. void *rx_dma_buf;
  278. void *rx_pkt;
  279. bool started;
  280. bool reg_access_ok;
  281. };
  282. /*
  283. * TX and RX descriptors are 16 bytes. This causes problems with the cache
  284. * maintenance on CPUs where the cache-line size exceeds the size of these
  285. * descriptors. What will happen is that when the driver receives a packet
  286. * it will be immediately requeued for the hardware to reuse. The CPU will
  287. * therefore need to flush the cache-line containing the descriptor, which
  288. * will cause all other descriptors in the same cache-line to be flushed
  289. * along with it. If one of those descriptors had been written to by the
  290. * device those changes (and the associated packet) will be lost.
  291. *
  292. * To work around this, we make use of non-cached memory if available. If
  293. * descriptors are mapped uncached there's no need to manually flush them
  294. * or invalidate them.
  295. *
  296. * Note that this only applies to descriptors. The packet data buffers do
  297. * not have the same constraints since they are 1536 bytes large, so they
  298. * are unlikely to share cache-lines.
  299. */
  300. static void *eqos_alloc_descs(unsigned int num)
  301. {
  302. #ifdef CONFIG_SYS_NONCACHED_MEMORY
  303. return (void *)noncached_alloc(EQOS_DESCRIPTORS_SIZE,
  304. EQOS_DESCRIPTOR_ALIGN);
  305. #else
  306. return memalign(EQOS_DESCRIPTOR_ALIGN, EQOS_DESCRIPTORS_SIZE);
  307. #endif
  308. }
  309. static void eqos_free_descs(void *descs)
  310. {
  311. #ifdef CONFIG_SYS_NONCACHED_MEMORY
  312. /* FIXME: noncached_alloc() has no opposite */
  313. #else
  314. free(descs);
  315. #endif
  316. }
  317. static void eqos_inval_desc_tegra186(void *desc)
  318. {
  319. #ifndef CONFIG_SYS_NONCACHED_MEMORY
  320. unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
  321. unsigned long end = ALIGN(start + EQOS_DESCRIPTOR_SIZE,
  322. ARCH_DMA_MINALIGN);
  323. invalidate_dcache_range(start, end);
  324. #endif
  325. }
  326. static void eqos_inval_desc_stm32(void *desc)
  327. {
  328. #ifndef CONFIG_SYS_NONCACHED_MEMORY
  329. unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN);
  330. unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE,
  331. ARCH_DMA_MINALIGN);
  332. invalidate_dcache_range(start, end);
  333. #endif
  334. }
  335. static void eqos_flush_desc_tegra186(void *desc)
  336. {
  337. #ifndef CONFIG_SYS_NONCACHED_MEMORY
  338. flush_cache((unsigned long)desc, EQOS_DESCRIPTOR_SIZE);
  339. #endif
  340. }
  341. static void eqos_flush_desc_stm32(void *desc)
  342. {
  343. #ifndef CONFIG_SYS_NONCACHED_MEMORY
  344. unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN);
  345. unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE,
  346. ARCH_DMA_MINALIGN);
  347. flush_dcache_range(start, end);
  348. #endif
  349. }
  350. static void eqos_inval_buffer_tegra186(void *buf, size_t size)
  351. {
  352. unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
  353. unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
  354. invalidate_dcache_range(start, end);
  355. }
  356. static void eqos_inval_buffer_stm32(void *buf, size_t size)
  357. {
  358. unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
  359. unsigned long end = roundup((unsigned long)buf + size,
  360. ARCH_DMA_MINALIGN);
  361. invalidate_dcache_range(start, end);
  362. }
  363. static void eqos_flush_buffer_tegra186(void *buf, size_t size)
  364. {
  365. flush_cache((unsigned long)buf, size);
  366. }
  367. static void eqos_flush_buffer_stm32(void *buf, size_t size)
  368. {
  369. unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
  370. unsigned long end = roundup((unsigned long)buf + size,
  371. ARCH_DMA_MINALIGN);
  372. flush_dcache_range(start, end);
  373. }
  374. static int eqos_mdio_wait_idle(struct eqos_priv *eqos)
  375. {
  376. return wait_for_bit_le32(&eqos->mac_regs->mdio_address,
  377. EQOS_MAC_MDIO_ADDRESS_GB, false,
  378. 1000000, true);
  379. }
  380. static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad,
  381. int mdio_reg)
  382. {
  383. struct eqos_priv *eqos = bus->priv;
  384. u32 val;
  385. int ret;
  386. debug("%s(dev=%p, addr=%x, reg=%d):\n", __func__, eqos->dev, mdio_addr,
  387. mdio_reg);
  388. ret = eqos_mdio_wait_idle(eqos);
  389. if (ret) {
  390. pr_err("MDIO not idle at entry");
  391. return ret;
  392. }
  393. val = readl(&eqos->mac_regs->mdio_address);
  394. val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
  395. EQOS_MAC_MDIO_ADDRESS_C45E;
  396. val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
  397. (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
  398. (eqos->config->config_mac_mdio <<
  399. EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
  400. (EQOS_MAC_MDIO_ADDRESS_GOC_READ <<
  401. EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
  402. EQOS_MAC_MDIO_ADDRESS_GB;
  403. writel(val, &eqos->mac_regs->mdio_address);
  404. udelay(eqos->config->mdio_wait);
  405. ret = eqos_mdio_wait_idle(eqos);
  406. if (ret) {
  407. pr_err("MDIO read didn't complete");
  408. return ret;
  409. }
  410. val = readl(&eqos->mac_regs->mdio_data);
  411. val &= EQOS_MAC_MDIO_DATA_GD_MASK;
  412. debug("%s: val=%x\n", __func__, val);
  413. return val;
  414. }
  415. static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad,
  416. int mdio_reg, u16 mdio_val)
  417. {
  418. struct eqos_priv *eqos = bus->priv;
  419. u32 val;
  420. int ret;
  421. debug("%s(dev=%p, addr=%x, reg=%d, val=%x):\n", __func__, eqos->dev,
  422. mdio_addr, mdio_reg, mdio_val);
  423. ret = eqos_mdio_wait_idle(eqos);
  424. if (ret) {
  425. pr_err("MDIO not idle at entry");
  426. return ret;
  427. }
  428. writel(mdio_val, &eqos->mac_regs->mdio_data);
  429. val = readl(&eqos->mac_regs->mdio_address);
  430. val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
  431. EQOS_MAC_MDIO_ADDRESS_C45E;
  432. val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
  433. (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
  434. (eqos->config->config_mac_mdio <<
  435. EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
  436. (EQOS_MAC_MDIO_ADDRESS_GOC_WRITE <<
  437. EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
  438. EQOS_MAC_MDIO_ADDRESS_GB;
  439. writel(val, &eqos->mac_regs->mdio_address);
  440. udelay(eqos->config->mdio_wait);
  441. ret = eqos_mdio_wait_idle(eqos);
  442. if (ret) {
  443. pr_err("MDIO read didn't complete");
  444. return ret;
  445. }
  446. return 0;
  447. }
  448. static int eqos_start_clks_tegra186(struct udevice *dev)
  449. {
  450. struct eqos_priv *eqos = dev_get_priv(dev);
  451. int ret;
  452. debug("%s(dev=%p):\n", __func__, dev);
  453. ret = clk_enable(&eqos->clk_slave_bus);
  454. if (ret < 0) {
  455. pr_err("clk_enable(clk_slave_bus) failed: %d", ret);
  456. goto err;
  457. }
  458. ret = clk_enable(&eqos->clk_master_bus);
  459. if (ret < 0) {
  460. pr_err("clk_enable(clk_master_bus) failed: %d", ret);
  461. goto err_disable_clk_slave_bus;
  462. }
  463. ret = clk_enable(&eqos->clk_rx);
  464. if (ret < 0) {
  465. pr_err("clk_enable(clk_rx) failed: %d", ret);
  466. goto err_disable_clk_master_bus;
  467. }
  468. ret = clk_enable(&eqos->clk_ptp_ref);
  469. if (ret < 0) {
  470. pr_err("clk_enable(clk_ptp_ref) failed: %d", ret);
  471. goto err_disable_clk_rx;
  472. }
  473. ret = clk_set_rate(&eqos->clk_ptp_ref, 125 * 1000 * 1000);
  474. if (ret < 0) {
  475. pr_err("clk_set_rate(clk_ptp_ref) failed: %d", ret);
  476. goto err_disable_clk_ptp_ref;
  477. }
  478. ret = clk_enable(&eqos->clk_tx);
  479. if (ret < 0) {
  480. pr_err("clk_enable(clk_tx) failed: %d", ret);
  481. goto err_disable_clk_ptp_ref;
  482. }
  483. debug("%s: OK\n", __func__);
  484. return 0;
  485. err_disable_clk_ptp_ref:
  486. clk_disable(&eqos->clk_ptp_ref);
  487. err_disable_clk_rx:
  488. clk_disable(&eqos->clk_rx);
  489. err_disable_clk_master_bus:
  490. clk_disable(&eqos->clk_master_bus);
  491. err_disable_clk_slave_bus:
  492. clk_disable(&eqos->clk_slave_bus);
  493. err:
  494. debug("%s: FAILED: %d\n", __func__, ret);
  495. return ret;
  496. }
  497. static int eqos_start_clks_stm32(struct udevice *dev)
  498. {
  499. struct eqos_priv *eqos = dev_get_priv(dev);
  500. int ret;
  501. debug("%s(dev=%p):\n", __func__, dev);
  502. ret = clk_enable(&eqos->clk_master_bus);
  503. if (ret < 0) {
  504. pr_err("clk_enable(clk_master_bus) failed: %d", ret);
  505. goto err;
  506. }
  507. ret = clk_enable(&eqos->clk_rx);
  508. if (ret < 0) {
  509. pr_err("clk_enable(clk_rx) failed: %d", ret);
  510. goto err_disable_clk_master_bus;
  511. }
  512. ret = clk_enable(&eqos->clk_tx);
  513. if (ret < 0) {
  514. pr_err("clk_enable(clk_tx) failed: %d", ret);
  515. goto err_disable_clk_rx;
  516. }
  517. if (clk_valid(&eqos->clk_ck)) {
  518. ret = clk_enable(&eqos->clk_ck);
  519. if (ret < 0) {
  520. pr_err("clk_enable(clk_ck) failed: %d", ret);
  521. goto err_disable_clk_tx;
  522. }
  523. }
  524. debug("%s: OK\n", __func__);
  525. return 0;
  526. err_disable_clk_tx:
  527. clk_disable(&eqos->clk_tx);
  528. err_disable_clk_rx:
  529. clk_disable(&eqos->clk_rx);
  530. err_disable_clk_master_bus:
  531. clk_disable(&eqos->clk_master_bus);
  532. err:
  533. debug("%s: FAILED: %d\n", __func__, ret);
  534. return ret;
  535. }
  536. static void eqos_stop_clks_tegra186(struct udevice *dev)
  537. {
  538. struct eqos_priv *eqos = dev_get_priv(dev);
  539. debug("%s(dev=%p):\n", __func__, dev);
  540. clk_disable(&eqos->clk_tx);
  541. clk_disable(&eqos->clk_ptp_ref);
  542. clk_disable(&eqos->clk_rx);
  543. clk_disable(&eqos->clk_master_bus);
  544. clk_disable(&eqos->clk_slave_bus);
  545. debug("%s: OK\n", __func__);
  546. }
  547. static void eqos_stop_clks_stm32(struct udevice *dev)
  548. {
  549. struct eqos_priv *eqos = dev_get_priv(dev);
  550. debug("%s(dev=%p):\n", __func__, dev);
  551. clk_disable(&eqos->clk_tx);
  552. clk_disable(&eqos->clk_rx);
  553. clk_disable(&eqos->clk_master_bus);
  554. if (clk_valid(&eqos->clk_ck))
  555. clk_disable(&eqos->clk_ck);
  556. debug("%s: OK\n", __func__);
  557. }
  558. static int eqos_start_resets_tegra186(struct udevice *dev)
  559. {
  560. struct eqos_priv *eqos = dev_get_priv(dev);
  561. int ret;
  562. debug("%s(dev=%p):\n", __func__, dev);
  563. ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
  564. if (ret < 0) {
  565. pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", ret);
  566. return ret;
  567. }
  568. udelay(2);
  569. ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
  570. if (ret < 0) {
  571. pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret);
  572. return ret;
  573. }
  574. ret = reset_assert(&eqos->reset_ctl);
  575. if (ret < 0) {
  576. pr_err("reset_assert() failed: %d", ret);
  577. return ret;
  578. }
  579. udelay(2);
  580. ret = reset_deassert(&eqos->reset_ctl);
  581. if (ret < 0) {
  582. pr_err("reset_deassert() failed: %d", ret);
  583. return ret;
  584. }
  585. debug("%s: OK\n", __func__);
  586. return 0;
  587. }
  588. static int eqos_start_resets_stm32(struct udevice *dev)
  589. {
  590. return 0;
  591. }
  592. static int eqos_stop_resets_tegra186(struct udevice *dev)
  593. {
  594. struct eqos_priv *eqos = dev_get_priv(dev);
  595. reset_assert(&eqos->reset_ctl);
  596. dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
  597. return 0;
  598. }
  599. static int eqos_stop_resets_stm32(struct udevice *dev)
  600. {
  601. return 0;
  602. }
  603. static int eqos_calibrate_pads_tegra186(struct udevice *dev)
  604. {
  605. struct eqos_priv *eqos = dev_get_priv(dev);
  606. int ret;
  607. debug("%s(dev=%p):\n", __func__, dev);
  608. setbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
  609. EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
  610. udelay(1);
  611. setbits_le32(&eqos->tegra186_regs->auto_cal_config,
  612. EQOS_AUTO_CAL_CONFIG_START | EQOS_AUTO_CAL_CONFIG_ENABLE);
  613. ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
  614. EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false);
  615. if (ret) {
  616. pr_err("calibrate didn't start");
  617. goto failed;
  618. }
  619. ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
  620. EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false);
  621. if (ret) {
  622. pr_err("calibrate didn't finish");
  623. goto failed;
  624. }
  625. ret = 0;
  626. failed:
  627. clrbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
  628. EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
  629. debug("%s: returns %d\n", __func__, ret);
  630. return ret;
  631. }
  632. static int eqos_disable_calibration_tegra186(struct udevice *dev)
  633. {
  634. struct eqos_priv *eqos = dev_get_priv(dev);
  635. debug("%s(dev=%p):\n", __func__, dev);
  636. clrbits_le32(&eqos->tegra186_regs->auto_cal_config,
  637. EQOS_AUTO_CAL_CONFIG_ENABLE);
  638. return 0;
  639. }
  640. static ulong eqos_get_tick_clk_rate_tegra186(struct udevice *dev)
  641. {
  642. struct eqos_priv *eqos = dev_get_priv(dev);
  643. return clk_get_rate(&eqos->clk_slave_bus);
  644. }
  645. static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev)
  646. {
  647. struct eqos_priv *eqos = dev_get_priv(dev);
  648. return clk_get_rate(&eqos->clk_master_bus);
  649. }
  650. static int eqos_calibrate_pads_stm32(struct udevice *dev)
  651. {
  652. return 0;
  653. }
  654. static int eqos_disable_calibration_stm32(struct udevice *dev)
  655. {
  656. return 0;
  657. }
  658. static int eqos_set_full_duplex(struct udevice *dev)
  659. {
  660. struct eqos_priv *eqos = dev_get_priv(dev);
  661. debug("%s(dev=%p):\n", __func__, dev);
  662. setbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
  663. return 0;
  664. }
  665. static int eqos_set_half_duplex(struct udevice *dev)
  666. {
  667. struct eqos_priv *eqos = dev_get_priv(dev);
  668. debug("%s(dev=%p):\n", __func__, dev);
  669. clrbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
  670. /* WAR: Flush TX queue when switching to half-duplex */
  671. setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
  672. EQOS_MTL_TXQ0_OPERATION_MODE_FTQ);
  673. return 0;
  674. }
  675. static int eqos_set_gmii_speed(struct udevice *dev)
  676. {
  677. struct eqos_priv *eqos = dev_get_priv(dev);
  678. debug("%s(dev=%p):\n", __func__, dev);
  679. clrbits_le32(&eqos->mac_regs->configuration,
  680. EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
  681. return 0;
  682. }
  683. static int eqos_set_mii_speed_100(struct udevice *dev)
  684. {
  685. struct eqos_priv *eqos = dev_get_priv(dev);
  686. debug("%s(dev=%p):\n", __func__, dev);
  687. setbits_le32(&eqos->mac_regs->configuration,
  688. EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
  689. return 0;
  690. }
  691. static int eqos_set_mii_speed_10(struct udevice *dev)
  692. {
  693. struct eqos_priv *eqos = dev_get_priv(dev);
  694. debug("%s(dev=%p):\n", __func__, dev);
  695. clrsetbits_le32(&eqos->mac_regs->configuration,
  696. EQOS_MAC_CONFIGURATION_FES, EQOS_MAC_CONFIGURATION_PS);
  697. return 0;
  698. }
  699. static int eqos_set_tx_clk_speed_tegra186(struct udevice *dev)
  700. {
  701. struct eqos_priv *eqos = dev_get_priv(dev);
  702. ulong rate;
  703. int ret;
  704. debug("%s(dev=%p):\n", __func__, dev);
  705. switch (eqos->phy->speed) {
  706. case SPEED_1000:
  707. rate = 125 * 1000 * 1000;
  708. break;
  709. case SPEED_100:
  710. rate = 25 * 1000 * 1000;
  711. break;
  712. case SPEED_10:
  713. rate = 2.5 * 1000 * 1000;
  714. break;
  715. default:
  716. pr_err("invalid speed %d", eqos->phy->speed);
  717. return -EINVAL;
  718. }
  719. ret = clk_set_rate(&eqos->clk_tx, rate);
  720. if (ret < 0) {
  721. pr_err("clk_set_rate(tx_clk, %lu) failed: %d", rate, ret);
  722. return ret;
  723. }
  724. return 0;
  725. }
  726. static int eqos_set_tx_clk_speed_stm32(struct udevice *dev)
  727. {
  728. return 0;
  729. }
  730. static int eqos_adjust_link(struct udevice *dev)
  731. {
  732. struct eqos_priv *eqos = dev_get_priv(dev);
  733. int ret;
  734. bool en_calibration;
  735. debug("%s(dev=%p):\n", __func__, dev);
  736. if (eqos->phy->duplex)
  737. ret = eqos_set_full_duplex(dev);
  738. else
  739. ret = eqos_set_half_duplex(dev);
  740. if (ret < 0) {
  741. pr_err("eqos_set_*_duplex() failed: %d", ret);
  742. return ret;
  743. }
  744. switch (eqos->phy->speed) {
  745. case SPEED_1000:
  746. en_calibration = true;
  747. ret = eqos_set_gmii_speed(dev);
  748. break;
  749. case SPEED_100:
  750. en_calibration = true;
  751. ret = eqos_set_mii_speed_100(dev);
  752. break;
  753. case SPEED_10:
  754. en_calibration = false;
  755. ret = eqos_set_mii_speed_10(dev);
  756. break;
  757. default:
  758. pr_err("invalid speed %d", eqos->phy->speed);
  759. return -EINVAL;
  760. }
  761. if (ret < 0) {
  762. pr_err("eqos_set_*mii_speed*() failed: %d", ret);
  763. return ret;
  764. }
  765. if (en_calibration) {
  766. ret = eqos->config->ops->eqos_calibrate_pads(dev);
  767. if (ret < 0) {
  768. pr_err("eqos_calibrate_pads() failed: %d",
  769. ret);
  770. return ret;
  771. }
  772. } else {
  773. ret = eqos->config->ops->eqos_disable_calibration(dev);
  774. if (ret < 0) {
  775. pr_err("eqos_disable_calibration() failed: %d",
  776. ret);
  777. return ret;
  778. }
  779. }
  780. ret = eqos->config->ops->eqos_set_tx_clk_speed(dev);
  781. if (ret < 0) {
  782. pr_err("eqos_set_tx_clk_speed() failed: %d", ret);
  783. return ret;
  784. }
  785. return 0;
  786. }
  787. static int eqos_write_hwaddr(struct udevice *dev)
  788. {
  789. struct eth_pdata *plat = dev_get_platdata(dev);
  790. struct eqos_priv *eqos = dev_get_priv(dev);
  791. uint32_t val;
  792. /*
  793. * This function may be called before start() or after stop(). At that
  794. * time, on at least some configurations of the EQoS HW, all clocks to
  795. * the EQoS HW block will be stopped, and a reset signal applied. If
  796. * any register access is attempted in this state, bus timeouts or CPU
  797. * hangs may occur. This check prevents that.
  798. *
  799. * A simple solution to this problem would be to not implement
  800. * write_hwaddr(), since start() always writes the MAC address into HW
  801. * anyway. However, it is desirable to implement write_hwaddr() to
  802. * support the case of SW that runs subsequent to U-Boot which expects
  803. * the MAC address to already be programmed into the EQoS registers,
  804. * which must happen irrespective of whether the U-Boot user (or
  805. * scripts) actually made use of the EQoS device, and hence
  806. * irrespective of whether start() was ever called.
  807. *
  808. * Note that this requirement by subsequent SW is not valid for
  809. * Tegra186, and is likely not valid for any non-PCI instantiation of
  810. * the EQoS HW block. This function is implemented solely as
  811. * future-proofing with the expectation the driver will eventually be
  812. * ported to some system where the expectation above is true.
  813. */
  814. if (!eqos->config->reg_access_always_ok && !eqos->reg_access_ok)
  815. return 0;
  816. /* Update the MAC address */
  817. val = (plat->enetaddr[5] << 8) |
  818. (plat->enetaddr[4]);
  819. writel(val, &eqos->mac_regs->address0_high);
  820. val = (plat->enetaddr[3] << 24) |
  821. (plat->enetaddr[2] << 16) |
  822. (plat->enetaddr[1] << 8) |
  823. (plat->enetaddr[0]);
  824. writel(val, &eqos->mac_regs->address0_low);
  825. return 0;
  826. }
  827. static int eqos_start(struct udevice *dev)
  828. {
  829. struct eqos_priv *eqos = dev_get_priv(dev);
  830. int ret, i;
  831. ulong rate;
  832. u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
  833. ulong last_rx_desc;
  834. debug("%s(dev=%p):\n", __func__, dev);
  835. eqos->tx_desc_idx = 0;
  836. eqos->rx_desc_idx = 0;
  837. ret = eqos->config->ops->eqos_start_clks(dev);
  838. if (ret < 0) {
  839. pr_err("eqos_start_clks() failed: %d", ret);
  840. goto err;
  841. }
  842. ret = eqos->config->ops->eqos_start_resets(dev);
  843. if (ret < 0) {
  844. pr_err("eqos_start_resets() failed: %d", ret);
  845. goto err_stop_clks;
  846. }
  847. udelay(10);
  848. eqos->reg_access_ok = true;
  849. ret = wait_for_bit_le32(&eqos->dma_regs->mode,
  850. EQOS_DMA_MODE_SWR, false,
  851. eqos->config->swr_wait, false);
  852. if (ret) {
  853. pr_err("EQOS_DMA_MODE_SWR stuck");
  854. goto err_stop_resets;
  855. }
  856. ret = eqos->config->ops->eqos_calibrate_pads(dev);
  857. if (ret < 0) {
  858. pr_err("eqos_calibrate_pads() failed: %d", ret);
  859. goto err_stop_resets;
  860. }
  861. rate = eqos->config->ops->eqos_get_tick_clk_rate(dev);
  862. val = (rate / 1000000) - 1;
  863. writel(val, &eqos->mac_regs->us_tic_counter);
  864. /*
  865. * if PHY was already connected and configured,
  866. * don't need to reconnect/reconfigure again
  867. */
  868. if (!eqos->phy) {
  869. eqos->phy = phy_connect(eqos->mii, 0, dev,
  870. eqos->config->interface(dev));
  871. if (!eqos->phy) {
  872. pr_err("phy_connect() failed");
  873. goto err_stop_resets;
  874. }
  875. ret = phy_config(eqos->phy);
  876. if (ret < 0) {
  877. pr_err("phy_config() failed: %d", ret);
  878. goto err_shutdown_phy;
  879. }
  880. }
  881. ret = phy_startup(eqos->phy);
  882. if (ret < 0) {
  883. pr_err("phy_startup() failed: %d", ret);
  884. goto err_shutdown_phy;
  885. }
  886. if (!eqos->phy->link) {
  887. pr_err("No link");
  888. goto err_shutdown_phy;
  889. }
  890. ret = eqos_adjust_link(dev);
  891. if (ret < 0) {
  892. pr_err("eqos_adjust_link() failed: %d", ret);
  893. goto err_shutdown_phy;
  894. }
  895. /* Configure MTL */
  896. /* Enable Store and Forward mode for TX */
  897. /* Program Tx operating mode */
  898. setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
  899. EQOS_MTL_TXQ0_OPERATION_MODE_TSF |
  900. (EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED <<
  901. EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT));
  902. /* Transmit Queue weight */
  903. writel(0x10, &eqos->mtl_regs->txq0_quantum_weight);
  904. /* Enable Store and Forward mode for RX, since no jumbo frame */
  905. setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
  906. EQOS_MTL_RXQ0_OPERATION_MODE_RSF);
  907. /* Transmit/Receive queue fifo size; use all RAM for 1 queue */
  908. val = readl(&eqos->mac_regs->hw_feature1);
  909. tx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) &
  910. EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK;
  911. rx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) &
  912. EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK;
  913. /*
  914. * r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting.
  915. * r/tqs is encoded as (n / 256) - 1.
  916. */
  917. tqs = (128 << tx_fifo_sz) / 256 - 1;
  918. rqs = (128 << rx_fifo_sz) / 256 - 1;
  919. clrsetbits_le32(&eqos->mtl_regs->txq0_operation_mode,
  920. EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK <<
  921. EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT,
  922. tqs << EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT);
  923. clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
  924. EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK <<
  925. EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT,
  926. rqs << EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT);
  927. /* Flow control used only if each channel gets 4KB or more FIFO */
  928. if (rqs >= ((4096 / 256) - 1)) {
  929. u32 rfd, rfa;
  930. setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
  931. EQOS_MTL_RXQ0_OPERATION_MODE_EHFC);
  932. /*
  933. * Set Threshold for Activating Flow Contol space for min 2
  934. * frames ie, (1500 * 1) = 1500 bytes.
  935. *
  936. * Set Threshold for Deactivating Flow Contol for space of
  937. * min 1 frame (frame size 1500bytes) in receive fifo
  938. */
  939. if (rqs == ((4096 / 256) - 1)) {
  940. /*
  941. * This violates the above formula because of FIFO size
  942. * limit therefore overflow may occur inspite of this.
  943. */
  944. rfd = 0x3; /* Full-3K */
  945. rfa = 0x1; /* Full-1.5K */
  946. } else if (rqs == ((8192 / 256) - 1)) {
  947. rfd = 0x6; /* Full-4K */
  948. rfa = 0xa; /* Full-6K */
  949. } else if (rqs == ((16384 / 256) - 1)) {
  950. rfd = 0x6; /* Full-4K */
  951. rfa = 0x12; /* Full-10K */
  952. } else {
  953. rfd = 0x6; /* Full-4K */
  954. rfa = 0x1E; /* Full-16K */
  955. }
  956. clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
  957. (EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK <<
  958. EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
  959. (EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK <<
  960. EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT),
  961. (rfd <<
  962. EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
  963. (rfa <<
  964. EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT));
  965. }
  966. /* Configure MAC */
  967. clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0,
  968. EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
  969. EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
  970. eqos->config->config_mac <<
  971. EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
  972. /* Set TX flow control parameters */
  973. /* Set Pause Time */
  974. setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
  975. 0xffff << EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT);
  976. /* Assign priority for TX flow control */
  977. clrbits_le32(&eqos->mac_regs->txq_prty_map0,
  978. EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK <<
  979. EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT);
  980. /* Assign priority for RX flow control */
  981. clrbits_le32(&eqos->mac_regs->rxq_ctrl2,
  982. EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK <<
  983. EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT);
  984. /* Enable flow control */
  985. setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
  986. EQOS_MAC_Q0_TX_FLOW_CTRL_TFE);
  987. setbits_le32(&eqos->mac_regs->rx_flow_ctrl,
  988. EQOS_MAC_RX_FLOW_CTRL_RFE);
  989. clrsetbits_le32(&eqos->mac_regs->configuration,
  990. EQOS_MAC_CONFIGURATION_GPSLCE |
  991. EQOS_MAC_CONFIGURATION_WD |
  992. EQOS_MAC_CONFIGURATION_JD |
  993. EQOS_MAC_CONFIGURATION_JE,
  994. EQOS_MAC_CONFIGURATION_CST |
  995. EQOS_MAC_CONFIGURATION_ACS);
  996. eqos_write_hwaddr(dev);
  997. /* Configure DMA */
  998. /* Enable OSP mode */
  999. setbits_le32(&eqos->dma_regs->ch0_tx_control,
  1000. EQOS_DMA_CH0_TX_CONTROL_OSP);
  1001. /* RX buffer size. Must be a multiple of bus width */
  1002. clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
  1003. EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK <<
  1004. EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT,
  1005. EQOS_MAX_PACKET_SIZE <<
  1006. EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT);
  1007. setbits_le32(&eqos->dma_regs->ch0_control,
  1008. EQOS_DMA_CH0_CONTROL_PBLX8);
  1009. /*
  1010. * Burst length must be < 1/2 FIFO size.
  1011. * FIFO size in tqs is encoded as (n / 256) - 1.
  1012. * Each burst is n * 8 (PBLX8) * 16 (AXI width) == 128 bytes.
  1013. * Half of n * 256 is n * 128, so pbl == tqs, modulo the -1.
  1014. */
  1015. pbl = tqs + 1;
  1016. if (pbl > 32)
  1017. pbl = 32;
  1018. clrsetbits_le32(&eqos->dma_regs->ch0_tx_control,
  1019. EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK <<
  1020. EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT,
  1021. pbl << EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT);
  1022. clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
  1023. EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK <<
  1024. EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT,
  1025. 8 << EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT);
  1026. /* DMA performance configuration */
  1027. val = (2 << EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) |
  1028. EQOS_DMA_SYSBUS_MODE_EAME | EQOS_DMA_SYSBUS_MODE_BLEN16 |
  1029. EQOS_DMA_SYSBUS_MODE_BLEN8 | EQOS_DMA_SYSBUS_MODE_BLEN4;
  1030. writel(val, &eqos->dma_regs->sysbus_mode);
  1031. /* Set up descriptors */
  1032. memset(eqos->descs, 0, EQOS_DESCRIPTORS_SIZE);
  1033. for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) {
  1034. struct eqos_desc *rx_desc = &(eqos->rx_descs[i]);
  1035. rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
  1036. (i * EQOS_MAX_PACKET_SIZE));
  1037. rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
  1038. }
  1039. eqos->config->ops->eqos_flush_desc(eqos->descs);
  1040. writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress);
  1041. writel((ulong)eqos->tx_descs, &eqos->dma_regs->ch0_txdesc_list_address);
  1042. writel(EQOS_DESCRIPTORS_TX - 1,
  1043. &eqos->dma_regs->ch0_txdesc_ring_length);
  1044. writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress);
  1045. writel((ulong)eqos->rx_descs, &eqos->dma_regs->ch0_rxdesc_list_address);
  1046. writel(EQOS_DESCRIPTORS_RX - 1,
  1047. &eqos->dma_regs->ch0_rxdesc_ring_length);
  1048. /* Enable everything */
  1049. setbits_le32(&eqos->mac_regs->configuration,
  1050. EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
  1051. setbits_le32(&eqos->dma_regs->ch0_tx_control,
  1052. EQOS_DMA_CH0_TX_CONTROL_ST);
  1053. setbits_le32(&eqos->dma_regs->ch0_rx_control,
  1054. EQOS_DMA_CH0_RX_CONTROL_SR);
  1055. /* TX tail pointer not written until we need to TX a packet */
  1056. /*
  1057. * Point RX tail pointer at last descriptor. Ideally, we'd point at the
  1058. * first descriptor, implying all descriptors were available. However,
  1059. * that's not distinguishable from none of the descriptors being
  1060. * available.
  1061. */
  1062. last_rx_desc = (ulong)&(eqos->rx_descs[(EQOS_DESCRIPTORS_RX - 1)]);
  1063. writel(last_rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
  1064. eqos->started = true;
  1065. debug("%s: OK\n", __func__);
  1066. return 0;
  1067. err_shutdown_phy:
  1068. phy_shutdown(eqos->phy);
  1069. err_stop_resets:
  1070. eqos->config->ops->eqos_stop_resets(dev);
  1071. err_stop_clks:
  1072. eqos->config->ops->eqos_stop_clks(dev);
  1073. err:
  1074. pr_err("FAILED: %d", ret);
  1075. return ret;
  1076. }
  1077. static void eqos_stop(struct udevice *dev)
  1078. {
  1079. struct eqos_priv *eqos = dev_get_priv(dev);
  1080. int i;
  1081. debug("%s(dev=%p):\n", __func__, dev);
  1082. if (!eqos->started)
  1083. return;
  1084. eqos->started = false;
  1085. eqos->reg_access_ok = false;
  1086. /* Disable TX DMA */
  1087. clrbits_le32(&eqos->dma_regs->ch0_tx_control,
  1088. EQOS_DMA_CH0_TX_CONTROL_ST);
  1089. /* Wait for TX all packets to drain out of MTL */
  1090. for (i = 0; i < 1000000; i++) {
  1091. u32 val = readl(&eqos->mtl_regs->txq0_debug);
  1092. u32 trcsts = (val >> EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) &
  1093. EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK;
  1094. u32 txqsts = val & EQOS_MTL_TXQ0_DEBUG_TXQSTS;
  1095. if ((trcsts != 1) && (!txqsts))
  1096. break;
  1097. }
  1098. /* Turn off MAC TX and RX */
  1099. clrbits_le32(&eqos->mac_regs->configuration,
  1100. EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
  1101. /* Wait for all RX packets to drain out of MTL */
  1102. for (i = 0; i < 1000000; i++) {
  1103. u32 val = readl(&eqos->mtl_regs->rxq0_debug);
  1104. u32 prxq = (val >> EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT) &
  1105. EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK;
  1106. u32 rxqsts = (val >> EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) &
  1107. EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK;
  1108. if ((!prxq) && (!rxqsts))
  1109. break;
  1110. }
  1111. /* Turn off RX DMA */
  1112. clrbits_le32(&eqos->dma_regs->ch0_rx_control,
  1113. EQOS_DMA_CH0_RX_CONTROL_SR);
  1114. if (eqos->phy) {
  1115. phy_shutdown(eqos->phy);
  1116. }
  1117. eqos->config->ops->eqos_stop_resets(dev);
  1118. eqos->config->ops->eqos_stop_clks(dev);
  1119. debug("%s: OK\n", __func__);
  1120. }
  1121. static int eqos_send(struct udevice *dev, void *packet, int length)
  1122. {
  1123. struct eqos_priv *eqos = dev_get_priv(dev);
  1124. struct eqos_desc *tx_desc;
  1125. int i;
  1126. debug("%s(dev=%p, packet=%p, length=%d):\n", __func__, dev, packet,
  1127. length);
  1128. memcpy(eqos->tx_dma_buf, packet, length);
  1129. eqos->config->ops->eqos_flush_buffer(eqos->tx_dma_buf, length);
  1130. tx_desc = &(eqos->tx_descs[eqos->tx_desc_idx]);
  1131. eqos->tx_desc_idx++;
  1132. eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX;
  1133. tx_desc->des0 = (ulong)eqos->tx_dma_buf;
  1134. tx_desc->des1 = 0;
  1135. tx_desc->des2 = length;
  1136. /*
  1137. * Make sure that if HW sees the _OWN write below, it will see all the
  1138. * writes to the rest of the descriptor too.
  1139. */
  1140. mb();
  1141. tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length;
  1142. eqos->config->ops->eqos_flush_desc(tx_desc);
  1143. writel((ulong)(tx_desc + 1), &eqos->dma_regs->ch0_txdesc_tail_pointer);
  1144. for (i = 0; i < 1000000; i++) {
  1145. eqos->config->ops->eqos_inval_desc(tx_desc);
  1146. if (!(readl(&tx_desc->des3) & EQOS_DESC3_OWN))
  1147. return 0;
  1148. udelay(1);
  1149. }
  1150. debug("%s: TX timeout\n", __func__);
  1151. return -ETIMEDOUT;
  1152. }
  1153. static int eqos_recv(struct udevice *dev, int flags, uchar **packetp)
  1154. {
  1155. struct eqos_priv *eqos = dev_get_priv(dev);
  1156. struct eqos_desc *rx_desc;
  1157. int length;
  1158. debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags);
  1159. rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
  1160. if (rx_desc->des3 & EQOS_DESC3_OWN) {
  1161. debug("%s: RX packet not available\n", __func__);
  1162. return -EAGAIN;
  1163. }
  1164. *packetp = eqos->rx_dma_buf +
  1165. (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
  1166. length = rx_desc->des3 & 0x7fff;
  1167. debug("%s: *packetp=%p, length=%d\n", __func__, *packetp, length);
  1168. eqos->config->ops->eqos_inval_buffer(*packetp, length);
  1169. return length;
  1170. }
  1171. static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length)
  1172. {
  1173. struct eqos_priv *eqos = dev_get_priv(dev);
  1174. uchar *packet_expected;
  1175. struct eqos_desc *rx_desc;
  1176. debug("%s(packet=%p, length=%d)\n", __func__, packet, length);
  1177. packet_expected = eqos->rx_dma_buf +
  1178. (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
  1179. if (packet != packet_expected) {
  1180. debug("%s: Unexpected packet (expected %p)\n", __func__,
  1181. packet_expected);
  1182. return -EINVAL;
  1183. }
  1184. rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
  1185. rx_desc->des0 = (u32)(ulong)packet;
  1186. rx_desc->des1 = 0;
  1187. rx_desc->des2 = 0;
  1188. /*
  1189. * Make sure that if HW sees the _OWN write below, it will see all the
  1190. * writes to the rest of the descriptor too.
  1191. */
  1192. mb();
  1193. rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
  1194. eqos->config->ops->eqos_flush_desc(rx_desc);
  1195. writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
  1196. eqos->rx_desc_idx++;
  1197. eqos->rx_desc_idx %= EQOS_DESCRIPTORS_RX;
  1198. return 0;
  1199. }
  1200. static int eqos_probe_resources_core(struct udevice *dev)
  1201. {
  1202. struct eqos_priv *eqos = dev_get_priv(dev);
  1203. int ret;
  1204. debug("%s(dev=%p):\n", __func__, dev);
  1205. eqos->descs = eqos_alloc_descs(EQOS_DESCRIPTORS_TX +
  1206. EQOS_DESCRIPTORS_RX);
  1207. if (!eqos->descs) {
  1208. debug("%s: eqos_alloc_descs() failed\n", __func__);
  1209. ret = -ENOMEM;
  1210. goto err;
  1211. }
  1212. eqos->tx_descs = (struct eqos_desc *)eqos->descs;
  1213. eqos->rx_descs = (eqos->tx_descs + EQOS_DESCRIPTORS_TX);
  1214. debug("%s: tx_descs=%p, rx_descs=%p\n", __func__, eqos->tx_descs,
  1215. eqos->rx_descs);
  1216. eqos->tx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_MAX_PACKET_SIZE);
  1217. if (!eqos->tx_dma_buf) {
  1218. debug("%s: memalign(tx_dma_buf) failed\n", __func__);
  1219. ret = -ENOMEM;
  1220. goto err_free_descs;
  1221. }
  1222. debug("%s: tx_dma_buf=%p\n", __func__, eqos->tx_dma_buf);
  1223. eqos->rx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_RX_BUFFER_SIZE);
  1224. if (!eqos->rx_dma_buf) {
  1225. debug("%s: memalign(rx_dma_buf) failed\n", __func__);
  1226. ret = -ENOMEM;
  1227. goto err_free_tx_dma_buf;
  1228. }
  1229. debug("%s: rx_dma_buf=%p\n", __func__, eqos->rx_dma_buf);
  1230. eqos->rx_pkt = malloc(EQOS_MAX_PACKET_SIZE);
  1231. if (!eqos->rx_pkt) {
  1232. debug("%s: malloc(rx_pkt) failed\n", __func__);
  1233. ret = -ENOMEM;
  1234. goto err_free_rx_dma_buf;
  1235. }
  1236. debug("%s: rx_pkt=%p\n", __func__, eqos->rx_pkt);
  1237. debug("%s: OK\n", __func__);
  1238. return 0;
  1239. err_free_rx_dma_buf:
  1240. free(eqos->rx_dma_buf);
  1241. err_free_tx_dma_buf:
  1242. free(eqos->tx_dma_buf);
  1243. err_free_descs:
  1244. eqos_free_descs(eqos->descs);
  1245. err:
  1246. debug("%s: returns %d\n", __func__, ret);
  1247. return ret;
  1248. }
  1249. static int eqos_remove_resources_core(struct udevice *dev)
  1250. {
  1251. struct eqos_priv *eqos = dev_get_priv(dev);
  1252. debug("%s(dev=%p):\n", __func__, dev);
  1253. free(eqos->rx_pkt);
  1254. free(eqos->rx_dma_buf);
  1255. free(eqos->tx_dma_buf);
  1256. eqos_free_descs(eqos->descs);
  1257. debug("%s: OK\n", __func__);
  1258. return 0;
  1259. }
  1260. static int eqos_probe_resources_tegra186(struct udevice *dev)
  1261. {
  1262. struct eqos_priv *eqos = dev_get_priv(dev);
  1263. int ret;
  1264. debug("%s(dev=%p):\n", __func__, dev);
  1265. ret = reset_get_by_name(dev, "eqos", &eqos->reset_ctl);
  1266. if (ret) {
  1267. pr_err("reset_get_by_name(rst) failed: %d", ret);
  1268. return ret;
  1269. }
  1270. ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
  1271. &eqos->phy_reset_gpio,
  1272. GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
  1273. if (ret) {
  1274. pr_err("gpio_request_by_name(phy reset) failed: %d", ret);
  1275. goto err_free_reset_eqos;
  1276. }
  1277. ret = clk_get_by_name(dev, "slave_bus", &eqos->clk_slave_bus);
  1278. if (ret) {
  1279. pr_err("clk_get_by_name(slave_bus) failed: %d", ret);
  1280. goto err_free_gpio_phy_reset;
  1281. }
  1282. ret = clk_get_by_name(dev, "master_bus", &eqos->clk_master_bus);
  1283. if (ret) {
  1284. pr_err("clk_get_by_name(master_bus) failed: %d", ret);
  1285. goto err_free_clk_slave_bus;
  1286. }
  1287. ret = clk_get_by_name(dev, "rx", &eqos->clk_rx);
  1288. if (ret) {
  1289. pr_err("clk_get_by_name(rx) failed: %d", ret);
  1290. goto err_free_clk_master_bus;
  1291. }
  1292. ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref);
  1293. if (ret) {
  1294. pr_err("clk_get_by_name(ptp_ref) failed: %d", ret);
  1295. goto err_free_clk_rx;
  1296. return ret;
  1297. }
  1298. ret = clk_get_by_name(dev, "tx", &eqos->clk_tx);
  1299. if (ret) {
  1300. pr_err("clk_get_by_name(tx) failed: %d", ret);
  1301. goto err_free_clk_ptp_ref;
  1302. }
  1303. debug("%s: OK\n", __func__);
  1304. return 0;
  1305. err_free_clk_ptp_ref:
  1306. clk_free(&eqos->clk_ptp_ref);
  1307. err_free_clk_rx:
  1308. clk_free(&eqos->clk_rx);
  1309. err_free_clk_master_bus:
  1310. clk_free(&eqos->clk_master_bus);
  1311. err_free_clk_slave_bus:
  1312. clk_free(&eqos->clk_slave_bus);
  1313. err_free_gpio_phy_reset:
  1314. dm_gpio_free(dev, &eqos->phy_reset_gpio);
  1315. err_free_reset_eqos:
  1316. reset_free(&eqos->reset_ctl);
  1317. debug("%s: returns %d\n", __func__, ret);
  1318. return ret;
  1319. }
  1320. /* board-specific Ethernet Interface initializations. */
  1321. __weak int board_interface_eth_init(struct udevice *dev,
  1322. phy_interface_t interface_type)
  1323. {
  1324. return 0;
  1325. }
  1326. static int eqos_probe_resources_stm32(struct udevice *dev)
  1327. {
  1328. struct eqos_priv *eqos = dev_get_priv(dev);
  1329. int ret;
  1330. phy_interface_t interface;
  1331. debug("%s(dev=%p):\n", __func__, dev);
  1332. interface = eqos->config->interface(dev);
  1333. if (interface == PHY_INTERFACE_MODE_NONE) {
  1334. pr_err("Invalid PHY interface\n");
  1335. return -EINVAL;
  1336. }
  1337. ret = board_interface_eth_init(dev, interface);
  1338. if (ret)
  1339. return -EINVAL;
  1340. ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
  1341. if (ret) {
  1342. pr_err("clk_get_by_name(master_bus) failed: %d", ret);
  1343. goto err_probe;
  1344. }
  1345. ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx);
  1346. if (ret) {
  1347. pr_err("clk_get_by_name(rx) failed: %d", ret);
  1348. goto err_free_clk_master_bus;
  1349. }
  1350. ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx);
  1351. if (ret) {
  1352. pr_err("clk_get_by_name(tx) failed: %d", ret);
  1353. goto err_free_clk_rx;
  1354. }
  1355. /* Get ETH_CLK clocks (optional) */
  1356. ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck);
  1357. if (ret)
  1358. pr_warn("No phy clock provided %d", ret);
  1359. debug("%s: OK\n", __func__);
  1360. return 0;
  1361. err_free_clk_rx:
  1362. clk_free(&eqos->clk_rx);
  1363. err_free_clk_master_bus:
  1364. clk_free(&eqos->clk_master_bus);
  1365. err_probe:
  1366. debug("%s: returns %d\n", __func__, ret);
  1367. return ret;
  1368. }
  1369. static phy_interface_t eqos_get_interface_stm32(struct udevice *dev)
  1370. {
  1371. const char *phy_mode;
  1372. phy_interface_t interface = PHY_INTERFACE_MODE_NONE;
  1373. debug("%s(dev=%p):\n", __func__, dev);
  1374. phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
  1375. NULL);
  1376. if (phy_mode)
  1377. interface = phy_get_interface_by_name(phy_mode);
  1378. return interface;
  1379. }
  1380. static phy_interface_t eqos_get_interface_tegra186(struct udevice *dev)
  1381. {
  1382. return PHY_INTERFACE_MODE_MII;
  1383. }
  1384. static int eqos_remove_resources_tegra186(struct udevice *dev)
  1385. {
  1386. struct eqos_priv *eqos = dev_get_priv(dev);
  1387. debug("%s(dev=%p):\n", __func__, dev);
  1388. clk_free(&eqos->clk_tx);
  1389. clk_free(&eqos->clk_ptp_ref);
  1390. clk_free(&eqos->clk_rx);
  1391. clk_free(&eqos->clk_slave_bus);
  1392. clk_free(&eqos->clk_master_bus);
  1393. dm_gpio_free(dev, &eqos->phy_reset_gpio);
  1394. reset_free(&eqos->reset_ctl);
  1395. debug("%s: OK\n", __func__);
  1396. return 0;
  1397. }
  1398. static int eqos_remove_resources_stm32(struct udevice *dev)
  1399. {
  1400. struct eqos_priv *eqos = dev_get_priv(dev);
  1401. debug("%s(dev=%p):\n", __func__, dev);
  1402. clk_free(&eqos->clk_tx);
  1403. clk_free(&eqos->clk_rx);
  1404. clk_free(&eqos->clk_master_bus);
  1405. if (clk_valid(&eqos->clk_ck))
  1406. clk_free(&eqos->clk_ck);
  1407. debug("%s: OK\n", __func__);
  1408. return 0;
  1409. }
  1410. static int eqos_probe(struct udevice *dev)
  1411. {
  1412. struct eqos_priv *eqos = dev_get_priv(dev);
  1413. int ret;
  1414. debug("%s(dev=%p):\n", __func__, dev);
  1415. eqos->dev = dev;
  1416. eqos->config = (void *)dev_get_driver_data(dev);
  1417. eqos->regs = devfdt_get_addr(dev);
  1418. if (eqos->regs == FDT_ADDR_T_NONE) {
  1419. pr_err("devfdt_get_addr() failed");
  1420. return -ENODEV;
  1421. }
  1422. eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE);
  1423. eqos->mtl_regs = (void *)(eqos->regs + EQOS_MTL_REGS_BASE);
  1424. eqos->dma_regs = (void *)(eqos->regs + EQOS_DMA_REGS_BASE);
  1425. eqos->tegra186_regs = (void *)(eqos->regs + EQOS_TEGRA186_REGS_BASE);
  1426. ret = eqos_probe_resources_core(dev);
  1427. if (ret < 0) {
  1428. pr_err("eqos_probe_resources_core() failed: %d", ret);
  1429. return ret;
  1430. }
  1431. ret = eqos->config->ops->eqos_probe_resources(dev);
  1432. if (ret < 0) {
  1433. pr_err("eqos_probe_resources() failed: %d", ret);
  1434. goto err_remove_resources_core;
  1435. }
  1436. eqos->mii = mdio_alloc();
  1437. if (!eqos->mii) {
  1438. pr_err("mdio_alloc() failed");
  1439. ret = -ENOMEM;
  1440. goto err_remove_resources_tegra;
  1441. }
  1442. eqos->mii->read = eqos_mdio_read;
  1443. eqos->mii->write = eqos_mdio_write;
  1444. eqos->mii->priv = eqos;
  1445. strcpy(eqos->mii->name, dev->name);
  1446. ret = mdio_register(eqos->mii);
  1447. if (ret < 0) {
  1448. pr_err("mdio_register() failed: %d", ret);
  1449. goto err_free_mdio;
  1450. }
  1451. debug("%s: OK\n", __func__);
  1452. return 0;
  1453. err_free_mdio:
  1454. mdio_free(eqos->mii);
  1455. err_remove_resources_tegra:
  1456. eqos->config->ops->eqos_remove_resources(dev);
  1457. err_remove_resources_core:
  1458. eqos_remove_resources_core(dev);
  1459. debug("%s: returns %d\n", __func__, ret);
  1460. return ret;
  1461. }
  1462. static int eqos_remove(struct udevice *dev)
  1463. {
  1464. struct eqos_priv *eqos = dev_get_priv(dev);
  1465. debug("%s(dev=%p):\n", __func__, dev);
  1466. mdio_unregister(eqos->mii);
  1467. mdio_free(eqos->mii);
  1468. eqos->config->ops->eqos_remove_resources(dev);
  1469. eqos_probe_resources_core(dev);
  1470. debug("%s: OK\n", __func__);
  1471. return 0;
  1472. }
  1473. static const struct eth_ops eqos_ops = {
  1474. .start = eqos_start,
  1475. .stop = eqos_stop,
  1476. .send = eqos_send,
  1477. .recv = eqos_recv,
  1478. .free_pkt = eqos_free_pkt,
  1479. .write_hwaddr = eqos_write_hwaddr,
  1480. };
  1481. static struct eqos_ops eqos_tegra186_ops = {
  1482. .eqos_inval_desc = eqos_inval_desc_tegra186,
  1483. .eqos_flush_desc = eqos_flush_desc_tegra186,
  1484. .eqos_inval_buffer = eqos_inval_buffer_tegra186,
  1485. .eqos_flush_buffer = eqos_flush_buffer_tegra186,
  1486. .eqos_probe_resources = eqos_probe_resources_tegra186,
  1487. .eqos_remove_resources = eqos_remove_resources_tegra186,
  1488. .eqos_stop_resets = eqos_stop_resets_tegra186,
  1489. .eqos_start_resets = eqos_start_resets_tegra186,
  1490. .eqos_stop_clks = eqos_stop_clks_tegra186,
  1491. .eqos_start_clks = eqos_start_clks_tegra186,
  1492. .eqos_calibrate_pads = eqos_calibrate_pads_tegra186,
  1493. .eqos_disable_calibration = eqos_disable_calibration_tegra186,
  1494. .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_tegra186,
  1495. .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186
  1496. };
  1497. static const struct eqos_config eqos_tegra186_config = {
  1498. .reg_access_always_ok = false,
  1499. .mdio_wait = 10,
  1500. .swr_wait = 10,
  1501. .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
  1502. .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_20_35,
  1503. .interface = eqos_get_interface_tegra186,
  1504. .ops = &eqos_tegra186_ops
  1505. };
  1506. static struct eqos_ops eqos_stm32_ops = {
  1507. .eqos_inval_desc = eqos_inval_desc_stm32,
  1508. .eqos_flush_desc = eqos_flush_desc_stm32,
  1509. .eqos_inval_buffer = eqos_inval_buffer_stm32,
  1510. .eqos_flush_buffer = eqos_flush_buffer_stm32,
  1511. .eqos_probe_resources = eqos_probe_resources_stm32,
  1512. .eqos_remove_resources = eqos_remove_resources_stm32,
  1513. .eqos_stop_resets = eqos_stop_resets_stm32,
  1514. .eqos_start_resets = eqos_start_resets_stm32,
  1515. .eqos_stop_clks = eqos_stop_clks_stm32,
  1516. .eqos_start_clks = eqos_start_clks_stm32,
  1517. .eqos_calibrate_pads = eqos_calibrate_pads_stm32,
  1518. .eqos_disable_calibration = eqos_disable_calibration_stm32,
  1519. .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_stm32,
  1520. .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32
  1521. };
  1522. static const struct eqos_config eqos_stm32_config = {
  1523. .reg_access_always_ok = false,
  1524. .mdio_wait = 10000,
  1525. .swr_wait = 50,
  1526. .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV,
  1527. .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
  1528. .interface = eqos_get_interface_stm32,
  1529. .ops = &eqos_stm32_ops
  1530. };
  1531. static const struct udevice_id eqos_ids[] = {
  1532. {
  1533. .compatible = "nvidia,tegra186-eqos",
  1534. .data = (ulong)&eqos_tegra186_config
  1535. },
  1536. {
  1537. .compatible = "snps,dwmac-4.20a",
  1538. .data = (ulong)&eqos_stm32_config
  1539. },
  1540. { }
  1541. };
  1542. U_BOOT_DRIVER(eth_eqos) = {
  1543. .name = "eth_eqos",
  1544. .id = UCLASS_ETH,
  1545. .of_match = eqos_ids,
  1546. .probe = eqos_probe,
  1547. .remove = eqos_remove,
  1548. .ops = &eqos_ops,
  1549. .priv_auto_alloc_size = sizeof(struct eqos_priv),
  1550. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  1551. };