init.S 4.1 KB

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  1. /*
  2. * (C) Copyright 2008
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <ppc_asm.tmpl>
  24. #include <config.h>
  25. #include <asm-ppc/mmu.h>
  26. /**************************************************************************
  27. * TLB TABLE
  28. *
  29. * This table is used by the cpu boot code to setup the initial tlb
  30. * entries. Rather than make broad assumptions in the cpu source tree,
  31. * this table lets each board set things up however they like.
  32. *
  33. * Pointer to the table is returned in r1
  34. *
  35. *************************************************************************/
  36. .section .bootpg,"ax"
  37. .globl tlbtab
  38. tlbtab:
  39. tlbtab_start
  40. /*
  41. * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
  42. * use the speed up boot process. It is patched after relocation to
  43. * enable SA_I
  44. */
  45. #ifndef CONFIG_NAND_SPL
  46. tlbentry(CFG_BOOT_BASE_ADDR, SZ_16M, CFG_BOOT_BASE_ADDR, 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */
  47. #else
  48. tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 4, AC_R|AC_W|AC_X|SA_G)
  49. tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
  50. tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
  51. #endif
  52. /*
  53. * TLB entries for SDRAM are not needed on this platform.
  54. * They are dynamically generated in the SPD DDR(2) detection
  55. * routine.
  56. */
  57. #ifdef CFG_INIT_RAM_DCACHE
  58. /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
  59. tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
  60. #endif
  61. tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
  62. tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
  63. tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
  64. tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
  65. tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
  66. tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
  67. tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
  68. /* PCIe UTL register */
  69. tlbentry(CFG_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_R|AC_W|SA_G|SA_I)
  70. /* TLB-entry for NAND */
  71. tlbentry(CFG_NAND_ADDR, SZ_16M, CFG_NAND_ADDR, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
  72. /* TLB-entry for CPLD */
  73. tlbentry(CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I)
  74. /* TLB-entry for OCM */
  75. tlbentry(CFG_OCM_BASE, SZ_16K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I)
  76. /* TLB-entry for Local Configuration registers => peripherals */
  77. tlbentry(CFG_LOCAL_CONF_REGS, SZ_16M, CFG_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
  78. /* AHB: Internal USB Peripherals (USB, SATA) */
  79. tlbentry(CFG_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
  80. tlbtab_end
  81. #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  82. /*
  83. * For NAND booting the first TLB has to be reconfigured to full size
  84. * and with caching disabled after running from RAM!
  85. */
  86. #define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M)
  87. #define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 1)
  88. #define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
  89. .globl reconfig_tlb0
  90. reconfig_tlb0:
  91. sync
  92. isync
  93. addi r4,r0,0x0000 /* TLB entry #0 */
  94. lis r5,TLB00@h
  95. ori r5,r5,TLB00@l
  96. tlbwe r5,r4,0x0000 /* Save it out */
  97. lis r5,TLB01@h
  98. ori r5,r5,TLB01@l
  99. tlbwe r5,r4,0x0001 /* Save it out */
  100. lis r5,TLB02@h
  101. ori r5,r5,TLB02@l
  102. tlbwe r5,r4,0x0002 /* Save it out */
  103. sync
  104. isync
  105. blr
  106. #endif