evm.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2004-2011
  4. * Texas Instruments, <www.ti.com>
  5. *
  6. * Author :
  7. * Manikandan Pillai <mani.pillai@ti.com>
  8. *
  9. * Derived from Beagle Board and 3430 SDP code by
  10. * Richard Woodruff <r-woodruff2@ti.com>
  11. * Syed Mohammed Khasim <khasim@ti.com>
  12. */
  13. #include <common.h>
  14. #include <dm.h>
  15. #include <env.h>
  16. #include <init.h>
  17. #include <net.h>
  18. #include <ns16550.h>
  19. #include <serial.h>
  20. #include <asm/io.h>
  21. #include <asm/arch/mem.h>
  22. #include <asm/arch/mux.h>
  23. #include <asm/arch/sys_proto.h>
  24. #include <asm/arch/mmc_host_def.h>
  25. #include <asm/gpio.h>
  26. #include <twl4030.h>
  27. #include <asm/mach-types.h>
  28. #include <linux/delay.h>
  29. #include <linux/mtd/rawnand.h>
  30. #include "evm.h"
  31. #define OMAP3EVM_GPIO_ETH_RST_GEN1 64
  32. #define OMAP3EVM_GPIO_ETH_RST_GEN2 7
  33. #define CONFIG_SMC911X_BASE 0x2C000000
  34. DECLARE_GLOBAL_DATA_PTR;
  35. static u32 omap3_evm_version;
  36. u32 get_omap3_evm_rev(void)
  37. {
  38. return omap3_evm_version;
  39. }
  40. static void omap3_evm_get_revision(void)
  41. {
  42. #if defined(CONFIG_SMC911X)
  43. /*
  44. * Board revision can be ascertained only by identifying
  45. * the Ethernet chipset.
  46. */
  47. unsigned int smsc_id;
  48. /* Ethernet PHY ID is stored at ID_REV register */
  49. smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000;
  50. printf("Read back SMSC id 0x%x\n", smsc_id);
  51. switch (smsc_id) {
  52. /* SMSC9115 chipset */
  53. case 0x01150000:
  54. omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
  55. break;
  56. /* SMSC 9220 chipset */
  57. case 0x92200000:
  58. default:
  59. omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
  60. }
  61. #else /* !CONFIG_SMC911X */
  62. #if defined(CONFIG_STATIC_BOARD_REV)
  63. /* Look for static defintion of the board revision */
  64. omap3_evm_version = CONFIG_STATIC_BOARD_REV;
  65. #else
  66. /* Fallback to the default above */
  67. omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
  68. #endif /* CONFIG_STATIC_BOARD_REV */
  69. #endif /* CONFIG_SMC911X */
  70. }
  71. #if defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)
  72. /* MUSB port on OMAP3EVM Rev >= E requires extvbus programming. */
  73. u8 omap3_evm_need_extvbus(void)
  74. {
  75. u8 retval = 0;
  76. if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
  77. retval = 1;
  78. return retval;
  79. }
  80. #endif /* CONFIG_USB_MUSB_{GADGET,HOST} */
  81. /*
  82. * Routine: board_init
  83. * Description: Early hardware init.
  84. */
  85. int board_init(void)
  86. {
  87. gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
  88. /* board id for Linux */
  89. gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
  90. /* boot param addr */
  91. gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
  92. return 0;
  93. }
  94. #if defined(CONFIG_SPL_OS_BOOT)
  95. int spl_start_uboot(void)
  96. {
  97. /* break into full u-boot on 'c' */
  98. if (serial_tstc() && serial_getc() == 'c')
  99. return 1;
  100. return 0;
  101. }
  102. #endif /* CONFIG_SPL_OS_BOOT */
  103. #if defined(CONFIG_SPL_BUILD)
  104. /*
  105. * Routine: get_board_mem_timings
  106. * Description: If we use SPL then there is no x-loader nor config header
  107. * so we have to setup the DDR timings ourself on the first bank. This
  108. * provides the timing values back to the function that configures
  109. * the memory.
  110. */
  111. void get_board_mem_timings(struct board_sdrc_timings *timings)
  112. {
  113. int pop_mfr, pop_id;
  114. /*
  115. * We need to identify what PoP memory is on the board so that
  116. * we know what timings to use. To map the ID values please see
  117. * nand_ids.c
  118. */
  119. identify_nand_chip(&pop_mfr, &pop_id);
  120. if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) {
  121. /* 256MB DDR */
  122. timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
  123. timings->ctrla = HYNIX_V_ACTIMA_200;
  124. timings->ctrlb = HYNIX_V_ACTIMB_200;
  125. } else {
  126. /* 128MB DDR */
  127. timings->mcfg = MICRON_V_MCFG_165(128 << 20);
  128. timings->ctrla = MICRON_V_ACTIMA_165;
  129. timings->ctrlb = MICRON_V_ACTIMB_165;
  130. }
  131. timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
  132. timings->mr = MICRON_V_MR_165;
  133. }
  134. #endif /* CONFIG_SPL_BUILD */
  135. /*
  136. * Routine: misc_init_r
  137. * Description: Init ethernet (done here so udelay works)
  138. */
  139. int misc_init_r(void)
  140. {
  141. twl4030_power_init();
  142. #if defined(CONFIG_SMC911X)
  143. setup_net_chip();
  144. #endif
  145. omap3_evm_get_revision();
  146. #if defined(CONFIG_SMC911X)
  147. reset_net_chip();
  148. #endif
  149. omap_die_id_display();
  150. #if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET) && \
  151. !defined(CONFIG_SMC911X)
  152. omap_die_id_usbethaddr();
  153. #endif
  154. return 0;
  155. }
  156. /*
  157. * Routine: set_muxconf_regs
  158. * Description: Setting up the configuration Mux registers specific to the
  159. * hardware. Many pins need to be moved from protect to primary
  160. * mode.
  161. */
  162. void set_muxconf_regs(void)
  163. {
  164. MUX_EVM();
  165. }
  166. #if defined(CONFIG_SMC911X)
  167. /*
  168. * Routine: setup_net_chip
  169. * Description: Setting up the configuration GPMC registers specific to the
  170. * Ethernet hardware.
  171. */
  172. static void setup_net_chip(void)
  173. {
  174. struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
  175. /* Configure GPMC registers */
  176. writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
  177. writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
  178. writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
  179. writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
  180. writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
  181. writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
  182. writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
  183. /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
  184. writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
  185. /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
  186. writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
  187. /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
  188. writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
  189. &ctrl_base->gpmc_nadv_ale);
  190. }
  191. /**
  192. * Reset the ethernet chip.
  193. */
  194. static void reset_net_chip(void)
  195. {
  196. int ret;
  197. int rst_gpio;
  198. if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1) {
  199. rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN1;
  200. } else {
  201. rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN2;
  202. }
  203. ret = gpio_request(rst_gpio, "");
  204. if (ret < 0) {
  205. printf("Unable to get GPIO %d\n", rst_gpio);
  206. return ;
  207. }
  208. /* Configure as output */
  209. gpio_direction_output(rst_gpio, 0);
  210. /* Send a pulse on the GPIO pin */
  211. gpio_set_value(rst_gpio, 1);
  212. udelay(1);
  213. gpio_set_value(rst_gpio, 0);
  214. udelay(1);
  215. gpio_set_value(rst_gpio, 1);
  216. }
  217. #endif /* CONFIG_SMC911X */
  218. #if defined(CONFIG_MMC)
  219. void board_mmc_power_init(void)
  220. {
  221. twl4030_power_mmc_init(0);
  222. }
  223. #endif /* CONFIG_MMC */