p1_p2_rdb_pc.c 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <env.h>
  8. #include <hwconfig.h>
  9. #include <init.h>
  10. #include <pci.h>
  11. #include <i2c.h>
  12. #include <asm/processor.h>
  13. #include <asm/mmu.h>
  14. #include <asm/cache.h>
  15. #include <asm/immap_85xx.h>
  16. #include <asm/fsl_pci.h>
  17. #include <fsl_ddr_sdram.h>
  18. #include <asm/io.h>
  19. #include <asm/fsl_law.h>
  20. #include <asm/fsl_lbc.h>
  21. #include <asm/mp.h>
  22. #include <miiphy.h>
  23. #include <linux/libfdt.h>
  24. #include <fdt_support.h>
  25. #include <fsl_mdio.h>
  26. #include <tsec.h>
  27. #include <vsc7385.h>
  28. #include <ioports.h>
  29. #include <asm/fsl_serdes.h>
  30. #include <netdev.h>
  31. #ifdef CONFIG_QE
  32. #define GPIO_GETH_SW_PORT 1
  33. #define GPIO_GETH_SW_PIN 29
  34. #define GPIO_GETH_SW_DATA (1 << (31 - GPIO_GETH_SW_PIN))
  35. #define GPIO_SLIC_PORT 1
  36. #define GPIO_SLIC_PIN 30
  37. #define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN))
  38. #if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
  39. #define GPIO_DDR_RST_PORT 1
  40. #define GPIO_DDR_RST_PIN 8
  41. #define GPIO_DDR_RST_DATA (1 << (31 - GPIO_DDR_RST_PIN))
  42. #define GPIO_2BIT_MASK (0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2))
  43. #endif
  44. #if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
  45. #define PCA_IOPORT_I2C_ADDR 0x23
  46. #define PCA_IOPORT_OUTPUT_CMD 0x2
  47. #define PCA_IOPORT_CFG_CMD 0x6
  48. #define PCA_IOPORT_QE_PIN_ENABLE 0xf8
  49. #define PCA_IOPORT_QE_TDM_ENABLE 0xf6
  50. #endif
  51. const qe_iop_conf_t qe_iop_conf_tab[] = {
  52. /* GPIO */
  53. {1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */
  54. #if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
  55. {1, 8, 1, 1, 0}, /* GPIO10/PB8 - DDR_RST */
  56. #endif
  57. {0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */
  58. {GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0}, /* RST_GETH_SW_N */
  59. {GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0}, /* RST_SLIC_N */
  60. #ifdef CONFIG_TARGET_P1025RDB
  61. /* QE_MUX_MDC */
  62. {1, 19, 1, 0, 1}, /* QE_MUX_MDC */
  63. /* QE_MUX_MDIO */
  64. {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
  65. /* UCC_1_MII */
  66. {0, 23, 2, 0, 2}, /* CLK12 */
  67. {0, 24, 2, 0, 1}, /* CLK9 */
  68. {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
  69. {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
  70. {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
  71. {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
  72. {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
  73. {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
  74. {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
  75. {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
  76. {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
  77. {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
  78. {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
  79. {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
  80. {0, 17, 2, 0, 2}, /* ENET1_CRS */
  81. {0, 16, 2, 0, 2}, /* ENET1_COL */
  82. /* UCC_5_RMII */
  83. {1, 11, 2, 0, 1}, /* CLK13 */
  84. {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
  85. {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
  86. {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
  87. {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
  88. {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
  89. {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
  90. {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
  91. #endif
  92. {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
  93. };
  94. #endif
  95. struct cpld_data {
  96. u8 cpld_rev_major;
  97. u8 pcba_rev;
  98. u8 wd_cfg;
  99. u8 rst_bps_sw;
  100. u8 load_default_n;
  101. u8 rst_bps_wd;
  102. u8 bypass_enable;
  103. u8 bps_led;
  104. u8 status_led; /* offset: 0x8 */
  105. u8 fxo_led; /* offset: 0x9 */
  106. u8 fxs_led; /* offset: 0xa */
  107. u8 rev4[2];
  108. u8 system_rst; /* offset: 0xd */
  109. u8 bps_out;
  110. u8 rev5[3];
  111. u8 cpld_rev_minor;
  112. };
  113. #define CPLD_WD_CFG 0x03
  114. #define CPLD_RST_BSW 0x00
  115. #define CPLD_RST_BWD 0x00
  116. #define CPLD_BYPASS_EN 0x03
  117. #define CPLD_STATUS_LED 0x01
  118. #define CPLD_FXO_LED 0x01
  119. #define CPLD_FXS_LED 0x0F
  120. #define CPLD_SYS_RST 0x00
  121. void board_cpld_init(void)
  122. {
  123. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  124. out_8(&cpld_data->wd_cfg, CPLD_WD_CFG);
  125. out_8(&cpld_data->status_led, CPLD_STATUS_LED);
  126. out_8(&cpld_data->fxo_led, CPLD_FXO_LED);
  127. out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
  128. out_8(&cpld_data->system_rst, CPLD_SYS_RST);
  129. }
  130. void board_gpio_init(void)
  131. {
  132. #ifdef CONFIG_QE
  133. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  134. par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
  135. #if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
  136. /* reset DDR3 */
  137. setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
  138. udelay(1000);
  139. clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
  140. udelay(1000);
  141. setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
  142. /* disable CE_PB8 */
  143. clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdir1, GPIO_2BIT_MASK);
  144. #endif
  145. /* Enable VSC7385 switch */
  146. setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA);
  147. /* Enable SLIC */
  148. setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA);
  149. #else
  150. ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
  151. /*
  152. * GPIO10 DDR Reset, open drain
  153. * GPIO7 LOAD_DEFAULT_N Input
  154. * GPIO11 WDI (watchdog input)
  155. * GPIO12 Ethernet Switch Reset
  156. * GPIO13 SLIC Reset
  157. */
  158. setbits_be32(&pgpio->gpdir, 0x02130000);
  159. #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
  160. /* init DDR3 reset signal */
  161. setbits_be32(&pgpio->gpdir, 0x00200000);
  162. setbits_be32(&pgpio->gpodr, 0x00200000);
  163. clrbits_be32(&pgpio->gpdat, 0x00200000);
  164. udelay(1000);
  165. setbits_be32(&pgpio->gpdat, 0x00200000);
  166. udelay(1000);
  167. clrbits_be32(&pgpio->gpdir, 0x00200000);
  168. #endif
  169. #ifdef CONFIG_VSC7385_ENET
  170. /* reset VSC7385 Switch */
  171. setbits_be32(&pgpio->gpdir, 0x00080000);
  172. setbits_be32(&pgpio->gpdat, 0x00080000);
  173. #endif
  174. #ifdef CONFIG_SLIC
  175. /* reset SLIC */
  176. setbits_be32(&pgpio->gpdir, 0x00040000);
  177. setbits_be32(&pgpio->gpdat, 0x00040000);
  178. #endif
  179. #endif
  180. }
  181. int board_early_init_f(void)
  182. {
  183. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  184. setbits_be32(&gur->pmuxcr,
  185. (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
  186. clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV);
  187. clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
  188. setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA);
  189. board_gpio_init();
  190. board_cpld_init();
  191. return 0;
  192. }
  193. int checkboard(void)
  194. {
  195. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  196. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  197. u8 in, out, io_config, val;
  198. printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME,
  199. in_8(&cpld_data->cpld_rev_major) & 0x0F,
  200. in_8(&cpld_data->cpld_rev_minor) & 0x0F,
  201. in_8(&cpld_data->pcba_rev) & 0x0F);
  202. /* Initialize i2c early for rom_loc and flash bank information */
  203. i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
  204. if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
  205. i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
  206. i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
  207. printf("Error reading i2c boot information!\n");
  208. return 0; /* Don't want to hang() on this error */
  209. }
  210. val = (in & io_config) | (out & (~io_config));
  211. puts("rom_loc: ");
  212. if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
  213. puts("sd");
  214. #ifdef __SW_BOOT_SPI
  215. } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) {
  216. puts("spi");
  217. #endif
  218. #ifdef __SW_BOOT_NAND
  219. } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_NAND) {
  220. puts("nand");
  221. #endif
  222. #ifdef __SW_BOOT_PCIE
  223. } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_PCIE) {
  224. puts("pcie");
  225. #endif
  226. } else {
  227. if (val & 0x2)
  228. puts("nor lower bank");
  229. else
  230. puts("nor upper bank");
  231. }
  232. puts("\n");
  233. if (val & 0x1) {
  234. setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
  235. puts("SD/MMC : 8-bit Mode\n");
  236. puts("eSPI : Disabled\n");
  237. } else {
  238. puts("SD/MMC : 4-bit Mode\n");
  239. puts("eSPI : Enabled\n");
  240. }
  241. return 0;
  242. }
  243. #if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
  244. void pci_init_board(void)
  245. {
  246. fsl_pcie_init_board(0);
  247. }
  248. #endif
  249. int board_early_init_r(void)
  250. {
  251. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  252. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  253. /*
  254. * Remap Boot flash region to caching-inhibited
  255. * so that flash can be erased properly.
  256. */
  257. /* Flush d-cache and invalidate i-cache of any FLASH data */
  258. flush_dcache();
  259. invalidate_icache();
  260. if (flash_esel == -1) {
  261. /* very unlikely unless something is messed up */
  262. puts("Error: Could not find TLB for FLASH BASE\n");
  263. flash_esel = 2; /* give our best effort to continue */
  264. } else {
  265. /* invalidate existing TLB entry for flash */
  266. disable_tlb(flash_esel);
  267. }
  268. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
  269. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
  270. 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
  271. return 0;
  272. }
  273. int board_eth_init(bd_t *bis)
  274. {
  275. struct fsl_pq_mdio_info mdio_info;
  276. struct tsec_info_struct tsec_info[4];
  277. ccsr_gur_t *gur __attribute__((unused)) =
  278. (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  279. int num = 0;
  280. #ifdef CONFIG_VSC7385_ENET
  281. char *tmp;
  282. unsigned int vscfw_addr;
  283. #endif
  284. #ifdef CONFIG_TSEC1
  285. SET_STD_TSEC_INFO(tsec_info[num], 1);
  286. num++;
  287. #endif
  288. #ifdef CONFIG_TSEC2
  289. SET_STD_TSEC_INFO(tsec_info[num], 2);
  290. if (is_serdes_configured(SGMII_TSEC2)) {
  291. printf("eTSEC2 is in sgmii mode.\n");
  292. tsec_info[num].flags |= TSEC_SGMII;
  293. }
  294. num++;
  295. #endif
  296. #ifdef CONFIG_TSEC3
  297. SET_STD_TSEC_INFO(tsec_info[num], 3);
  298. num++;
  299. #endif
  300. if (!num) {
  301. printf("No TSECs initialized\n");
  302. return 0;
  303. }
  304. #ifdef CONFIG_VSC7385_ENET
  305. /* If a VSC7385 microcode image is present, then upload it. */
  306. tmp = env_get("vscfw_addr");
  307. if (tmp) {
  308. vscfw_addr = simple_strtoul(tmp, NULL, 16);
  309. printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
  310. if (vsc7385_upload_firmware((void *) vscfw_addr,
  311. CONFIG_VSC7385_IMAGE_SIZE))
  312. puts("Failure uploading VSC7385 microcode.\n");
  313. } else
  314. puts("No address specified for VSC7385 microcode.\n");
  315. #endif
  316. mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1);
  317. mdio_info.name = DEFAULT_MII_NAME;
  318. fsl_pq_mdio_init(bis, &mdio_info);
  319. tsec_eth_init(bis, tsec_info, num);
  320. #if defined(CONFIG_UEC_ETH)
  321. /* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */
  322. setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0);
  323. setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3);
  324. uec_standard_init(bis);
  325. #endif
  326. return pci_eth_init(bis);
  327. }
  328. #if defined(CONFIG_QE) && \
  329. (defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB))
  330. static void fdt_board_fixup_qe_pins(void *blob)
  331. {
  332. unsigned int oldbus;
  333. u8 val8;
  334. int node;
  335. fsl_lbc_t *lbc = LBC_BASE_ADDR;
  336. if (hwconfig("qe")) {
  337. /* For QE and eLBC pins multiplexing,
  338. * there is a PCA9555 device on P1025RDB.
  339. * It control the multiplex pins' functions,
  340. * and setting the PCA9555 can switch the
  341. * function between QE and eLBC.
  342. */
  343. oldbus = i2c_get_bus_num();
  344. i2c_set_bus_num(0);
  345. if (hwconfig("tdm"))
  346. val8 = PCA_IOPORT_QE_TDM_ENABLE;
  347. else
  348. val8 = PCA_IOPORT_QE_PIN_ENABLE;
  349. i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_CFG_CMD,
  350. 1, &val8, 1);
  351. i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_OUTPUT_CMD,
  352. 1, &val8, 1);
  353. i2c_set_bus_num(oldbus);
  354. /* if run QE TDM, Set ABSWP to implement
  355. * conversion of addresses in the eLBC.
  356. */
  357. if (hwconfig("tdm")) {
  358. set_lbc_or(2, CONFIG_PMC_OR_PRELIM);
  359. set_lbc_br(2, CONFIG_PMC_BR_PRELIM);
  360. setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
  361. }
  362. } else {
  363. node = fdt_path_offset(blob, "/qe");
  364. if (node >= 0)
  365. fdt_del_node(blob, node);
  366. }
  367. return;
  368. }
  369. #endif
  370. #ifdef CONFIG_OF_BOARD_SETUP
  371. int ft_board_setup(void *blob, bd_t *bd)
  372. {
  373. phys_addr_t base;
  374. phys_size_t size;
  375. #if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
  376. const char *soc_usb_compat = "fsl-usb2-dr";
  377. int usb_err, usb1_off, usb2_off;
  378. #endif
  379. #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
  380. int err;
  381. #endif
  382. ft_cpu_setup(blob, bd);
  383. base = env_get_bootm_low();
  384. size = env_get_bootm_size();
  385. fdt_fixup_memory(blob, (u64)base, (u64)size);
  386. #if !defined(CONFIG_DM_PCI)
  387. FT_FSL_PCI_SETUP;
  388. #endif
  389. #ifdef CONFIG_QE
  390. do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
  391. sizeof("okay"), 0);
  392. #if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
  393. fdt_board_fixup_qe_pins(blob);
  394. #endif
  395. #endif
  396. #if defined(CONFIG_HAS_FSL_DR_USB)
  397. fsl_fdt_fixup_dr_usb(blob, bd);
  398. #endif
  399. #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
  400. /* Delete eLBC node as it is muxed with USB2 controller */
  401. if (hwconfig("usb2")) {
  402. const char *soc_elbc_compat = "fsl,p1020-elbc";
  403. int off = fdt_node_offset_by_compatible(blob, -1,
  404. soc_elbc_compat);
  405. if (off < 0) {
  406. printf("WARNING: could not find compatible node %s\n",
  407. soc_elbc_compat);
  408. return off;
  409. }
  410. err = fdt_del_node(blob, off);
  411. if (err < 0) {
  412. printf("WARNING: could not remove %s\n",
  413. soc_elbc_compat);
  414. return err;
  415. }
  416. return 0;
  417. }
  418. #endif
  419. #if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
  420. /* Delete USB2 node as it is muxed with eLBC */
  421. usb1_off = fdt_node_offset_by_compatible(blob, -1,
  422. soc_usb_compat);
  423. if (usb1_off < 0) {
  424. printf("WARNING: could not find compatible node %s\n",
  425. soc_usb_compat);
  426. return usb1_off;
  427. }
  428. usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
  429. soc_usb_compat);
  430. if (usb2_off < 0) {
  431. printf("WARNING: could not find compatible node %s\n",
  432. soc_usb_compat);
  433. return usb2_off;
  434. }
  435. usb_err = fdt_del_node(blob, usb2_off);
  436. if (usb_err < 0) {
  437. printf("WARNING: could not remove %s\n", soc_usb_compat);
  438. return usb_err;
  439. }
  440. #endif
  441. return 0;
  442. }
  443. #endif