p1010rdb.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <init.h>
  7. #include <asm/processor.h>
  8. #include <asm/mmu.h>
  9. #include <asm/cache.h>
  10. #include <asm/immap_85xx.h>
  11. #include <asm/io.h>
  12. #include <env.h>
  13. #include <miiphy.h>
  14. #include <linux/libfdt.h>
  15. #include <fdt_support.h>
  16. #include <fsl_mdio.h>
  17. #include <tsec.h>
  18. #include <mmc.h>
  19. #include <netdev.h>
  20. #include <pci.h>
  21. #include <asm/fsl_serdes.h>
  22. #include <fsl_ifc.h>
  23. #include <asm/fsl_pci.h>
  24. #include <hwconfig.h>
  25. #include <i2c.h>
  26. DECLARE_GLOBAL_DATA_PTR;
  27. #define GPIO4_PCIE_RESET_SET 0x08000000
  28. #define MUX_CPLD_CAN_UART 0x00
  29. #define MUX_CPLD_TDM 0x01
  30. #define MUX_CPLD_SPICS0_FLASH 0x00
  31. #define MUX_CPLD_SPICS0_SLIC 0x02
  32. #define PMUXCR1_IFC_MASK 0x00ffff00
  33. #define PMUXCR1_SDHC_MASK 0x00fff000
  34. #define PMUXCR1_SDHC_ENABLE 0x00555000
  35. enum {
  36. MUX_TYPE_IFC,
  37. MUX_TYPE_SDHC,
  38. MUX_TYPE_SPIFLASH,
  39. MUX_TYPE_TDM,
  40. MUX_TYPE_CAN,
  41. MUX_TYPE_CS0_NOR,
  42. MUX_TYPE_CS0_NAND,
  43. };
  44. enum {
  45. I2C_READ_BANK,
  46. I2C_READ_PCB_VER,
  47. };
  48. static uint sd_ifc_mux;
  49. struct cpld_data {
  50. u8 cpld_ver; /* cpld revision */
  51. #if defined(CONFIG_TARGET_P1010RDB_PA)
  52. u8 pcba_ver; /* pcb revision number */
  53. u8 twindie_ddr3;
  54. u8 res1[6];
  55. u8 bank_sel; /* NOR Flash bank */
  56. u8 res2[5];
  57. u8 usb2_sel;
  58. u8 res3[1];
  59. u8 porsw_sel;
  60. u8 tdm_can_sel;
  61. u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */
  62. u8 por0; /* POR Options */
  63. u8 por1; /* POR Options */
  64. u8 por2; /* POR Options */
  65. u8 por3; /* POR Options */
  66. #elif defined(CONFIG_TARGET_P1010RDB_PB)
  67. u8 rom_loc;
  68. #endif
  69. };
  70. int board_early_init_f(void)
  71. {
  72. ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
  73. struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
  74. /* Clock configuration to access CPLD using IFC(GPCM) */
  75. setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
  76. /*
  77. * Reset PCIe slots via GPIO4
  78. */
  79. setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
  80. setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);
  81. return 0;
  82. }
  83. int board_early_init_r(void)
  84. {
  85. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  86. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  87. /*
  88. * Remap Boot flash region to caching-inhibited
  89. * so that flash can be erased properly.
  90. */
  91. /* Flush d-cache and invalidate i-cache of any FLASH data */
  92. flush_dcache();
  93. invalidate_icache();
  94. if (flash_esel == -1) {
  95. /* very unlikely unless something is messed up */
  96. puts("Error: Could not find TLB for FLASH BASE\n");
  97. flash_esel = 2; /* give our best effort to continue */
  98. } else {
  99. /* invalidate existing TLB entry for flash */
  100. disable_tlb(flash_esel);
  101. }
  102. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  103. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  104. 0, flash_esel, BOOKE_PAGESZ_16M, 1);
  105. set_tlb(1, flashbase + 0x1000000,
  106. CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
  107. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  108. 0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
  109. return 0;
  110. }
  111. #ifdef CONFIG_PCI
  112. void pci_init_board(void)
  113. {
  114. fsl_pcie_init_board(0);
  115. }
  116. #endif /* ifdef CONFIG_PCI */
  117. int config_board_mux(int ctrl_type)
  118. {
  119. ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  120. u8 tmp;
  121. #if defined(CONFIG_TARGET_P1010RDB_PA)
  122. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  123. switch (ctrl_type) {
  124. case MUX_TYPE_IFC:
  125. i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
  126. tmp = 0xf0;
  127. i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
  128. tmp = 0x01;
  129. i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
  130. sd_ifc_mux = MUX_TYPE_IFC;
  131. clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
  132. break;
  133. case MUX_TYPE_SDHC:
  134. i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
  135. tmp = 0xf0;
  136. i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
  137. tmp = 0x05;
  138. i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
  139. sd_ifc_mux = MUX_TYPE_SDHC;
  140. clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
  141. PMUXCR1_SDHC_ENABLE);
  142. break;
  143. case MUX_TYPE_SPIFLASH:
  144. out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
  145. break;
  146. case MUX_TYPE_TDM:
  147. out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
  148. out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
  149. break;
  150. case MUX_TYPE_CAN:
  151. out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
  152. break;
  153. default:
  154. break;
  155. }
  156. #elif defined(CONFIG_TARGET_P1010RDB_PB)
  157. uint orig_bus = i2c_get_bus_num();
  158. i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
  159. switch (ctrl_type) {
  160. case MUX_TYPE_IFC:
  161. i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
  162. clrbits_8(&tmp, 0x04);
  163. i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
  164. i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  165. clrbits_8(&tmp, 0x04);
  166. i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  167. sd_ifc_mux = MUX_TYPE_IFC;
  168. clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
  169. break;
  170. case MUX_TYPE_SDHC:
  171. i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
  172. setbits_8(&tmp, 0x04);
  173. i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
  174. i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  175. clrbits_8(&tmp, 0x04);
  176. i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  177. sd_ifc_mux = MUX_TYPE_SDHC;
  178. clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
  179. PMUXCR1_SDHC_ENABLE);
  180. break;
  181. case MUX_TYPE_SPIFLASH:
  182. i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
  183. clrbits_8(&tmp, 0x80);
  184. i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
  185. i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  186. clrbits_8(&tmp, 0x80);
  187. i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  188. break;
  189. case MUX_TYPE_TDM:
  190. i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
  191. setbits_8(&tmp, 0x82);
  192. i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
  193. i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  194. clrbits_8(&tmp, 0x82);
  195. i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  196. break;
  197. case MUX_TYPE_CAN:
  198. i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
  199. clrbits_8(&tmp, 0x02);
  200. i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
  201. i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  202. clrbits_8(&tmp, 0x02);
  203. i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  204. break;
  205. case MUX_TYPE_CS0_NOR:
  206. i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
  207. clrbits_8(&tmp, 0x08);
  208. i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
  209. i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  210. clrbits_8(&tmp, 0x08);
  211. i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  212. break;
  213. case MUX_TYPE_CS0_NAND:
  214. i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
  215. setbits_8(&tmp, 0x08);
  216. i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
  217. i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  218. clrbits_8(&tmp, 0x08);
  219. i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
  220. break;
  221. default:
  222. break;
  223. }
  224. i2c_set_bus_num(orig_bus);
  225. #endif
  226. return 0;
  227. }
  228. #ifdef CONFIG_TARGET_P1010RDB_PB
  229. int i2c_pca9557_read(int type)
  230. {
  231. u8 val;
  232. i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
  233. i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);
  234. switch (type) {
  235. case I2C_READ_BANK:
  236. val = (val & 0x10) >> 4;
  237. break;
  238. case I2C_READ_PCB_VER:
  239. val = ((val & 0x60) >> 5) + 1;
  240. break;
  241. default:
  242. break;
  243. }
  244. return val;
  245. }
  246. #endif
  247. int checkboard(void)
  248. {
  249. struct cpu_type *cpu;
  250. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  251. u8 val;
  252. cpu = gd->arch.cpu;
  253. #if defined(CONFIG_TARGET_P1010RDB_PA)
  254. printf("Board: %sRDB-PA, ", cpu->name);
  255. #elif defined(CONFIG_TARGET_P1010RDB_PB)
  256. printf("Board: %sRDB-PB, ", cpu->name);
  257. i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
  258. i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
  259. val = 0x0; /* no polarity inversion */
  260. i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
  261. #endif
  262. #ifdef CONFIG_SDCARD
  263. /* switch to IFC to read info from CPLD */
  264. config_board_mux(MUX_TYPE_IFC);
  265. #endif
  266. #if defined(CONFIG_TARGET_P1010RDB_PA)
  267. val = (in_8(&cpld_data->pcba_ver) & 0xf);
  268. printf("PCB: v%x.0\n", val);
  269. #elif defined(CONFIG_TARGET_P1010RDB_PB)
  270. val = in_8(&cpld_data->cpld_ver);
  271. printf("CPLD: v%x.%x, ", val >> 4, val & 0xf);
  272. printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER));
  273. val = in_8(&cpld_data->rom_loc) & 0xf;
  274. puts("Boot from: ");
  275. switch (val) {
  276. case 0xf:
  277. config_board_mux(MUX_TYPE_CS0_NOR);
  278. printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK));
  279. break;
  280. case 0xe:
  281. puts("SDHC\n");
  282. val = 0x60; /* set pca9557 pin input/output */
  283. i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
  284. break;
  285. case 0x5:
  286. config_board_mux(MUX_TYPE_IFC);
  287. config_board_mux(MUX_TYPE_CS0_NAND);
  288. puts("NAND\n");
  289. break;
  290. case 0x6:
  291. config_board_mux(MUX_TYPE_IFC);
  292. puts("SPI\n");
  293. break;
  294. default:
  295. puts("unknown\n");
  296. break;
  297. }
  298. #endif
  299. return 0;
  300. }
  301. int board_eth_init(bd_t *bis)
  302. {
  303. #ifdef CONFIG_TSEC_ENET
  304. struct fsl_pq_mdio_info mdio_info;
  305. struct tsec_info_struct tsec_info[4];
  306. struct cpu_type *cpu;
  307. int num = 0;
  308. cpu = gd->arch.cpu;
  309. #ifdef CONFIG_TSEC1
  310. SET_STD_TSEC_INFO(tsec_info[num], 1);
  311. num++;
  312. #endif
  313. #ifdef CONFIG_TSEC2
  314. SET_STD_TSEC_INFO(tsec_info[num], 2);
  315. num++;
  316. #endif
  317. #ifdef CONFIG_TSEC3
  318. /* P1014 and it's derivatives do not support eTSEC3 */
  319. if (cpu->soc_ver != SVR_P1014) {
  320. SET_STD_TSEC_INFO(tsec_info[num], 3);
  321. num++;
  322. }
  323. #endif
  324. if (!num) {
  325. printf("No TSECs initialized\n");
  326. return 0;
  327. }
  328. mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
  329. mdio_info.name = DEFAULT_MII_NAME;
  330. fsl_pq_mdio_init(bis, &mdio_info);
  331. tsec_eth_init(bis, tsec_info, num);
  332. #endif
  333. return pci_eth_init(bis);
  334. }
  335. #if defined(CONFIG_OF_BOARD_SETUP)
  336. void fdt_del_flexcan(void *blob)
  337. {
  338. int nodeoff = 0;
  339. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  340. "fsl,p1010-flexcan")) >= 0) {
  341. fdt_del_node(blob, nodeoff);
  342. }
  343. }
  344. void fdt_del_spi_flash(void *blob)
  345. {
  346. int nodeoff = 0;
  347. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  348. "spansion,s25sl12801")) >= 0) {
  349. fdt_del_node(blob, nodeoff);
  350. }
  351. }
  352. void fdt_del_spi_slic(void *blob)
  353. {
  354. int nodeoff = 0;
  355. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  356. "zarlink,le88266")) >= 0) {
  357. fdt_del_node(blob, nodeoff);
  358. }
  359. }
  360. void fdt_del_tdm(void *blob)
  361. {
  362. int nodeoff = 0;
  363. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  364. "fsl,starlite-tdm")) >= 0) {
  365. fdt_del_node(blob, nodeoff);
  366. }
  367. }
  368. void fdt_del_sdhc(void *blob)
  369. {
  370. int nodeoff = 0;
  371. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  372. "fsl,esdhc")) >= 0) {
  373. fdt_del_node(blob, nodeoff);
  374. }
  375. }
  376. void fdt_del_ifc(void *blob)
  377. {
  378. int nodeoff = 0;
  379. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  380. "fsl,ifc")) >= 0) {
  381. fdt_del_node(blob, nodeoff);
  382. }
  383. }
  384. void fdt_disable_uart1(void *blob)
  385. {
  386. int nodeoff;
  387. nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550",
  388. CONFIG_SYS_NS16550_COM2);
  389. if (nodeoff > 0) {
  390. fdt_status_disabled(blob, nodeoff);
  391. } else {
  392. printf("WARNING unable to set status for fsl,ns16550 "
  393. "uart1: %s\n", fdt_strerror(nodeoff));
  394. }
  395. }
  396. int ft_board_setup(void *blob, bd_t *bd)
  397. {
  398. phys_addr_t base;
  399. phys_size_t size;
  400. struct cpu_type *cpu;
  401. cpu = gd->arch.cpu;
  402. ft_cpu_setup(blob, bd);
  403. base = env_get_bootm_low();
  404. size = env_get_bootm_size();
  405. #if defined(CONFIG_PCI)
  406. FT_FSL_PCI_SETUP;
  407. #endif
  408. fdt_fixup_memory(blob, (u64)base, (u64)size);
  409. #if defined(CONFIG_HAS_FSL_DR_USB)
  410. fsl_fdt_fixup_dr_usb(blob, bd);
  411. #endif
  412. /* P1014 and it's derivatives don't support CAN and eTSEC3 */
  413. if (cpu->soc_ver == SVR_P1014) {
  414. fdt_del_flexcan(blob);
  415. fdt_del_node_and_alias(blob, "ethernet2");
  416. }
  417. /* Delete IFC node as IFC pins are multiplexing with SDHC */
  418. if (sd_ifc_mux != MUX_TYPE_IFC)
  419. fdt_del_ifc(blob);
  420. else
  421. fdt_del_sdhc(blob);
  422. if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
  423. fdt_del_tdm(blob);
  424. fdt_del_spi_slic(blob);
  425. } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
  426. fdt_del_flexcan(blob);
  427. fdt_del_spi_flash(blob);
  428. fdt_disable_uart1(blob);
  429. } else {
  430. /*
  431. * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm"
  432. * explicitly, defaultly spi_cs_sel to spi-flash instead of
  433. * to tdm/slic.
  434. */
  435. fdt_del_tdm(blob);
  436. fdt_del_flexcan(blob);
  437. fdt_disable_uart1(blob);
  438. }
  439. return 0;
  440. }
  441. #endif
  442. #ifdef CONFIG_SDCARD
  443. int board_mmc_init(bd_t *bis)
  444. {
  445. config_board_mux(MUX_TYPE_SDHC);
  446. return -1;
  447. }
  448. #else
  449. void board_reset(void)
  450. {
  451. /* mux to IFC to enable CPLD for reset */
  452. if (sd_ifc_mux != MUX_TYPE_IFC)
  453. config_board_mux(MUX_TYPE_IFC);
  454. }
  455. #endif
  456. int misc_init_r(void)
  457. {
  458. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  459. if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
  460. clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
  461. MPC85xx_PMUXCR_CAN1_UART |
  462. MPC85xx_PMUXCR_CAN2_TDM |
  463. MPC85xx_PMUXCR_CAN2_UART);
  464. config_board_mux(MUX_TYPE_CAN);
  465. } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
  466. clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
  467. MPC85xx_PMUXCR_CAN1_UART);
  468. setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |
  469. MPC85xx_PMUXCR_CAN1_TDM);
  470. clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
  471. setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
  472. config_board_mux(MUX_TYPE_TDM);
  473. } else {
  474. /* defaultly spi_cs_sel to flash */
  475. config_board_mux(MUX_TYPE_SPIFLASH);
  476. }
  477. if (hwconfig("esdhc"))
  478. config_board_mux(MUX_TYPE_SDHC);
  479. else if (hwconfig("ifc"))
  480. config_board_mux(MUX_TYPE_IFC);
  481. #ifdef CONFIG_TARGET_P1010RDB_PB
  482. setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
  483. #endif
  484. return 0;
  485. }
  486. #ifndef CONFIG_SPL_BUILD
  487. static int pin_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
  488. char * const argv[])
  489. {
  490. if (argc < 2)
  491. return CMD_RET_USAGE;
  492. if (strcmp(argv[1], "ifc") == 0)
  493. config_board_mux(MUX_TYPE_IFC);
  494. else if (strcmp(argv[1], "sdhc") == 0)
  495. config_board_mux(MUX_TYPE_SDHC);
  496. else
  497. return CMD_RET_USAGE;
  498. return 0;
  499. }
  500. U_BOOT_CMD(
  501. mux, 2, 0, pin_mux_cmd,
  502. "configure multiplexing pin for IFC/SDHC bus in runtime",
  503. "bus_type (e.g. mux sdhc)"
  504. );
  505. #endif