mx7dsabresd.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Freescale Semiconductor, Inc.
  4. */
  5. #include <init.h>
  6. #include <asm/arch/clock.h>
  7. #include <asm/arch/imx-regs.h>
  8. #include <asm/arch/mx7-pins.h>
  9. #include <asm/arch/sys_proto.h>
  10. #include <asm/gpio.h>
  11. #include <asm/mach-imx/iomux-v3.h>
  12. #include <asm/io.h>
  13. #include <linux/sizes.h>
  14. #include <common.h>
  15. #include <fsl_esdhc_imx.h>
  16. #include <mmc.h>
  17. #include <miiphy.h>
  18. #include <netdev.h>
  19. #include <power/pmic.h>
  20. #include <power/pfuze3000_pmic.h>
  21. #include "../common/pfuze.h"
  22. #include <i2c.h>
  23. #include <asm/mach-imx/mxc_i2c.h>
  24. #include <asm/arch/crm_regs.h>
  25. DECLARE_GLOBAL_DATA_PTR;
  26. #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
  27. PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
  28. #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  29. #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
  30. #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  31. #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
  32. PAD_CTL_DSE_3P3V_49OHM)
  33. #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
  34. #define SPI_PAD_CTRL \
  35. (PAD_CTL_HYS | PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST)
  36. #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
  37. #ifdef CONFIG_MXC_SPI
  38. static iomux_v3_cfg_t const ecspi3_pads[] = {
  39. MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  40. MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  41. MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  42. MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
  43. };
  44. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  45. {
  46. return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(6, 22)) : -1;
  47. }
  48. static void setup_spi(void)
  49. {
  50. imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));
  51. }
  52. #endif
  53. int dram_init(void)
  54. {
  55. gd->ram_size = PHYS_SDRAM_SIZE;
  56. return 0;
  57. }
  58. static iomux_v3_cfg_t const wdog_pads[] = {
  59. MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  60. };
  61. static iomux_v3_cfg_t const uart1_pads[] = {
  62. MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  63. MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  64. };
  65. #ifdef CONFIG_NAND_MXS
  66. static iomux_v3_cfg_t const gpmi_pads[] = {
  67. MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  68. MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  69. MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  70. MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  71. MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  72. MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  73. MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  74. MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  75. MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
  76. MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
  77. MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  78. MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  79. MX7D_PAD_SAI1_MCLK__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  80. MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  81. MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  82. MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  83. MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  84. MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL),
  85. MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
  86. };
  87. static void setup_gpmi_nand(void)
  88. {
  89. imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
  90. /* NAND_USDHC_BUS_CLK is set in rom */
  91. set_clk_nand();
  92. }
  93. #endif
  94. #ifdef CONFIG_VIDEO_MXS
  95. static iomux_v3_cfg_t const lcd_pads[] = {
  96. MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
  97. MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
  98. MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  99. MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  100. MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  101. MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  102. MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  103. MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  104. MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  105. MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  106. MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  107. MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  108. MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  109. MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  110. MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  111. MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  112. MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  113. MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  114. MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  115. MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  116. MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  117. MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  118. MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  119. MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  120. MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  121. MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  122. MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  123. MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  124. MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  125. };
  126. static iomux_v3_cfg_t const pwm_pads[] = {
  127. /* Use GPIO for Brightness adjustment, duty cycle = period */
  128. MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
  129. };
  130. static int setup_lcd(void)
  131. {
  132. imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
  133. imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
  134. /* Reset LCD */
  135. gpio_request(IMX_GPIO_NR(3, 4), "lcd reset");
  136. gpio_direction_output(IMX_GPIO_NR(3, 4) , 0);
  137. udelay(500);
  138. gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
  139. /* Set Brightness to high */
  140. gpio_request(IMX_GPIO_NR(1, 1), "lcd backlight");
  141. gpio_direction_output(IMX_GPIO_NR(1, 1) , 1);
  142. return 0;
  143. }
  144. #endif
  145. #ifdef CONFIG_FEC_MXC
  146. static iomux_v3_cfg_t const fec1_pads[] = {
  147. MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  148. MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  149. MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  150. MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  151. MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  152. MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  153. MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  154. MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  155. MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  156. MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  157. MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  158. MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  159. MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
  160. MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
  161. };
  162. static void setup_iomux_fec(void)
  163. {
  164. imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
  165. }
  166. #endif
  167. static void setup_iomux_uart(void)
  168. {
  169. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  170. }
  171. int board_mmc_get_env_dev(int devno)
  172. {
  173. if (devno == 2)
  174. devno--;
  175. return devno;
  176. }
  177. int mmc_map_to_kernel_blk(int dev_no)
  178. {
  179. if (dev_no == 1)
  180. dev_no++;
  181. return dev_no;
  182. }
  183. #ifdef CONFIG_FEC_MXC
  184. int board_eth_init(bd_t *bis)
  185. {
  186. int ret;
  187. unsigned int gpio;
  188. ret = gpio_lookup_name("gpio_spi@0_5", NULL, NULL, &gpio);
  189. if (ret) {
  190. printf("GPIO: 'gpio_spi@0_5' not found\n");
  191. return -ENODEV;
  192. }
  193. ret = gpio_request(gpio, "fec_rst");
  194. if (ret && ret != -EBUSY) {
  195. printf("gpio: requesting pin %u failed\n", gpio);
  196. return ret;
  197. }
  198. gpio_direction_output(gpio, 0);
  199. udelay(500);
  200. gpio_direction_output(gpio, 1);
  201. setup_iomux_fec();
  202. ret = fecmxc_initialize_multi(bis, 0,
  203. CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
  204. if (ret)
  205. printf("FEC1 MXC: %s:failed\n", __func__);
  206. return ret;
  207. }
  208. static int setup_fec(void)
  209. {
  210. struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
  211. = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
  212. /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
  213. clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
  214. (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
  215. IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
  216. return set_clk_enet(ENET_125MHZ);
  217. }
  218. int board_phy_config(struct phy_device *phydev)
  219. {
  220. /* enable rgmii rxc skew and phy mode select to RGMII copper */
  221. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21);
  222. phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8);
  223. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f);
  224. phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7);
  225. if (phydev->drv->config)
  226. phydev->drv->config(phydev);
  227. return 0;
  228. }
  229. #endif
  230. #ifdef CONFIG_FSL_QSPI
  231. int board_qspi_init(void)
  232. {
  233. /* Set the clock */
  234. set_clk_qspi();
  235. return 0;
  236. }
  237. #endif
  238. int board_early_init_f(void)
  239. {
  240. setup_iomux_uart();
  241. return 0;
  242. }
  243. int board_init(void)
  244. {
  245. /* address of boot parameters */
  246. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  247. #ifdef CONFIG_FEC_MXC
  248. setup_fec();
  249. #endif
  250. #ifdef CONFIG_NAND_MXS
  251. setup_gpmi_nand();
  252. #endif
  253. #ifdef CONFIG_VIDEO_MXS
  254. setup_lcd();
  255. #endif
  256. #ifdef CONFIG_FSL_QSPI
  257. board_qspi_init();
  258. #endif
  259. #ifdef CONFIG_MXC_SPI
  260. setup_spi();
  261. #endif
  262. return 0;
  263. }
  264. #ifdef CONFIG_DM_PMIC
  265. int power_init_board(void)
  266. {
  267. struct udevice *dev;
  268. int ret, dev_id, rev_id;
  269. ret = pmic_get("pfuze3000", &dev);
  270. if (ret == -ENODEV)
  271. return 0;
  272. if (ret != 0)
  273. return ret;
  274. dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
  275. rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
  276. printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
  277. pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1);
  278. /*
  279. * Set the voltage of VLDO4 output to 2.8V which feeds
  280. * the MIPI DSI and MIPI CSI inputs.
  281. */
  282. pmic_clrsetbits(dev, PFUZE3000_VLD4CTL, 0xF, 0xA);
  283. return 0;
  284. }
  285. #endif
  286. int board_late_init(void)
  287. {
  288. struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  289. imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  290. set_wdog_reset(wdog);
  291. /*
  292. * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
  293. * since we use PMIC_PWRON to reset the board.
  294. */
  295. clrsetbits_le16(&wdog->wcr, 0, 0x10);
  296. return 0;
  297. }
  298. int checkboard(void)
  299. {
  300. char *mode;
  301. if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
  302. mode = "secure";
  303. else
  304. mode = "non-secure";
  305. printf("Board: i.MX7D SABRESD in %s mode\n", mode);
  306. return 0;
  307. }