mx53evk.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <init.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include <asm/arch/sys_proto.h>
  10. #include <asm/arch/crm_regs.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/iomux-mx53.h>
  13. #include <linux/errno.h>
  14. #include <asm/mach-imx/boot_mode.h>
  15. #include <netdev.h>
  16. #include <i2c.h>
  17. #include <mmc.h>
  18. #include <fsl_esdhc_imx.h>
  19. #include <power/pmic.h>
  20. #include <fsl_pmic.h>
  21. #include <asm/gpio.h>
  22. #include <mc13892.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. int dram_init(void)
  25. {
  26. /* dram_init must store complete ramsize in gd->ram_size */
  27. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  28. PHYS_SDRAM_1_SIZE);
  29. return 0;
  30. }
  31. #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
  32. PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
  33. static void setup_iomux_uart(void)
  34. {
  35. static const iomux_v3_cfg_t uart_pads[] = {
  36. NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
  37. NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
  38. };
  39. imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  40. }
  41. #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
  42. PAD_CTL_HYS | PAD_CTL_ODE)
  43. static void setup_i2c(unsigned int port_number)
  44. {
  45. static const iomux_v3_cfg_t i2c1_pads[] = {
  46. NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
  47. NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
  48. };
  49. static const iomux_v3_cfg_t i2c2_pads[] = {
  50. NEW_PAD_CTRL(MX53_PAD_KEY_ROW3__I2C2_SDA, I2C_PAD_CTRL),
  51. NEW_PAD_CTRL(MX53_PAD_KEY_COL3__I2C2_SCL, I2C_PAD_CTRL),
  52. };
  53. switch (port_number) {
  54. case 0:
  55. imx_iomux_v3_setup_multiple_pads(i2c1_pads,
  56. ARRAY_SIZE(i2c1_pads));
  57. break;
  58. case 1:
  59. imx_iomux_v3_setup_multiple_pads(i2c2_pads,
  60. ARRAY_SIZE(i2c2_pads));
  61. break;
  62. default:
  63. printf("Warning: Wrong I2C port number\n");
  64. break;
  65. }
  66. }
  67. void power_init(void)
  68. {
  69. unsigned int val;
  70. struct pmic *p;
  71. int ret;
  72. ret = pmic_init(I2C_0);
  73. if (ret)
  74. return;
  75. p = pmic_get("FSL_PMIC");
  76. if (!p)
  77. return;
  78. /* Set VDDA to 1.25V */
  79. pmic_reg_read(p, REG_SW_2, &val);
  80. val &= ~SWX_OUT_MASK;
  81. val |= SWX_OUT_1_25;
  82. pmic_reg_write(p, REG_SW_2, val);
  83. /*
  84. * Need increase VCC and VDDA to 1.3V
  85. * according to MX53 IC TO2 datasheet.
  86. */
  87. if (is_soc_rev(CHIP_REV_2_0) == 0) {
  88. /* Set VCC to 1.3V for TO2 */
  89. pmic_reg_read(p, REG_SW_1, &val);
  90. val &= ~SWX_OUT_MASK;
  91. val |= SWX_OUT_1_30;
  92. pmic_reg_write(p, REG_SW_1, val);
  93. /* Set VDDA to 1.3V for TO2 */
  94. pmic_reg_read(p, REG_SW_2, &val);
  95. val &= ~SWX_OUT_MASK;
  96. val |= SWX_OUT_1_30;
  97. pmic_reg_write(p, REG_SW_2, val);
  98. }
  99. }
  100. static void setup_iomux_fec(void)
  101. {
  102. static const iomux_v3_cfg_t fec_pads[] = {
  103. NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
  104. PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
  105. NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
  106. NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
  107. PAD_CTL_HYS | PAD_CTL_PKE),
  108. NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
  109. PAD_CTL_HYS | PAD_CTL_PKE),
  110. NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
  111. NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
  112. NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
  113. NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
  114. PAD_CTL_HYS | PAD_CTL_PKE),
  115. NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
  116. PAD_CTL_HYS | PAD_CTL_PKE),
  117. NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
  118. PAD_CTL_HYS | PAD_CTL_PKE),
  119. };
  120. imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
  121. }
  122. #ifdef CONFIG_FSL_ESDHC_IMX
  123. struct fsl_esdhc_cfg esdhc_cfg[2] = {
  124. {MMC_SDHC1_BASE_ADDR},
  125. {MMC_SDHC3_BASE_ADDR},
  126. };
  127. int board_mmc_getcd(struct mmc *mmc)
  128. {
  129. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  130. int ret;
  131. imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
  132. gpio_direction_input(IMX_GPIO_NR(3, 11));
  133. imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
  134. gpio_direction_input(IMX_GPIO_NR(3, 13));
  135. if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
  136. ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
  137. else
  138. ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
  139. return ret;
  140. }
  141. #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
  142. PAD_CTL_PUS_100K_UP)
  143. #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
  144. PAD_CTL_DSE_HIGH)
  145. int board_mmc_init(bd_t *bis)
  146. {
  147. static const iomux_v3_cfg_t sd1_pads[] = {
  148. NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
  149. NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
  150. NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
  151. NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
  152. NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
  153. NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
  154. MX53_PAD_EIM_DA13__GPIO3_13,
  155. };
  156. static const iomux_v3_cfg_t sd2_pads[] = {
  157. NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
  158. SD_CMD_PAD_CTRL),
  159. NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
  160. NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
  161. NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
  162. NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
  163. NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
  164. NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
  165. NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
  166. NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
  167. NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
  168. MX53_PAD_EIM_DA11__GPIO3_11,
  169. };
  170. u32 index;
  171. int ret;
  172. esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  173. esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  174. for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
  175. switch (index) {
  176. case 0:
  177. imx_iomux_v3_setup_multiple_pads(sd1_pads,
  178. ARRAY_SIZE(sd1_pads));
  179. break;
  180. case 1:
  181. imx_iomux_v3_setup_multiple_pads(sd2_pads,
  182. ARRAY_SIZE(sd2_pads));
  183. break;
  184. default:
  185. printf("Warning: you configured more ESDHC controller"
  186. "(%d) as supported by the board(2)\n",
  187. CONFIG_SYS_FSL_ESDHC_NUM);
  188. return -EINVAL;
  189. }
  190. ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
  191. if (ret)
  192. return ret;
  193. }
  194. return 0;
  195. }
  196. #endif
  197. int board_early_init_f(void)
  198. {
  199. setup_iomux_uart();
  200. setup_iomux_fec();
  201. return 0;
  202. }
  203. int board_init(void)
  204. {
  205. /* address of boot parameters */
  206. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  207. return 0;
  208. }
  209. #ifdef CONFIG_CMD_BMODE
  210. static const struct boot_mode board_boot_modes[] = {
  211. /* 4 bit bus width */
  212. {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
  213. {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
  214. {NULL, 0},
  215. };
  216. #endif
  217. int board_late_init(void)
  218. {
  219. setup_i2c(1);
  220. power_init();
  221. #ifdef CONFIG_CMD_BMODE
  222. add_board_boot_modes(board_boot_modes);
  223. #endif
  224. return 0;
  225. }
  226. int checkboard(void)
  227. {
  228. puts("Board: MX53EVK\n");
  229. return 0;
  230. }