mx35pdk.c 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
  4. *
  5. * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
  6. */
  7. #include <common.h>
  8. #include <init.h>
  9. #include <asm/io.h>
  10. #include <linux/errno.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <asm/arch/crm_regs.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/iomux-mx35.h>
  15. #include <i2c.h>
  16. #include <power/pmic.h>
  17. #include <fsl_pmic.h>
  18. #include <mmc.h>
  19. #include <fsl_esdhc_imx.h>
  20. #include <mc9sdz60.h>
  21. #include <mc13892.h>
  22. #include <linux/types.h>
  23. #include <asm/gpio.h>
  24. #include <asm/arch/sys_proto.h>
  25. #include <netdev.h>
  26. #include <asm/mach-types.h>
  27. #ifndef CONFIG_BOARD_LATE_INIT
  28. #error "CONFIG_BOARD_LATE_INIT must be set for this board"
  29. #endif
  30. #ifndef CONFIG_BOARD_EARLY_INIT_F
  31. #error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
  32. #endif
  33. DECLARE_GLOBAL_DATA_PTR;
  34. int dram_init(void)
  35. {
  36. u32 size1, size2;
  37. size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  38. size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
  39. gd->ram_size = size1 + size2;
  40. return 0;
  41. }
  42. int dram_init_banksize(void)
  43. {
  44. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  45. gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  46. gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  47. gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  48. return 0;
  49. }
  50. #define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
  51. static void setup_iomux_i2c(void)
  52. {
  53. static const iomux_v3_cfg_t i2c1_pads[] = {
  54. NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
  55. NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
  56. };
  57. /* setup pins for I2C1 */
  58. imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
  59. }
  60. static void setup_iomux_spi(void)
  61. {
  62. static const iomux_v3_cfg_t spi_pads[] = {
  63. MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
  64. MX35_PAD_CSPI1_MISO__CSPI1_MISO,
  65. MX35_PAD_CSPI1_SS0__CSPI1_SS0,
  66. MX35_PAD_CSPI1_SS1__CSPI1_SS1,
  67. MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
  68. };
  69. imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
  70. }
  71. #define USBOTG_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | \
  72. PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
  73. #define USBOTG_OUT_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
  74. static void setup_iomux_usbotg(void)
  75. {
  76. static const iomux_v3_cfg_t usbotg_pads[] = {
  77. NEW_PAD_CTRL(MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
  78. USBOTG_OUT_PAD_CTRL),
  79. NEW_PAD_CTRL(MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
  80. USBOTG_IN_PAD_CTRL),
  81. };
  82. /* Set up pins for USBOTG. */
  83. imx_iomux_v3_setup_multiple_pads(usbotg_pads, ARRAY_SIZE(usbotg_pads));
  84. }
  85. #define FEC_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
  86. static void setup_iomux_fec(void)
  87. {
  88. static const iomux_v3_cfg_t fec_pads[] = {
  89. NEW_PAD_CTRL(MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, FEC_PAD_CTRL |
  90. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  91. NEW_PAD_CTRL(MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, FEC_PAD_CTRL |
  92. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  93. NEW_PAD_CTRL(MX35_PAD_FEC_RX_DV__FEC_RX_DV, FEC_PAD_CTRL |
  94. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  95. NEW_PAD_CTRL(MX35_PAD_FEC_COL__FEC_COL, FEC_PAD_CTRL |
  96. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  97. NEW_PAD_CTRL(MX35_PAD_FEC_RDATA0__FEC_RDATA_0, FEC_PAD_CTRL |
  98. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  99. NEW_PAD_CTRL(MX35_PAD_FEC_TDATA0__FEC_TDATA_0, FEC_PAD_CTRL),
  100. NEW_PAD_CTRL(MX35_PAD_FEC_TX_EN__FEC_TX_EN, FEC_PAD_CTRL),
  101. NEW_PAD_CTRL(MX35_PAD_FEC_MDC__FEC_MDC, FEC_PAD_CTRL),
  102. NEW_PAD_CTRL(MX35_PAD_FEC_MDIO__FEC_MDIO, FEC_PAD_CTRL |
  103. PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
  104. NEW_PAD_CTRL(MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, FEC_PAD_CTRL),
  105. NEW_PAD_CTRL(MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, FEC_PAD_CTRL |
  106. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  107. NEW_PAD_CTRL(MX35_PAD_FEC_CRS__FEC_CRS, FEC_PAD_CTRL |
  108. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  109. NEW_PAD_CTRL(MX35_PAD_FEC_RDATA1__FEC_RDATA_1, FEC_PAD_CTRL |
  110. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  111. NEW_PAD_CTRL(MX35_PAD_FEC_TDATA1__FEC_TDATA_1, FEC_PAD_CTRL),
  112. NEW_PAD_CTRL(MX35_PAD_FEC_RDATA2__FEC_RDATA_2, FEC_PAD_CTRL |
  113. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  114. NEW_PAD_CTRL(MX35_PAD_FEC_TDATA2__FEC_TDATA_2, FEC_PAD_CTRL),
  115. NEW_PAD_CTRL(MX35_PAD_FEC_RDATA3__FEC_RDATA_3, FEC_PAD_CTRL |
  116. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  117. NEW_PAD_CTRL(MX35_PAD_FEC_TDATA3__FEC_TDATA_3, FEC_PAD_CTRL),
  118. };
  119. /* setup pins for FEC */
  120. imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
  121. }
  122. int board_early_init_f(void)
  123. {
  124. struct ccm_regs *ccm =
  125. (struct ccm_regs *)IMX_CCM_BASE;
  126. /* enable clocks */
  127. writel(readl(&ccm->cgr0) |
  128. MXC_CCM_CGR0_EMI_MASK |
  129. MXC_CCM_CGR0_EDIO_MASK |
  130. MXC_CCM_CGR0_EPIT1_MASK,
  131. &ccm->cgr0);
  132. writel(readl(&ccm->cgr1) |
  133. MXC_CCM_CGR1_FEC_MASK |
  134. MXC_CCM_CGR1_GPIO1_MASK |
  135. MXC_CCM_CGR1_GPIO2_MASK |
  136. MXC_CCM_CGR1_GPIO3_MASK |
  137. MXC_CCM_CGR1_I2C1_MASK |
  138. MXC_CCM_CGR1_I2C2_MASK |
  139. MXC_CCM_CGR1_IPU_MASK,
  140. &ccm->cgr1);
  141. /* Setup NAND */
  142. __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
  143. setup_iomux_i2c();
  144. setup_iomux_usbotg();
  145. setup_iomux_fec();
  146. setup_iomux_spi();
  147. return 0;
  148. }
  149. int board_init(void)
  150. {
  151. gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */
  152. /* address of boot parameters */
  153. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  154. return 0;
  155. }
  156. static inline int pmic_detect(void)
  157. {
  158. unsigned int id;
  159. struct pmic *p = pmic_get("FSL_PMIC");
  160. if (!p)
  161. return -ENODEV;
  162. pmic_reg_read(p, REG_IDENTIFICATION, &id);
  163. id = (id >> 6) & 0x7;
  164. if (id == 0x7)
  165. return 1;
  166. return 0;
  167. }
  168. u32 get_board_rev(void)
  169. {
  170. int rev;
  171. rev = pmic_detect();
  172. return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
  173. }
  174. int board_late_init(void)
  175. {
  176. u8 val;
  177. u32 pmic_val;
  178. struct pmic *p;
  179. int ret;
  180. ret = pmic_init(I2C_0);
  181. if (ret)
  182. return ret;
  183. if (pmic_detect()) {
  184. p = pmic_get("FSL_PMIC");
  185. imx_iomux_v3_setup_pad(MX35_PAD_WDOG_RST__WDOG_WDOG_B);
  186. pmic_reg_read(p, REG_SETTING_0, &pmic_val);
  187. pmic_reg_write(p, REG_SETTING_0,
  188. pmic_val | VO_1_30V | VO_1_50V);
  189. pmic_reg_read(p, REG_MODE_0, &pmic_val);
  190. pmic_reg_write(p, REG_MODE_0, pmic_val | VGEN3EN);
  191. imx_iomux_v3_setup_pad(MX35_PAD_COMPARE__GPIO1_5);
  192. gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
  193. }
  194. val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04;
  195. mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val);
  196. mdelay(200);
  197. val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F;
  198. mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
  199. mdelay(200);
  200. val |= 0x80;
  201. mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
  202. /* Print board revision */
  203. printf("Board: MX35 PDK %d.0\n", ((get_board_rev() >> 8) + 1) & 0x0F);
  204. return 0;
  205. }
  206. int board_eth_init(bd_t *bis)
  207. {
  208. #if defined(CONFIG_SMC911X)
  209. int rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
  210. if (rc)
  211. return rc;
  212. #endif
  213. return cpu_eth_init(bis);
  214. }
  215. #if defined(CONFIG_FSL_ESDHC_IMX)
  216. struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
  217. int board_mmc_init(bd_t *bis)
  218. {
  219. static const iomux_v3_cfg_t sdhc1_pads[] = {
  220. MX35_PAD_SD1_CMD__ESDHC1_CMD,
  221. MX35_PAD_SD1_CLK__ESDHC1_CLK,
  222. MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
  223. MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
  224. MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
  225. MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
  226. };
  227. /* configure pins for SDHC1 only */
  228. imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
  229. esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
  230. return fsl_esdhc_initialize(bis, &esdhc_cfg);
  231. }
  232. int board_mmc_getcd(struct mmc *mmc)
  233. {
  234. return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4);
  235. }
  236. #endif