mx31pdk.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
  5. *
  6. * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  7. */
  8. #include <common.h>
  9. #include <init.h>
  10. #include <netdev.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <watchdog.h>
  15. #include <power/pmic.h>
  16. #include <fsl_pmic.h>
  17. #include <errno.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. #ifdef CONFIG_SPL_BUILD
  20. void board_init_f(ulong bootflag)
  21. {
  22. /*
  23. * copy ourselves from where we are running to where we were
  24. * linked at. Use ulong pointers as all addresses involved
  25. * are 4-byte-aligned.
  26. */
  27. ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst;
  28. asm volatile ("ldr %0, =_start" : "=r"(start_ptr));
  29. asm volatile ("ldr %0, =_end" : "=r"(end_ptr));
  30. asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr));
  31. asm volatile ("adr %0, board_init_f" : "=r"(run_ptr));
  32. for (dst = start_ptr; dst < end_ptr; dst++)
  33. *dst = *(dst+(run_ptr-link_ptr));
  34. /*
  35. * branch to nand_boot's link-time address.
  36. */
  37. asm volatile("ldr pc, =nand_boot");
  38. }
  39. #endif
  40. int dram_init(void)
  41. {
  42. /* dram_init must store complete ramsize in gd->ram_size */
  43. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  44. PHYS_SDRAM_1_SIZE);
  45. return 0;
  46. }
  47. int board_early_init_f(void)
  48. {
  49. /* CS5: CPLD incl. network controller */
  50. static const struct mxc_weimcs cs5 = {
  51. /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
  52. CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3),
  53. /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
  54. CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1),
  55. /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
  56. CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0)
  57. };
  58. mxc_setup_weimcs(5, &cs5);
  59. /* Setup UART1 and SPI2 pins */
  60. mx31_uart1_hw_init();
  61. mx31_spi2_hw_init();
  62. return 0;
  63. }
  64. int board_init(void)
  65. {
  66. /* adress of boot parameters */
  67. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  68. return 0;
  69. }
  70. int board_late_init(void)
  71. {
  72. u32 val;
  73. struct pmic *p;
  74. int ret;
  75. ret = pmic_init(CONFIG_FSL_PMIC_BUS);
  76. if (ret)
  77. return ret;
  78. p = pmic_get("FSL_PMIC");
  79. if (!p)
  80. return -ENODEV;
  81. /* Enable RTC battery */
  82. pmic_reg_read(p, REG_POWER_CTL0, &val);
  83. pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
  84. pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
  85. #ifdef CONFIG_HW_WATCHDOG
  86. hw_watchdog_init();
  87. #endif
  88. return 0;
  89. }
  90. int checkboard(void)
  91. {
  92. printf("Board: MX31PDK\n");
  93. return 0;
  94. }
  95. int board_eth_init(bd_t *bis)
  96. {
  97. int rc = 0;
  98. #ifdef CONFIG_SMC911X
  99. rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
  100. #endif
  101. return rc;
  102. }