mpc8536ds.c 6.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2008-2012 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <init.h>
  8. #include <pci.h>
  9. #include <asm/processor.h>
  10. #include <asm/mmu.h>
  11. #include <asm/cache.h>
  12. #include <asm/immap_85xx.h>
  13. #include <asm/fsl_pci.h>
  14. #include <fsl_ddr_sdram.h>
  15. #include <asm/io.h>
  16. #include <asm/fsl_serdes.h>
  17. #include <spd.h>
  18. #include <miiphy.h>
  19. #include <linux/libfdt.h>
  20. #include <spd_sdram.h>
  21. #include <fdt_support.h>
  22. #include <fsl_mdio.h>
  23. #include <tsec.h>
  24. #include <netdev.h>
  25. #include <sata.h>
  26. #include "../common/sgmii_riser.h"
  27. int board_early_init_f (void)
  28. {
  29. #ifdef CONFIG_MMC
  30. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  31. setbits_be32(&gur->pmuxcr,
  32. (MPC85xx_PMUXCR_SDHC_CD |
  33. MPC85xx_PMUXCR_SDHC_WP));
  34. /* The MPC8536DS board insert the SDHC_WP pin for erratum NMG_eSDHC118,
  35. * however, this erratum only applies to MPC8536 Rev1.0.
  36. * So set SDHC_WP to active-low when use MPC8536 Rev1.1 and greater.*/
  37. if ((((SVR_MAJ(get_svr()) & 0x7) == 0x1) &&
  38. (SVR_MIN(get_svr()) >= 0x1))
  39. || (SVR_MAJ(get_svr() & 0x7) > 0x1))
  40. setbits_be32(&gur->gencfgr, MPC85xx_GENCFGR_SDHC_WP_INV);
  41. #endif
  42. return 0;
  43. }
  44. int checkboard (void)
  45. {
  46. u8 vboot;
  47. u8 *pixis_base = (u8 *)PIXIS_BASE;
  48. printf("Board: MPC8536DS Sys ID: 0x%02x, "
  49. "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  50. in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
  51. in_8(pixis_base + PIXIS_PVER));
  52. vboot = in_8(pixis_base + PIXIS_VBOOT);
  53. switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
  54. case PIXIS_VBOOT_LBMAP_NOR0:
  55. puts ("vBank: 0\n");
  56. break;
  57. case PIXIS_VBOOT_LBMAP_NOR1:
  58. puts ("vBank: 1\n");
  59. break;
  60. case PIXIS_VBOOT_LBMAP_NOR2:
  61. puts ("vBank: 2\n");
  62. break;
  63. case PIXIS_VBOOT_LBMAP_NOR3:
  64. puts ("vBank: 3\n");
  65. break;
  66. case PIXIS_VBOOT_LBMAP_PJET:
  67. puts ("Promjet\n");
  68. break;
  69. case PIXIS_VBOOT_LBMAP_NAND:
  70. puts ("NAND\n");
  71. break;
  72. }
  73. return 0;
  74. }
  75. #if !defined(CONFIG_SPD_EEPROM)
  76. /*
  77. * Fixed sdram init -- doesn't use serial presence detect.
  78. */
  79. phys_size_t fixed_sdram (void)
  80. {
  81. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  82. struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
  83. uint d_init;
  84. ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
  85. ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  86. ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  87. ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  88. ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  89. ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  90. ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
  91. ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
  92. ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  93. ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
  94. ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
  95. ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
  96. #if defined (CONFIG_DDR_ECC)
  97. ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
  98. ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
  99. ddr->err_sbe = CONFIG_SYS_DDR_SBE;
  100. #endif
  101. asm("sync;isync");
  102. udelay(500);
  103. ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
  104. #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  105. d_init = 1;
  106. debug("DDR - 1st controller: memory initializing\n");
  107. /*
  108. * Poll until memory is initialized.
  109. * 512 Meg at 400 might hit this 200 times or so.
  110. */
  111. while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
  112. udelay(1000);
  113. }
  114. debug("DDR: memory initialized\n\n");
  115. asm("sync; isync");
  116. udelay(500);
  117. #endif
  118. return 512 * 1024 * 1024;
  119. }
  120. #endif
  121. #ifdef CONFIG_PCI1
  122. static struct pci_controller pci1_hose;
  123. #endif
  124. #ifdef CONFIG_PCI
  125. void pci_init_board(void)
  126. {
  127. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  128. struct fsl_pci_info pci_info;
  129. u32 devdisr, pordevsr;
  130. u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
  131. int first_free_busno;
  132. first_free_busno = fsl_pcie_init_board(0);
  133. #ifdef CONFIG_PCI1
  134. devdisr = in_be32(&gur->devdisr);
  135. pordevsr = in_be32(&gur->pordevsr);
  136. porpllsr = in_be32(&gur->porpllsr);
  137. pci_speed = 66666000;
  138. pci_32 = 1;
  139. pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
  140. pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
  141. if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
  142. SET_STD_PCI_INFO(pci_info, 1);
  143. set_next_law(pci_info.mem_phys,
  144. law_size_bits(pci_info.mem_size), pci_info.law);
  145. set_next_law(pci_info.io_phys,
  146. law_size_bits(pci_info.io_size), pci_info.law);
  147. pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
  148. printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
  149. (pci_32) ? 32 : 64,
  150. (pci_speed == 33333000) ? "33" :
  151. (pci_speed == 66666000) ? "66" : "unknown",
  152. pci_clk_sel ? "sync" : "async",
  153. pci_agent ? "agent" : "host",
  154. pci_arb ? "arbiter" : "external-arbiter",
  155. pci_info.regs);
  156. first_free_busno = fsl_pci_init_port(&pci_info,
  157. &pci1_hose, first_free_busno);
  158. } else {
  159. printf("PCI: disabled\n");
  160. }
  161. puts("\n");
  162. #else
  163. setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
  164. #endif
  165. }
  166. #endif
  167. int board_early_init_r(void)
  168. {
  169. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  170. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  171. /*
  172. * Remap Boot flash + PROMJET region to caching-inhibited
  173. * so that flash can be erased properly.
  174. */
  175. /* Flush d-cache and invalidate i-cache of any FLASH data */
  176. flush_dcache();
  177. invalidate_icache();
  178. if (flash_esel == -1) {
  179. /* very unlikely unless something is messed up */
  180. puts("Error: Could not find TLB for FLASH BASE\n");
  181. flash_esel = 1; /* give our best effort to continue */
  182. } else {
  183. /* invalidate existing TLB entry for flash + promjet */
  184. disable_tlb(flash_esel);
  185. }
  186. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
  187. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
  188. 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
  189. return 0;
  190. }
  191. int board_eth_init(bd_t *bis)
  192. {
  193. #ifdef CONFIG_TSEC_ENET
  194. struct fsl_pq_mdio_info mdio_info;
  195. struct tsec_info_struct tsec_info[2];
  196. int num = 0;
  197. #ifdef CONFIG_TSEC1
  198. SET_STD_TSEC_INFO(tsec_info[num], 1);
  199. if (is_serdes_configured(SGMII_TSEC1)) {
  200. puts("eTSEC1 is in sgmii mode.\n");
  201. tsec_info[num].phyaddr = 0;
  202. tsec_info[num].flags |= TSEC_SGMII;
  203. }
  204. num++;
  205. #endif
  206. #ifdef CONFIG_TSEC3
  207. SET_STD_TSEC_INFO(tsec_info[num], 3);
  208. if (is_serdes_configured(SGMII_TSEC3)) {
  209. puts("eTSEC3 is in sgmii mode.\n");
  210. tsec_info[num].phyaddr = 1;
  211. tsec_info[num].flags |= TSEC_SGMII;
  212. }
  213. num++;
  214. #endif
  215. if (!num) {
  216. printf("No TSECs initialized\n");
  217. return 0;
  218. }
  219. #ifdef CONFIG_FSL_SGMII_RISER
  220. if (is_serdes_configured(SGMII_TSEC1) ||
  221. is_serdes_configured(SGMII_TSEC3)) {
  222. fsl_sgmii_riser_init(tsec_info, num);
  223. }
  224. #endif
  225. mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
  226. mdio_info.name = DEFAULT_MII_NAME;
  227. fsl_pq_mdio_init(bis, &mdio_info);
  228. tsec_eth_init(bis, tsec_info, num);
  229. #endif
  230. return pci_eth_init(bis);
  231. }
  232. #if defined(CONFIG_OF_BOARD_SETUP)
  233. int ft_board_setup(void *blob, bd_t *bd)
  234. {
  235. ft_cpu_setup(blob, bd);
  236. FT_FSL_PCI_SETUP;
  237. #ifdef CONFIG_FSL_SGMII_RISER
  238. fsl_sgmii_riser_fdt_fixup(blob);
  239. #endif
  240. #ifdef CONFIG_HAS_FSL_MPH_USB
  241. fsl_fdt_fixup_dr_usb(blob, bd);
  242. #endif
  243. return 0;
  244. }
  245. #endif