c29xpcie.c 3.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <init.h>
  7. #include <asm/processor.h>
  8. #include <asm/mmu.h>
  9. #include <asm/cache.h>
  10. #include <asm/immap_85xx.h>
  11. #include <asm/io.h>
  12. #include <env.h>
  13. #include <miiphy.h>
  14. #include <linux/libfdt.h>
  15. #include <fdt_support.h>
  16. #include <fsl_mdio.h>
  17. #include <tsec.h>
  18. #include <mmc.h>
  19. #include <netdev.h>
  20. #include <pci.h>
  21. #include <fsl_ifc.h>
  22. #include <asm/fsl_pci.h>
  23. #include "cpld.h"
  24. DECLARE_GLOBAL_DATA_PTR;
  25. int checkboard(void)
  26. {
  27. struct cpu_type *cpu = gd->arch.cpu;
  28. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  29. printf("Board: %sPCIe, ", cpu->name);
  30. printf("CPLD Ver: 0x%02x\n", in_8(&cpld_data->cpldver));
  31. return 0;
  32. }
  33. int board_early_init_f(void)
  34. {
  35. struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
  36. /* Clock configuration to access CPLD using IFC(GPCM) */
  37. setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
  38. return 0;
  39. }
  40. int board_early_init_r(void)
  41. {
  42. const unsigned long flashbase = CONFIG_SYS_FLASH_BASE;
  43. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  44. /*
  45. * Remap Boot flash region to caching-inhibited
  46. * so that flash can be erased properly.
  47. */
  48. /* Flush d-cache and invalidate i-cache of any FLASH data */
  49. flush_dcache();
  50. invalidate_icache();
  51. if (flash_esel == -1) {
  52. /* very unlikely unless something is messed up */
  53. puts("Error: Could not find TLB for FLASH BASE\n");
  54. flash_esel = 1; /* give our best effort to continue */
  55. } else {
  56. /* invalidate existing TLB entry for flash */
  57. disable_tlb(flash_esel);
  58. }
  59. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  60. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  61. 0, flash_esel, BOOKE_PAGESZ_64M, 1);
  62. return 0;
  63. }
  64. #ifdef CONFIG_PCI
  65. void pci_init_board(void)
  66. {
  67. fsl_pcie_init_board(0);
  68. }
  69. #endif /* ifdef CONFIG_PCI */
  70. int board_eth_init(bd_t *bis)
  71. {
  72. #ifdef CONFIG_TSEC_ENET
  73. struct fsl_pq_mdio_info mdio_info;
  74. struct tsec_info_struct tsec_info[2];
  75. int num = 0;
  76. #ifdef CONFIG_TSEC1
  77. SET_STD_TSEC_INFO(tsec_info[num], 1);
  78. num++;
  79. #endif
  80. #ifdef CONFIG_TSEC2
  81. SET_STD_TSEC_INFO(tsec_info[num], 2);
  82. num++;
  83. #endif
  84. if (!num) {
  85. printf("No TSECs initialized\n");
  86. return 0;
  87. }
  88. /* Register 1G MDIO bus */
  89. mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
  90. mdio_info.name = DEFAULT_MII_NAME;
  91. fsl_pq_mdio_init(bis, &mdio_info);
  92. tsec_eth_init(bis, tsec_info, num);
  93. #endif
  94. return pci_eth_init(bis);
  95. }
  96. #if defined(CONFIG_OF_BOARD_SETUP)
  97. void fdt_del_sec(void *blob, int offset)
  98. {
  99. int nodeoff = 0;
  100. while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0",
  101. CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET
  102. + offset * CONFIG_SYS_FSL_SEC_IDX_OFFSET)) >= 0) {
  103. fdt_del_node(blob, nodeoff);
  104. offset++;
  105. }
  106. }
  107. int ft_board_setup(void *blob, bd_t *bd)
  108. {
  109. phys_addr_t base;
  110. phys_size_t size;
  111. struct cpu_type *cpu;
  112. cpu = gd->arch.cpu;
  113. ft_cpu_setup(blob, bd);
  114. base = env_get_bootm_low();
  115. size = env_get_bootm_size();
  116. #if defined(CONFIG_PCI)
  117. FT_FSL_PCI_SETUP;
  118. #endif
  119. fdt_fixup_memory(blob, (u64)base, (u64)size);
  120. if (cpu->soc_ver == SVR_C291)
  121. fdt_del_sec(blob, 1);
  122. else if (cpu->soc_ver == SVR_C292)
  123. fdt_del_sec(blob, 2);
  124. return 0;
  125. }
  126. #endif