mx6boards.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Eukréa Electromatique
  4. * Author: Eric Bénard <eric@eukrea.com>
  5. * Fabio Estevam <fabio.estevam@freescale.com>
  6. * Jon Nettleton <jon.nettleton@gmail.com>
  7. *
  8. * based on sabresd.c which is :
  9. * Copyright (C) 2012 Freescale Semiconductor, Inc.
  10. * and on hummingboard.c which is :
  11. * Copyright (C) 2013 SolidRun ltd.
  12. * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>.
  13. */
  14. #include <init.h>
  15. #include <asm/arch/clock.h>
  16. #include <asm/arch/sys_proto.h>
  17. #include <asm/arch/imx-regs.h>
  18. #include <asm/arch/iomux.h>
  19. #include <asm/arch/mx6-pins.h>
  20. #include <linux/errno.h>
  21. #include <asm/gpio.h>
  22. #include <asm/mach-imx/iomux-v3.h>
  23. #include <asm/mach-imx/boot_mode.h>
  24. #include <asm/mach-imx/mxc_i2c.h>
  25. #include <asm/mach-imx/spi.h>
  26. #include <asm/mach-imx/video.h>
  27. #include <i2c.h>
  28. #include <input.h>
  29. #include <mmc.h>
  30. #include <fsl_esdhc_imx.h>
  31. #include <miiphy.h>
  32. #include <netdev.h>
  33. #include <asm/arch/mxc_hdmi.h>
  34. #include <asm/arch/crm_regs.h>
  35. #include <linux/fb.h>
  36. #include <ipu_pixfmt.h>
  37. #include <asm/io.h>
  38. DECLARE_GLOBAL_DATA_PTR;
  39. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  40. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  41. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  42. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  43. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  44. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  45. #define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW | \
  46. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
  47. PAD_CTL_HYS)
  48. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  49. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  50. #define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
  51. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  52. #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
  53. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  54. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  55. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  56. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  57. #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  58. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  59. static int board_type = -1;
  60. #define BOARD_IS_MARSBOARD 0
  61. #define BOARD_IS_RIOTBOARD 1
  62. int dram_init(void)
  63. {
  64. gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  65. return 0;
  66. }
  67. static iomux_v3_cfg_t const uart2_pads[] = {
  68. MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  69. MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  70. };
  71. static void setup_iomux_uart(void)
  72. {
  73. imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  74. }
  75. iomux_v3_cfg_t const enet_pads[] = {
  76. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  77. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  78. /* GPIO16 -> AR8035 25MHz */
  79. MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
  80. MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL),
  81. MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  82. MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  83. MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  84. MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  85. MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  86. /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
  87. MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
  88. MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  89. MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
  90. MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
  91. MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  92. MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  93. MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
  94. /* AR8035 PHY Reset */
  95. MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
  96. /* AR8035 PHY Interrupt */
  97. MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  98. };
  99. static void setup_iomux_enet(void)
  100. {
  101. imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  102. /* Reset AR8035 PHY */
  103. gpio_direction_output(IMX_GPIO_NR(3, 31) , 0);
  104. mdelay(2);
  105. gpio_set_value(IMX_GPIO_NR(3, 31), 1);
  106. }
  107. int mx6_rgmii_rework(struct phy_device *phydev)
  108. {
  109. /* from linux/arch/arm/mach-imx/mach-imx6q.c :
  110. * Ar803x phy SmartEEE feature cause link status generates glitch,
  111. * which cause ethernet link down/up issue, so disable SmartEEE
  112. */
  113. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  114. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
  115. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
  116. return 0;
  117. }
  118. int board_phy_config(struct phy_device *phydev)
  119. {
  120. mx6_rgmii_rework(phydev);
  121. if (phydev->drv->config)
  122. phydev->drv->config(phydev);
  123. return 0;
  124. }
  125. iomux_v3_cfg_t const usdhc2_pads[] = {
  126. MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
  127. MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  128. MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  129. MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  130. MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  131. MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  132. MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
  133. MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  134. };
  135. iomux_v3_cfg_t const usdhc3_pads[] = {
  136. MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
  137. MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  138. MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  139. MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  140. MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  141. MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  142. };
  143. iomux_v3_cfg_t const riotboard_usdhc3_pads[] = {
  144. MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
  145. MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  146. };
  147. iomux_v3_cfg_t const usdhc4_pads[] = {
  148. MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
  149. MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  150. MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  151. MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  152. MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  153. MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  154. /* eMMC RST */
  155. MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
  156. };
  157. #ifdef CONFIG_FSL_ESDHC_IMX
  158. struct fsl_esdhc_cfg usdhc_cfg[3] = {
  159. {USDHC2_BASE_ADDR},
  160. {USDHC3_BASE_ADDR},
  161. {USDHC4_BASE_ADDR},
  162. };
  163. #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
  164. #define USDHC3_CD_GPIO IMX_GPIO_NR(7, 0)
  165. int board_mmc_getcd(struct mmc *mmc)
  166. {
  167. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  168. int ret = 0;
  169. switch (cfg->esdhc_base) {
  170. case USDHC2_BASE_ADDR:
  171. ret = !gpio_get_value(USDHC2_CD_GPIO);
  172. break;
  173. case USDHC3_BASE_ADDR:
  174. if (board_type == BOARD_IS_RIOTBOARD)
  175. ret = !gpio_get_value(USDHC3_CD_GPIO);
  176. else if (board_type == BOARD_IS_MARSBOARD)
  177. ret = 1; /* eMMC/uSDHC3 is always present */
  178. break;
  179. case USDHC4_BASE_ADDR:
  180. ret = 1; /* eMMC/uSDHC4 is always present */
  181. break;
  182. }
  183. return ret;
  184. }
  185. int board_mmc_init(bd_t *bis)
  186. {
  187. int ret;
  188. int i;
  189. /*
  190. * According to the board_mmc_init() the following map is done:
  191. * (U-Boot device node) (Physical Port)
  192. * ** RiOTboard :
  193. * mmc0 SDCard slot (bottom)
  194. * mmc1 uSDCard slot (top)
  195. * mmc2 eMMC
  196. * ** MarSBoard :
  197. * mmc0 uSDCard slot (bottom)
  198. * mmc1 eMMC
  199. */
  200. for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  201. switch (i) {
  202. case 0:
  203. imx_iomux_v3_setup_multiple_pads(
  204. usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  205. gpio_direction_input(USDHC2_CD_GPIO);
  206. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  207. usdhc_cfg[0].max_bus_width = 4;
  208. break;
  209. case 1:
  210. imx_iomux_v3_setup_multiple_pads(
  211. usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  212. if (board_type == BOARD_IS_RIOTBOARD) {
  213. imx_iomux_v3_setup_multiple_pads(
  214. riotboard_usdhc3_pads,
  215. ARRAY_SIZE(riotboard_usdhc3_pads));
  216. gpio_direction_input(USDHC3_CD_GPIO);
  217. } else {
  218. gpio_direction_output(IMX_GPIO_NR(7, 8) , 0);
  219. udelay(250);
  220. gpio_set_value(IMX_GPIO_NR(7, 8), 1);
  221. }
  222. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  223. usdhc_cfg[1].max_bus_width = 4;
  224. break;
  225. case 2:
  226. imx_iomux_v3_setup_multiple_pads(
  227. usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
  228. usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  229. usdhc_cfg[2].max_bus_width = 4;
  230. gpio_direction_output(IMX_GPIO_NR(6, 8) , 0);
  231. udelay(250);
  232. gpio_set_value(IMX_GPIO_NR(6, 8), 1);
  233. break;
  234. default:
  235. printf("Warning: you configured more USDHC controllers"
  236. "(%d) then supported by the board (%d)\n",
  237. i + 1, CONFIG_SYS_FSL_USDHC_NUM);
  238. return -EINVAL;
  239. }
  240. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  241. if (ret)
  242. return ret;
  243. }
  244. return 0;
  245. }
  246. #endif
  247. #ifdef CONFIG_MXC_SPI
  248. iomux_v3_cfg_t const ecspi1_pads[] = {
  249. MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  250. MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  251. MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  252. MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
  253. };
  254. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  255. {
  256. return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
  257. }
  258. static void setup_spi(void)
  259. {
  260. imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
  261. }
  262. #endif
  263. struct i2c_pads_info i2c_pad_info1 = {
  264. .scl = {
  265. .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL
  266. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  267. .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27
  268. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  269. .gp = IMX_GPIO_NR(5, 27)
  270. },
  271. .sda = {
  272. .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA
  273. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  274. .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26
  275. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  276. .gp = IMX_GPIO_NR(5, 26)
  277. }
  278. };
  279. struct i2c_pads_info i2c_pad_info2 = {
  280. .scl = {
  281. .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL
  282. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  283. .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12
  284. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  285. .gp = IMX_GPIO_NR(4, 12)
  286. },
  287. .sda = {
  288. .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA
  289. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  290. .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13
  291. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  292. .gp = IMX_GPIO_NR(4, 13)
  293. }
  294. };
  295. struct i2c_pads_info i2c_pad_info3 = {
  296. .scl = {
  297. .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL
  298. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  299. .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05
  300. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  301. .gp = IMX_GPIO_NR(1, 5)
  302. },
  303. .sda = {
  304. .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA
  305. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  306. .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06
  307. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  308. .gp = IMX_GPIO_NR(1, 6)
  309. }
  310. };
  311. iomux_v3_cfg_t const tft_pads_riot[] = {
  312. /* LCD_PWR_EN */
  313. MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  314. /* TOUCH_INT */
  315. MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
  316. /* LED_PWR_EN */
  317. MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
  318. /* BL LEVEL */
  319. MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
  320. };
  321. iomux_v3_cfg_t const tft_pads_mars[] = {
  322. /* LCD_PWR_EN */
  323. MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  324. /* TOUCH_INT */
  325. MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
  326. /* LED_PWR_EN */
  327. MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
  328. /* BL LEVEL (PWM4) */
  329. MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  330. };
  331. #if defined(CONFIG_VIDEO_IPUV3)
  332. static void enable_lvds(struct display_info_t const *dev)
  333. {
  334. struct iomuxc *iomux = (struct iomuxc *)
  335. IOMUXC_BASE_ADDR;
  336. setbits_le32(&iomux->gpr[2],
  337. IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT);
  338. /* set backlight level to ON */
  339. if (board_type == BOARD_IS_RIOTBOARD)
  340. gpio_direction_output(IMX_GPIO_NR(1, 18) , 1);
  341. else if (board_type == BOARD_IS_MARSBOARD)
  342. gpio_direction_output(IMX_GPIO_NR(2, 10) , 1);
  343. }
  344. static void disable_lvds(struct display_info_t const *dev)
  345. {
  346. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  347. /* set backlight level to OFF */
  348. if (board_type == BOARD_IS_RIOTBOARD)
  349. gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
  350. else if (board_type == BOARD_IS_MARSBOARD)
  351. gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
  352. clrbits_le32(&iomux->gpr[2],
  353. IOMUXC_GPR2_LVDS_CH0_MODE_MASK);
  354. }
  355. static void do_enable_hdmi(struct display_info_t const *dev)
  356. {
  357. disable_lvds(dev);
  358. imx_enable_hdmi_phy();
  359. }
  360. static int detect_i2c(struct display_info_t const *dev)
  361. {
  362. return (0 == i2c_set_bus_num(dev->bus)) &&
  363. (0 == i2c_probe(dev->addr));
  364. }
  365. struct display_info_t const displays[] = {{
  366. .bus = -1,
  367. .addr = 0,
  368. .pixfmt = IPU_PIX_FMT_RGB24,
  369. .detect = detect_hdmi,
  370. .enable = do_enable_hdmi,
  371. .mode = {
  372. .name = "HDMI",
  373. .refresh = 60,
  374. .xres = 1024,
  375. .yres = 768,
  376. .pixclock = 15385,
  377. .left_margin = 220,
  378. .right_margin = 40,
  379. .upper_margin = 21,
  380. .lower_margin = 7,
  381. .hsync_len = 60,
  382. .vsync_len = 10,
  383. .sync = FB_SYNC_EXT,
  384. .vmode = FB_VMODE_NONINTERLACED
  385. } }, {
  386. .bus = 2,
  387. .addr = 0x1,
  388. .pixfmt = IPU_PIX_FMT_LVDS666,
  389. .detect = detect_i2c,
  390. .enable = enable_lvds,
  391. .mode = {
  392. .name = "LCD8000-97C",
  393. .refresh = 60,
  394. .xres = 1024,
  395. .yres = 768,
  396. .pixclock = 15385,
  397. .left_margin = 100,
  398. .right_margin = 200,
  399. .upper_margin = 10,
  400. .lower_margin = 20,
  401. .hsync_len = 20,
  402. .vsync_len = 8,
  403. .sync = FB_SYNC_EXT,
  404. .vmode = FB_VMODE_NONINTERLACED
  405. } } };
  406. size_t display_count = ARRAY_SIZE(displays);
  407. static void setup_display(void)
  408. {
  409. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  410. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  411. int reg;
  412. enable_ipu_clock();
  413. imx_setup_hdmi();
  414. /* Turn on LDB0, IPU,IPU DI0 clocks */
  415. setbits_le32(&mxc_ccm->CCGR3,
  416. MXC_CCM_CCGR3_LDB_DI0_MASK);
  417. /* set LDB0 clk select to 011/011 */
  418. clrsetbits_le32(&mxc_ccm->cs2cdr,
  419. MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
  420. (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
  421. setbits_le32(&mxc_ccm->cscmr2,
  422. MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
  423. setbits_le32(&mxc_ccm->chsccdr,
  424. (CHSCCDR_CLK_SEL_LDB_DI0
  425. << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
  426. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  427. | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  428. | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  429. | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  430. | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  431. | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  432. | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
  433. | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  434. writel(reg, &iomux->gpr[2]);
  435. clrsetbits_le32(&iomux->gpr[3],
  436. IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
  437. IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
  438. IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  439. << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  440. }
  441. #endif /* CONFIG_VIDEO_IPUV3 */
  442. /*
  443. * Do not overwrite the console
  444. * Use always serial for U-Boot console
  445. */
  446. int overwrite_console(void)
  447. {
  448. return 1;
  449. }
  450. int board_eth_init(bd_t *bis)
  451. {
  452. setup_iomux_enet();
  453. return cpu_eth_init(bis);
  454. }
  455. int board_early_init_f(void)
  456. {
  457. u32 cputype = cpu_type(get_cpu_rev());
  458. switch (cputype) {
  459. case MXC_CPU_MX6SOLO:
  460. board_type = BOARD_IS_RIOTBOARD;
  461. break;
  462. case MXC_CPU_MX6D:
  463. board_type = BOARD_IS_MARSBOARD;
  464. break;
  465. }
  466. setup_iomux_uart();
  467. if (board_type == BOARD_IS_RIOTBOARD)
  468. imx_iomux_v3_setup_multiple_pads(
  469. tft_pads_riot, ARRAY_SIZE(tft_pads_riot));
  470. else if (board_type == BOARD_IS_MARSBOARD)
  471. imx_iomux_v3_setup_multiple_pads(
  472. tft_pads_mars, ARRAY_SIZE(tft_pads_mars));
  473. #if defined(CONFIG_VIDEO_IPUV3)
  474. /* power ON LCD */
  475. gpio_direction_output(IMX_GPIO_NR(1, 29) , 1);
  476. /* touch interrupt is an input */
  477. gpio_direction_input(IMX_GPIO_NR(6, 14));
  478. /* power ON backlight */
  479. gpio_direction_output(IMX_GPIO_NR(6, 15) , 1);
  480. /* set backlight level to off */
  481. if (board_type == BOARD_IS_RIOTBOARD)
  482. gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
  483. else if (board_type == BOARD_IS_MARSBOARD)
  484. gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
  485. setup_display();
  486. #endif
  487. return 0;
  488. }
  489. int board_init(void)
  490. {
  491. /* address of boot parameters */
  492. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  493. /* i2c1 : PMIC, Audio codec on RiOT, Expansion connector on MarS */
  494. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  495. /* i2c2 : HDMI EDID */
  496. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  497. /* i2c3 : LVDS, Expansion connector */
  498. setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
  499. #ifdef CONFIG_MXC_SPI
  500. setup_spi();
  501. #endif
  502. return 0;
  503. }
  504. #ifdef CONFIG_CMD_BMODE
  505. static const struct boot_mode riotboard_boot_modes[] = {
  506. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  507. {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  508. {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
  509. {NULL, 0},
  510. };
  511. static const struct boot_mode marsboard_boot_modes[] = {
  512. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  513. {"emmc", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  514. {NULL, 0},
  515. };
  516. #endif
  517. int board_late_init(void)
  518. {
  519. #ifdef CONFIG_CMD_BMODE
  520. if (board_type == BOARD_IS_RIOTBOARD)
  521. add_board_boot_modes(riotboard_boot_modes);
  522. else if (board_type == BOARD_IS_RIOTBOARD)
  523. add_board_boot_modes(marsboard_boot_modes);
  524. #endif
  525. return 0;
  526. }
  527. int checkboard(void)
  528. {
  529. puts("Board: ");
  530. if (board_type == BOARD_IS_MARSBOARD)
  531. puts("MarSBoard\n");
  532. else if (board_type == BOARD_IS_RIOTBOARD)
  533. puts("RIoTboard\n");
  534. else
  535. printf("unknown - cputype : %02x\n", cpu_type(get_cpu_rev()));
  536. return 0;
  537. }
  538. #ifdef CONFIG_SPL_BUILD
  539. #include <spl.h>
  540. void board_init_f(ulong dummy)
  541. {
  542. u32 cputype = cpu_type(get_cpu_rev());
  543. switch (cputype) {
  544. case MXC_CPU_MX6SOLO:
  545. board_type = BOARD_IS_RIOTBOARD;
  546. break;
  547. case MXC_CPU_MX6D:
  548. board_type = BOARD_IS_MARSBOARD;
  549. break;
  550. }
  551. arch_cpu_init();
  552. /* setup GP timer */
  553. timer_init();
  554. #ifdef CONFIG_SPL_SERIAL_SUPPORT
  555. setup_iomux_uart();
  556. preloader_console_init();
  557. #endif
  558. }
  559. void board_boot_order(u32 *spl_boot_list)
  560. {
  561. spl_boot_list[0] = BOOT_DEVICE_MMC1;
  562. }
  563. /*
  564. * In order to jump to standard u-boot shell, you have to connect pin 5 of J13
  565. * to pin 3 (ground).
  566. */
  567. int spl_start_uboot(void)
  568. {
  569. int gpio_key = IMX_GPIO_NR(4, 16);
  570. gpio_direction_input(gpio_key);
  571. if (gpio_get_value(gpio_key) == 0)
  572. return 1;
  573. else
  574. return 0;
  575. }
  576. #endif