MCR3000.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010-2017 CS Systemes d'Information
  4. * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
  5. * Christophe Leroy <christophe.leroy@c-s.fr>
  6. *
  7. * Board specific routines for the MCR3000 board
  8. */
  9. #include <common.h>
  10. #include <env.h>
  11. #include <hwconfig.h>
  12. #include <init.h>
  13. #include <mpc8xx.h>
  14. #include <fdt_support.h>
  15. #include <serial.h>
  16. #include <asm/io.h>
  17. #include <dm/uclass.h>
  18. #include <wdt.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. #define SDRAM_MAX_SIZE (32 * 1024 * 1024)
  21. static const uint cs1_dram_table_66[] = {
  22. /* DRAM - single read. (offset 0 in upm RAM) */
  23. 0x0F3DFC04, 0x0FEFBC04, 0x00BE7804, 0x0FFDF400,
  24. 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  25. /* DRAM - burst read. (offset 8 in upm RAM) */
  26. 0x0F3DFC04, 0x0FEFBC04, 0x00BF7C04, 0x00FFFC00,
  27. 0x00FFFC00, 0x00FEF800, 0x0FFDF400, 0x1FFFFC05,
  28. 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  29. 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  30. /* DRAM - single write. (offset 18 in upm RAM) */
  31. 0x0F3DFC04, 0x0FEFB800, 0x00BF7404, 0x0FFEF804,
  32. 0x0FFDF404, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
  33. /* DRAM - burst write. (offset 20 in upm RAM) */
  34. 0x0F3DFC04, 0x0FEFB800, 0x00BF7400, 0x00FFFC00,
  35. 0x00FFFC00, 0x00FFFC04, 0x0FFEF804, 0x0FFDF404,
  36. 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  37. 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  38. /* refresh (offset 30 in upm RAM) */
  39. 0x0FFDF404, 0x0FFEBC04, 0x0FFD7C84, 0x0FFFFC04,
  40. 0x0FFFFC04, 0x0FFFFC04, 0x1FFFFC85, 0xFFFFFFFF,
  41. /* init */
  42. 0x0FEEB874, 0x0FBD7474, 0x1FFFFC45, 0xFFFFFFFF,
  43. /* exception. (offset 3c in upm RAM) */
  44. 0xFFFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  45. };
  46. int ft_board_setup(void *blob, bd_t *bd)
  47. {
  48. const char *sync = "receive";
  49. ft_cpu_setup(blob, bd);
  50. /* BRG */
  51. do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency",
  52. bd->bi_busfreq, 1);
  53. /* MAC addr */
  54. fdt_fixup_ethernet(blob);
  55. /* Bus Frequency for CPM */
  56. do_fixup_by_path_u32(blob, "/soc", "bus-frequency", bd->bi_busfreq, 1);
  57. /* E1 interface - Set data rate */
  58. do_fixup_by_path_u32(blob, "/localbus/e1-wan", "data-rate", 2, 1);
  59. /* E1 interface - Set channel phase to 0 */
  60. do_fixup_by_path_u32(blob, "/localbus/e1-wan", "channel-phase", 0, 1);
  61. /* E1 interface - rising edge sync pulse transmit */
  62. do_fixup_by_path(blob, "/localbus/e1-wan", "rising-edge-sync-pulse",
  63. sync, strlen(sync), 1);
  64. return 0;
  65. }
  66. int checkboard(void)
  67. {
  68. serial_puts("BOARD: MCR3000 CSSI\n");
  69. return 0;
  70. }
  71. int dram_init(void)
  72. {
  73. immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
  74. memctl8xx_t __iomem *memctl = &immap->im_memctl;
  75. printf("UPMA init for SDRAM (CAS latency 2), ");
  76. printf("init address 0x%08x, size ", (int)dram_init);
  77. /* Configure UPMA for cs1 */
  78. upmconfig(UPMA, (uint *)cs1_dram_table_66,
  79. sizeof(cs1_dram_table_66) / sizeof(uint));
  80. udelay(10);
  81. out_be16(&memctl->memc_mptpr, 0x0200);
  82. out_be32(&memctl->memc_mamr, 0x14904000);
  83. udelay(10);
  84. out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);
  85. out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);
  86. udelay(10);
  87. out_be32(&memctl->memc_mcr, 0x80002830);
  88. out_be32(&memctl->memc_mar, 0x00000088);
  89. out_be32(&memctl->memc_mcr, 0x80002038);
  90. udelay(200);
  91. gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
  92. SDRAM_MAX_SIZE);
  93. return 0;
  94. }
  95. int misc_init_r(void)
  96. {
  97. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  98. iop8xx_t __iomem *iop = &immr->im_ioport;
  99. /* Set port C13 as GPIO (BTN_ACQ_AL) */
  100. clrbits_be16(&iop->iop_pcpar, 0x4);
  101. clrbits_be16(&iop->iop_pcdir, 0x4);
  102. /* if BTN_ACQ_AL is pressed then bootdelay is changed to 60 second */
  103. if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0)
  104. env_set("bootdelay", "60");
  105. return 0;
  106. }
  107. int board_early_init_f(void)
  108. {
  109. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  110. /*
  111. * Erase FPGA(s) for reboot
  112. */
  113. clrbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA down */
  114. setbits_be32(&immr->im_cpm.cp_pbdir, 0x00020000); /* PROGFPGA output */
  115. udelay(1); /* Wait more than 300ns */
  116. setbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA up */
  117. return 0;
  118. }
  119. int board_early_init_r(void)
  120. {
  121. struct udevice *watchdog_dev = NULL;
  122. if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
  123. puts("Cannot find watchdog!\n");
  124. } else {
  125. puts("Enabling watchdog.\n");
  126. wdt_start(watchdog_dev, 0xffff, 0);
  127. }
  128. return 0;
  129. }