xtfpga.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007 - 2013 Tensilica Inc.
  4. * (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <dm.h>
  9. #include <init.h>
  10. #include <dm/platform_data/net_ethoc.h>
  11. #include <env.h>
  12. #include <linux/ctype.h>
  13. #include <linux/string.h>
  14. #include <linux/stringify.h>
  15. #include <asm/global_data.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. /*
  18. * Check board idendity.
  19. * (Print information about the board to stdout.)
  20. */
  21. #if defined(CONFIG_XTFPGA_LX60)
  22. const char *board = "XT_AV60";
  23. const char *description = "Avnet Xilinx LX60 FPGA Evaluation Board / ";
  24. #elif defined(CONFIG_XTFPGA_LX110)
  25. const char *board = "XT_AV110";
  26. const char *description = "Avnet Xilinx Virtex-5 LX110 Evaluation Kit / ";
  27. #elif defined(CONFIG_XTFPGA_LX200)
  28. const char *board = "XT_AV200";
  29. const char *description = "Avnet Xilinx Virtex-4 LX200 Evaluation Kit / ";
  30. #elif defined(CONFIG_XTFPGA_ML605)
  31. const char *board = "XT_ML605";
  32. const char *description = "Xilinx Virtex-6 FPGA ML605 Evaluation Kit / ";
  33. #elif defined(CONFIG_XTFPGA_KC705)
  34. const char *board = "XT_KC705";
  35. const char *description = "Xilinx Kintex-7 FPGA KC705 Evaluation Kit / ";
  36. #else
  37. const char *board = "<unknown>";
  38. const char *description = "";
  39. #endif
  40. int checkboard(void)
  41. {
  42. printf("Board: %s: %sTensilica bitstream\n", board, description);
  43. return 0;
  44. }
  45. int dram_init_banksize(void)
  46. {
  47. gd->bd->bi_memstart = PHYSADDR(CONFIG_SYS_SDRAM_BASE);
  48. gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
  49. return 0;
  50. }
  51. int board_postclk_init(void)
  52. {
  53. /*
  54. * Obtain CPU clock frequency from board and cache in global
  55. * data structure (Hz). Return 0 on success (OK to continue),
  56. * else non-zero (hang).
  57. */
  58. #ifdef CONFIG_SYS_FPGAREG_FREQ
  59. gd->cpu_clk = (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ);
  60. #else
  61. /* early Tensilica bitstreams lack this reg, but most run at 50 MHz */
  62. gd->cpu_clk = 50000000UL;
  63. #endif
  64. return 0;
  65. }
  66. /*
  67. * Miscellaneous late initializations.
  68. * The environment has been set up, so we can set the Ethernet address.
  69. */
  70. int misc_init_r(void)
  71. {
  72. #ifdef CONFIG_CMD_NET
  73. /*
  74. * Initialize ethernet environment variables and board info.
  75. * Default MAC address comes from CONFIG_ETHADDR + DIP switches 1-6.
  76. */
  77. char *s = env_get("ethaddr");
  78. if (s == 0) {
  79. unsigned int x;
  80. char s[] = __stringify(CONFIG_ETHBASE);
  81. x = (*(volatile u32 *)CONFIG_SYS_FPGAREG_DIPSW)
  82. & FPGAREG_MAC_MASK;
  83. sprintf(&s[15], "%02x", x);
  84. env_set("ethaddr", s);
  85. }
  86. #endif /* CONFIG_CMD_NET */
  87. return 0;
  88. }
  89. U_BOOT_DEVICE(sysreset) = {
  90. .name = "xtfpga_sysreset",
  91. };
  92. static struct ethoc_eth_pdata ethoc_pdata = {
  93. .eth_pdata = {
  94. .iobase = CONFIG_SYS_ETHOC_BASE,
  95. },
  96. .packet_base = CONFIG_SYS_ETHOC_BUFFER_ADDR,
  97. };
  98. U_BOOT_DEVICE(ethoc) = {
  99. .name = "ethoc",
  100. .platdata = &ethoc_pdata,
  101. };