sama5d4ek.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Atmel
  4. * Bo Shen <voice.shen@atmel.com>
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/at91_common.h>
  10. #include <asm/arch/at91_rstc.h>
  11. #include <asm/arch/atmel_mpddrc.h>
  12. #include <asm/arch/gpio.h>
  13. #include <asm/arch/clk.h>
  14. #include <asm/arch/sama5d3_smc.h>
  15. #include <asm/arch/sama5d4.h>
  16. #include <debug_uart.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. #ifdef CONFIG_NAND_ATMEL
  19. static void sama5d4ek_nand_hw_init(void)
  20. {
  21. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  22. at91_periph_clk_enable(ATMEL_ID_SMC);
  23. /* Configure SMC CS3 for NAND */
  24. writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
  25. AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
  26. &smc->cs[3].setup);
  27. writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
  28. AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
  29. &smc->cs[3].pulse);
  30. writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  31. &smc->cs[3].cycle);
  32. writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
  33. AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) |
  34. AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)|
  35. AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
  36. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  37. AT91_SMC_MODE_EXNW_DISABLE |
  38. AT91_SMC_MODE_DBW_8 |
  39. AT91_SMC_MODE_TDF_CYCLE(3),
  40. &smc->cs[3].mode);
  41. at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */
  42. at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */
  43. at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */
  44. at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */
  45. at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */
  46. at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */
  47. at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */
  48. at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */
  49. at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */
  50. at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */
  51. at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */
  52. at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */
  53. at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */
  54. at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */
  55. }
  56. #endif
  57. #ifdef CONFIG_CMD_USB
  58. static void sama5d4ek_usb_hw_init(void)
  59. {
  60. at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
  61. at91_set_pio_output(AT91_PIO_PORTE, 12, 0);
  62. at91_set_pio_output(AT91_PIO_PORTE, 10, 0);
  63. }
  64. #endif
  65. #ifdef CONFIG_BOARD_LATE_INIT
  66. int board_late_init(void)
  67. {
  68. #ifdef CONFIG_DM_VIDEO
  69. at91_video_show_board_info();
  70. #endif
  71. return 0;
  72. }
  73. #endif
  74. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  75. static void sama5d4ek_serial3_hw_init(void)
  76. {
  77. at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */
  78. at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */
  79. /* Enable clock */
  80. at91_periph_clk_enable(ATMEL_ID_USART3);
  81. }
  82. void board_debug_uart_init(void)
  83. {
  84. sama5d4ek_serial3_hw_init();
  85. }
  86. #endif
  87. #ifdef CONFIG_BOARD_EARLY_INIT_F
  88. int board_early_init_f(void)
  89. {
  90. #ifdef CONFIG_DEBUG_UART
  91. debug_uart_init();
  92. #endif
  93. return 0;
  94. }
  95. #endif
  96. int board_init(void)
  97. {
  98. /* adress of boot parameters */
  99. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  100. #ifdef CONFIG_NAND_ATMEL
  101. sama5d4ek_nand_hw_init();
  102. #endif
  103. #ifdef CONFIG_CMD_USB
  104. sama5d4ek_usb_hw_init();
  105. #endif
  106. return 0;
  107. }
  108. int dram_init(void)
  109. {
  110. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  111. CONFIG_SYS_SDRAM_SIZE);
  112. return 0;
  113. }
  114. /* SPL */
  115. #ifdef CONFIG_SPL_BUILD
  116. void spl_board_init(void)
  117. {
  118. #if CONFIG_NAND_BOOT
  119. sama5d4ek_nand_hw_init();
  120. #endif
  121. }
  122. static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
  123. {
  124. ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
  125. ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
  126. ATMEL_MPDDRC_CR_NR_ROW_14 |
  127. ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
  128. ATMEL_MPDDRC_CR_NB_8BANKS |
  129. ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
  130. ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
  131. ddr2->rtr = 0x2b0;
  132. ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
  133. 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
  134. 3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
  135. 10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
  136. 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
  137. 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
  138. 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
  139. 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
  140. ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
  141. 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
  142. 25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
  143. 23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
  144. ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
  145. 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
  146. 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
  147. 2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
  148. 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
  149. }
  150. void mem_init(void)
  151. {
  152. struct atmel_mpddrc_config ddr2;
  153. const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
  154. u32 tmp;
  155. ddr2_conf(&ddr2);
  156. /* Enable MPDDR clock */
  157. at91_periph_clk_enable(ATMEL_ID_MPDDRC);
  158. at91_system_clk_enable(AT91_PMC_DDR);
  159. tmp = ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE;
  160. writel(tmp, &mpddr->rd_data_path);
  161. tmp = readl(&mpddr->io_calibr);
  162. tmp = (tmp & ~(ATMEL_MPDDRC_IO_CALIBR_RDIV |
  163. ATMEL_MPDDRC_IO_CALIBR_TZQIO |
  164. ATMEL_MPDDRC_IO_CALIBR_CALCODEP |
  165. ATMEL_MPDDRC_IO_CALIBR_CALCODEN)) |
  166. ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_52 |
  167. ATMEL_MPDDRC_IO_CALIBR_TZQIO_(8) |
  168. ATMEL_MPDDRC_IO_CALIBR_EN_CALIB;
  169. writel(tmp, &mpddr->io_calibr);
  170. /* DDRAM2 Controller initialize */
  171. ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
  172. }
  173. void at91_pmc_init(void)
  174. {
  175. u32 tmp;
  176. tmp = AT91_PMC_PLLAR_29 |
  177. AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
  178. AT91_PMC_PLLXR_MUL(87) |
  179. AT91_PMC_PLLXR_DIV(1);
  180. at91_plla_init(tmp);
  181. at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0));
  182. tmp = AT91_PMC_MCKR_H32MXDIV |
  183. AT91_PMC_MCKR_PLLADIV_2 |
  184. AT91_PMC_MCKR_MDIV_3 |
  185. AT91_PMC_MCKR_CSS_PLLA;
  186. at91_mck_init(tmp);
  187. }
  188. #endif