sama5d4_xplained.c 5.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Atmel
  4. * Bo Shen <voice.shen@atmel.com>
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/at91_common.h>
  10. #include <asm/arch/at91_rstc.h>
  11. #include <asm/arch/atmel_mpddrc.h>
  12. #include <asm/arch/gpio.h>
  13. #include <asm/arch/clk.h>
  14. #include <asm/arch/sama5d3_smc.h>
  15. #include <asm/arch/sama5d4.h>
  16. #include <debug_uart.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. extern void at91_pda_detect(void);
  19. #ifdef CONFIG_NAND_ATMEL
  20. static void sama5d4_xplained_nand_hw_init(void)
  21. {
  22. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  23. at91_periph_clk_enable(ATMEL_ID_SMC);
  24. /* Configure SMC CS3 for NAND */
  25. writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
  26. AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
  27. &smc->cs[3].setup);
  28. writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
  29. AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
  30. &smc->cs[3].pulse);
  31. writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  32. &smc->cs[3].cycle);
  33. writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
  34. AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) |
  35. AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)|
  36. AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
  37. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  38. AT91_SMC_MODE_EXNW_DISABLE |
  39. AT91_SMC_MODE_DBW_8 |
  40. AT91_SMC_MODE_TDF_CYCLE(3),
  41. &smc->cs[3].mode);
  42. at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */
  43. at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */
  44. at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */
  45. at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */
  46. at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */
  47. at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */
  48. at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */
  49. at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */
  50. at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */
  51. at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */
  52. at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */
  53. at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */
  54. at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */
  55. at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */
  56. }
  57. #endif
  58. #ifdef CONFIG_CMD_USB
  59. static void sama5d4_xplained_usb_hw_init(void)
  60. {
  61. at91_set_pio_output(AT91_PIO_PORTE, 11, 1);
  62. at91_set_pio_output(AT91_PIO_PORTE, 14, 1);
  63. }
  64. #endif
  65. #ifdef CONFIG_BOARD_LATE_INIT
  66. int board_late_init(void)
  67. {
  68. at91_pda_detect();
  69. #ifdef CONFIG_DM_VIDEO
  70. at91_video_show_board_info();
  71. #endif
  72. return 0;
  73. }
  74. #endif
  75. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  76. static void sama5d4_xplained_serial3_hw_init(void)
  77. {
  78. at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */
  79. at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */
  80. /* Enable clock */
  81. at91_periph_clk_enable(ATMEL_ID_USART3);
  82. }
  83. void board_debug_uart_init(void)
  84. {
  85. sama5d4_xplained_serial3_hw_init();
  86. }
  87. #endif
  88. #ifdef CONFIG_BOARD_EARLY_INIT_F
  89. int board_early_init_f(void)
  90. {
  91. #ifdef CONFIG_DEBUG_UART
  92. debug_uart_init();
  93. #endif
  94. return 0;
  95. }
  96. #endif
  97. #define AT24MAC_MAC_OFFSET 0x9a
  98. #ifdef CONFIG_MISC_INIT_R
  99. int misc_init_r(void)
  100. {
  101. #ifdef CONFIG_I2C_EEPROM
  102. at91_set_ethaddr(AT24MAC_MAC_OFFSET);
  103. #endif
  104. return 0;
  105. }
  106. #endif
  107. int board_init(void)
  108. {
  109. /* adress of boot parameters */
  110. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  111. #ifdef CONFIG_NAND_ATMEL
  112. sama5d4_xplained_nand_hw_init();
  113. #endif
  114. #ifdef CONFIG_CMD_USB
  115. sama5d4_xplained_usb_hw_init();
  116. #endif
  117. return 0;
  118. }
  119. int dram_init(void)
  120. {
  121. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  122. CONFIG_SYS_SDRAM_SIZE);
  123. return 0;
  124. }
  125. /* SPL */
  126. #ifdef CONFIG_SPL_BUILD
  127. void spl_board_init(void)
  128. {
  129. #if CONFIG_NAND_BOOT
  130. sama5d4_xplained_nand_hw_init();
  131. #endif
  132. }
  133. static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
  134. {
  135. ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
  136. ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
  137. ATMEL_MPDDRC_CR_NR_ROW_14 |
  138. ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
  139. ATMEL_MPDDRC_CR_NB_8BANKS |
  140. ATMEL_MPDDRC_CR_NDQS_DISABLED |
  141. ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
  142. ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
  143. ddr2->rtr = 0x2b0;
  144. ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
  145. 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
  146. 3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
  147. 10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
  148. 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
  149. 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
  150. 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
  151. 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
  152. ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
  153. 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
  154. 25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
  155. 23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
  156. ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
  157. 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
  158. 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
  159. 2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
  160. 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
  161. }
  162. void mem_init(void)
  163. {
  164. struct atmel_mpddrc_config ddr2;
  165. ddr2_conf(&ddr2);
  166. /* Enable MPDDR clock */
  167. at91_periph_clk_enable(ATMEL_ID_MPDDRC);
  168. at91_system_clk_enable(AT91_PMC_DDR);
  169. /* DDRAM2 Controller initialize */
  170. ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
  171. }
  172. void at91_pmc_init(void)
  173. {
  174. u32 tmp;
  175. tmp = AT91_PMC_PLLAR_29 |
  176. AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
  177. AT91_PMC_PLLXR_MUL(87) |
  178. AT91_PMC_PLLXR_DIV(1);
  179. at91_plla_init(tmp);
  180. at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0));
  181. tmp = AT91_PMC_MCKR_H32MXDIV |
  182. AT91_PMC_MCKR_PLLADIV_2 |
  183. AT91_PMC_MCKR_MDIV_3 |
  184. AT91_PMC_MCKR_CSS_PLLA;
  185. at91_mck_init(tmp);
  186. }
  187. #endif