sama5d2_ptc_ek.c 3.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Microchip Corporation
  4. * Wenyou Yang <wenyou.yang@microchip.com>
  5. */
  6. #include <common.h>
  7. #include <debug_uart.h>
  8. #include <dm.h>
  9. #include <i2c.h>
  10. #include <init.h>
  11. #include <nand.h>
  12. #include <version.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/at91_common.h>
  15. #include <asm/arch/atmel_pio4.h>
  16. #include <asm/arch/atmel_mpddrc.h>
  17. #include <asm/arch/atmel_sdhci.h>
  18. #include <asm/arch/clk.h>
  19. #include <asm/arch/gpio.h>
  20. #include <asm/arch/sama5d2.h>
  21. #include <asm/arch/sama5d2_smc.h>
  22. extern void at91_pda_detect(void);
  23. DECLARE_GLOBAL_DATA_PTR;
  24. #ifdef CONFIG_NAND_ATMEL
  25. static void board_nand_hw_init(void)
  26. {
  27. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  28. at91_periph_clk_enable(ATMEL_ID_HSMC);
  29. /* Configure SMC CS3 for NAND */
  30. writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
  31. AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
  32. &smc->cs[3].setup);
  33. writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(4) |
  34. AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
  35. &smc->cs[3].pulse);
  36. writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(5),
  37. &smc->cs[3].cycle);
  38. writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
  39. AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) |
  40. AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3) |
  41. AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
  42. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  43. AT91_SMC_MODE_EXNW_DISABLE |
  44. AT91_SMC_MODE_DBW_8 |
  45. AT91_SMC_MODE_TDF_CYCLE(3),
  46. &smc->cs[3].mode);
  47. atmel_pio4_set_b_periph(AT91_PIO_PORTA, 22, ATMEL_PIO_DRVSTR_ME); /* D0 */
  48. atmel_pio4_set_b_periph(AT91_PIO_PORTA, 23, ATMEL_PIO_DRVSTR_ME); /* D1 */
  49. atmel_pio4_set_b_periph(AT91_PIO_PORTA, 24, ATMEL_PIO_DRVSTR_ME); /* D2 */
  50. atmel_pio4_set_b_periph(AT91_PIO_PORTA, 25, ATMEL_PIO_DRVSTR_ME); /* D3 */
  51. atmel_pio4_set_b_periph(AT91_PIO_PORTA, 26, ATMEL_PIO_DRVSTR_ME); /* D4 */
  52. atmel_pio4_set_b_periph(AT91_PIO_PORTA, 27, ATMEL_PIO_DRVSTR_ME); /* D5 */
  53. atmel_pio4_set_b_periph(AT91_PIO_PORTA, 28, ATMEL_PIO_DRVSTR_ME); /* D6 */
  54. atmel_pio4_set_b_periph(AT91_PIO_PORTA, 29, ATMEL_PIO_DRVSTR_ME); /* D7 */
  55. atmel_pio4_set_b_periph(AT91_PIO_PORTB, 2, 0); /* RE */
  56. atmel_pio4_set_b_periph(AT91_PIO_PORTA, 30, 0); /* WE */
  57. atmel_pio4_set_b_periph(AT91_PIO_PORTA, 31, ATMEL_PIO_PUEN_MASK); /* NCS */
  58. atmel_pio4_set_b_periph(AT91_PIO_PORTC, 8, ATMEL_PIO_PUEN_MASK); /* RDY */
  59. atmel_pio4_set_b_periph(AT91_PIO_PORTB, 0, ATMEL_PIO_PUEN_MASK); /* ALE */
  60. atmel_pio4_set_b_periph(AT91_PIO_PORTB, 1, ATMEL_PIO_PUEN_MASK); /* CLE */
  61. }
  62. #endif
  63. #ifdef CONFIG_BOARD_LATE_INIT
  64. int board_late_init(void)
  65. {
  66. at91_pda_detect();
  67. return 0;
  68. }
  69. #endif
  70. static void board_usb_hw_init(void)
  71. {
  72. atmel_pio4_set_pio_output(AT91_PIO_PORTB, 12, ATMEL_PIO_PUEN_MASK);
  73. }
  74. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  75. static void board_uart0_hw_init(void)
  76. {
  77. atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK); /* URXD0 */
  78. atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
  79. at91_periph_clk_enable(ATMEL_ID_UART0);
  80. }
  81. void board_debug_uart_init(void)
  82. {
  83. board_uart0_hw_init();
  84. }
  85. #endif
  86. #ifdef CONFIG_BOARD_EARLY_INIT_F
  87. int board_early_init_f(void)
  88. {
  89. #ifdef CONFIG_DEBUG_UART
  90. debug_uart_init();
  91. #endif
  92. return 0;
  93. }
  94. #endif
  95. int board_init(void)
  96. {
  97. /* address of boot parameters */
  98. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  99. #ifdef CONFIG_NAND_ATMEL
  100. board_nand_hw_init();
  101. #endif
  102. #ifdef CONFIG_CMD_USB
  103. board_usb_hw_init();
  104. #endif
  105. return 0;
  106. }
  107. int dram_init(void)
  108. {
  109. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  110. CONFIG_SYS_SDRAM_SIZE);
  111. return 0;
  112. }
  113. #define AT24MAC_MAC_OFFSET 0xfa
  114. #ifdef CONFIG_MISC_INIT_R
  115. int misc_init_r(void)
  116. {
  117. #ifdef CONFIG_I2C_EEPROM
  118. at91_set_ethaddr(AT24MAC_MAC_OFFSET);
  119. #endif
  120. return 0;
  121. }
  122. #endif