sama5d2_icp.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Microchip Technology, Inc.
  4. * Eugen Hristev <eugen.hristev@microchip.com>
  5. */
  6. #include <common.h>
  7. #include <debug_uart.h>
  8. #include <init.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/at91_common.h>
  11. #include <asm/arch/atmel_pio4.h>
  12. #include <asm/arch/atmel_mpddrc.h>
  13. #include <asm/arch/atmel_sdhci.h>
  14. #include <asm/arch/clk.h>
  15. #include <asm/arch/gpio.h>
  16. #include <asm/arch/sama5d2.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. int board_late_init(void)
  19. {
  20. return 0;
  21. }
  22. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  23. static void board_uart0_hw_init(void)
  24. {
  25. atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK); /* URXD0 */
  26. atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
  27. at91_periph_clk_enable(ATMEL_ID_UART0);
  28. }
  29. void board_debug_uart_init(void)
  30. {
  31. board_uart0_hw_init();
  32. }
  33. #endif
  34. int board_early_init_f(void)
  35. {
  36. #ifdef CONFIG_DEBUG_UART
  37. debug_uart_init();
  38. #endif
  39. return 0;
  40. }
  41. int board_init(void)
  42. {
  43. /* address of boot parameters */
  44. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  45. return 0;
  46. }
  47. int dram_init(void)
  48. {
  49. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  50. CONFIG_SYS_SDRAM_SIZE);
  51. return 0;
  52. }
  53. #define MAC24AA_MAC_OFFSET 0xfa
  54. int misc_init_r(void)
  55. {
  56. #ifdef CONFIG_I2C_EEPROM
  57. at91_set_ethaddr(MAC24AA_MAC_OFFSET);
  58. #endif
  59. return 0;
  60. }
  61. /* SPL */
  62. #ifdef CONFIG_SPL_BUILD
  63. /* must set PB25 low to enable the CAN transceivers */
  64. static void board_can_stdby_dis(void)
  65. {
  66. atmel_pio4_set_pio_output(AT91_PIO_PORTB, 25, 0);
  67. }
  68. static void board_leds_init(void)
  69. {
  70. atmel_pio4_set_pio_output(AT91_PIO_PORTB, 0, 0); /* RED */
  71. atmel_pio4_set_pio_output(AT91_PIO_PORTB, 1, 1); /* GREEN */
  72. atmel_pio4_set_pio_output(AT91_PIO_PORTA, 31, 0); /* BLUE */
  73. }
  74. /* deassert reset lines for external periph in case of warm reboot */
  75. static void board_reset_additional_periph(void)
  76. {
  77. atmel_pio4_set_pio_output(AT91_PIO_PORTB, 16, 0); /* LAN9252_RST */
  78. atmel_pio4_set_pio_output(AT91_PIO_PORTC, 2, 0); /* HSIC_RST */
  79. atmel_pio4_set_pio_output(AT91_PIO_PORTC, 17, 0); /* USB2534_RST */
  80. atmel_pio4_set_pio_output(AT91_PIO_PORTD, 4, 0); /* KSZ8563_RST */
  81. }
  82. static void board_start_additional_periph(void)
  83. {
  84. atmel_pio4_set_pio_output(AT91_PIO_PORTB, 16, 1); /* LAN9252_RST */
  85. atmel_pio4_set_pio_output(AT91_PIO_PORTC, 2, 1); /* HSIC_RST */
  86. atmel_pio4_set_pio_output(AT91_PIO_PORTC, 17, 1); /* USB2534_RST */
  87. atmel_pio4_set_pio_output(AT91_PIO_PORTD, 4, 1); /* KSZ8563_RST */
  88. }
  89. #ifdef CONFIG_SD_BOOT
  90. void spl_mmc_init(void)
  91. {
  92. atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0); /* CMD */
  93. atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0); /* DAT0 */
  94. atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0); /* DAT1 */
  95. atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0); /* DAT2 */
  96. atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0); /* DAT3 */
  97. atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0); /* CK */
  98. atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CD */
  99. at91_periph_clk_enable(ATMEL_ID_SDMMC0);
  100. }
  101. #endif
  102. void spl_board_init(void)
  103. {
  104. #ifdef CONFIG_SD_BOOT
  105. spl_mmc_init();
  106. #endif
  107. board_reset_additional_periph();
  108. board_can_stdby_dis();
  109. board_leds_init();
  110. }
  111. void spl_display_print(void)
  112. {
  113. }
  114. void spl_board_prepare_for_boot(void)
  115. {
  116. board_start_additional_periph();
  117. }
  118. static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
  119. {
  120. ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
  121. ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
  122. ATMEL_MPDDRC_CR_NR_ROW_14 |
  123. ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
  124. ATMEL_MPDDRC_CR_DIC_DS |
  125. ATMEL_MPDDRC_CR_NB_8BANKS |
  126. ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
  127. ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
  128. ddrc->rtr = 0x298;
  129. ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
  130. (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
  131. (3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
  132. (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
  133. (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
  134. (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
  135. (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
  136. (4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
  137. ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
  138. (29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
  139. (0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
  140. (10 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
  141. ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
  142. (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
  143. (0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
  144. (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
  145. (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
  146. }
  147. void mem_init(void)
  148. {
  149. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  150. struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
  151. struct atmel_mpddrc_config ddrc_config;
  152. u32 reg;
  153. ddrc_conf(&ddrc_config);
  154. at91_periph_clk_enable(ATMEL_ID_MPDDRC);
  155. writel(AT91_PMC_DDR, &pmc->scer);
  156. reg = readl(&mpddrc->io_calibr);
  157. reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
  158. reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
  159. reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
  160. reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
  161. writel(reg, &mpddrc->io_calibr);
  162. writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE,
  163. &mpddrc->rd_data_path);
  164. ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
  165. writel(0x5355, &mpddrc->cal_mr4);
  166. writel(64, &mpddrc->tim_cal);
  167. }
  168. void at91_pmc_init(void)
  169. {
  170. u32 tmp;
  171. /*
  172. * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
  173. * so we need to slow down and configure MCKR accordingly.
  174. * This is why we have a special flavor of the switching function.
  175. */
  176. tmp = AT91_PMC_MCKR_PLLADIV_2 |
  177. AT91_PMC_MCKR_MDIV_3 |
  178. AT91_PMC_MCKR_CSS_MAIN;
  179. at91_mck_init_down(tmp);
  180. tmp = AT91_PMC_PLLAR_29 |
  181. AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
  182. AT91_PMC_PLLXR_MUL(82) |
  183. AT91_PMC_PLLXR_DIV(1);
  184. at91_plla_init(tmp);
  185. tmp = AT91_PMC_MCKR_H32MXDIV |
  186. AT91_PMC_MCKR_PLLADIV_2 |
  187. AT91_PMC_MCKR_MDIV_3 |
  188. AT91_PMC_MCKR_CSS_PLLA;
  189. at91_mck_init(tmp);
  190. }
  191. #endif