sama5d27_som1_ek.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Microchip Corporation
  4. * Wenyou.Yang <wenyou.yang@microchip.com>
  5. */
  6. #include <common.h>
  7. #include <debug_uart.h>
  8. #include <init.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/at91_common.h>
  11. #include <asm/arch/atmel_pio4.h>
  12. #include <asm/arch/atmel_mpddrc.h>
  13. #include <asm/arch/atmel_sdhci.h>
  14. #include <asm/arch/clk.h>
  15. #include <asm/arch/gpio.h>
  16. #include <asm/arch/sama5d2.h>
  17. extern void at91_pda_detect(void);
  18. DECLARE_GLOBAL_DATA_PTR;
  19. static void board_usb_hw_init(void)
  20. {
  21. atmel_pio4_set_pio_output(AT91_PIO_PORTA, 27, 1);
  22. }
  23. #ifdef CONFIG_BOARD_LATE_INIT
  24. int board_late_init(void)
  25. {
  26. #ifdef CONFIG_DM_VIDEO
  27. at91_video_show_board_info();
  28. #endif
  29. at91_pda_detect();
  30. return 0;
  31. }
  32. #endif
  33. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  34. static void board_uart1_hw_init(void)
  35. {
  36. atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, ATMEL_PIO_PUEN_MASK); /* URXD1 */
  37. atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0); /* UTXD1 */
  38. at91_periph_clk_enable(ATMEL_ID_UART1);
  39. }
  40. void board_debug_uart_init(void)
  41. {
  42. board_uart1_hw_init();
  43. }
  44. #endif
  45. #ifdef CONFIG_BOARD_EARLY_INIT_F
  46. int board_early_init_f(void)
  47. {
  48. #ifdef CONFIG_DEBUG_UART
  49. debug_uart_init();
  50. #endif
  51. return 0;
  52. }
  53. #endif
  54. int board_init(void)
  55. {
  56. /* address of boot parameters */
  57. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  58. #ifdef CONFIG_CMD_USB
  59. board_usb_hw_init();
  60. #endif
  61. return 0;
  62. }
  63. int dram_init(void)
  64. {
  65. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  66. CONFIG_SYS_SDRAM_SIZE);
  67. return 0;
  68. }
  69. #define MAC24AA_MAC_OFFSET 0xfa
  70. #ifdef CONFIG_MISC_INIT_R
  71. int misc_init_r(void)
  72. {
  73. #ifdef CONFIG_I2C_EEPROM
  74. at91_set_ethaddr(MAC24AA_MAC_OFFSET);
  75. #endif
  76. return 0;
  77. }
  78. #endif
  79. /* SPL */
  80. #ifdef CONFIG_SPL_BUILD
  81. void spl_board_init(void)
  82. {
  83. }
  84. static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
  85. {
  86. ddrc->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
  87. ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
  88. ATMEL_MPDDRC_CR_NR_ROW_13 |
  89. ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
  90. ATMEL_MPDDRC_CR_DIC_DS |
  91. ATMEL_MPDDRC_CR_ZQ_LONG |
  92. ATMEL_MPDDRC_CR_NB_8BANKS |
  93. ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
  94. ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
  95. ddrc->rtr = 0x511;
  96. ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
  97. (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
  98. (3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
  99. (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
  100. (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
  101. (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
  102. (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
  103. (2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
  104. ddrc->tpr1 = ((22 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
  105. (23 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
  106. (200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
  107. (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
  108. ddrc->tpr2 = ((2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
  109. (8 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
  110. (4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
  111. (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
  112. (8 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
  113. }
  114. void mem_init(void)
  115. {
  116. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  117. struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
  118. struct atmel_mpddrc_config ddrc_config;
  119. u32 reg;
  120. ddrc_conf(&ddrc_config);
  121. at91_periph_clk_enable(ATMEL_ID_MPDDRC);
  122. writel(AT91_PMC_DDR, &pmc->scer);
  123. reg = readl(&mpddrc->io_calibr);
  124. reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
  125. reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
  126. reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
  127. reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(101);
  128. writel(reg, &mpddrc->io_calibr);
  129. writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE,
  130. &mpddrc->rd_data_path);
  131. ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
  132. writel(0x3, &mpddrc->cal_mr4);
  133. writel(64, &mpddrc->tim_cal);
  134. }
  135. void at91_pmc_init(void)
  136. {
  137. u32 tmp;
  138. /*
  139. * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
  140. * so we need to slow down and configure MCKR accordingly.
  141. * This is why we have a special flavor of the switching function.
  142. */
  143. tmp = AT91_PMC_MCKR_PLLADIV_2 |
  144. AT91_PMC_MCKR_MDIV_3 |
  145. AT91_PMC_MCKR_CSS_MAIN;
  146. at91_mck_init_down(tmp);
  147. tmp = AT91_PMC_PLLAR_29 |
  148. AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
  149. AT91_PMC_PLLXR_MUL(40) |
  150. AT91_PMC_PLLXR_DIV(1);
  151. at91_plla_init(tmp);
  152. tmp = AT91_PMC_MCKR_H32MXDIV |
  153. AT91_PMC_MCKR_PLLADIV_2 |
  154. AT91_PMC_MCKR_MDIV_3 |
  155. AT91_PMC_MCKR_CSS_PLLA;
  156. at91_mck_init(tmp);
  157. }
  158. #endif