dms-ba16.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016 Timesys Corporation
  4. * Copyright 2016 Advantech Corporation
  5. * Copyright 2012 Freescale Semiconductor, Inc.
  6. */
  7. #include <init.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <asm/arch/iomux.h>
  11. #include <asm/arch/mx6-pins.h>
  12. #include <linux/errno.h>
  13. #include <asm/gpio.h>
  14. #include <asm/mach-imx/mxc_i2c.h>
  15. #include <asm/mach-imx/iomux-v3.h>
  16. #include <asm/mach-imx/boot_mode.h>
  17. #include <asm/mach-imx/video.h>
  18. #include <mmc.h>
  19. #include <fsl_esdhc_imx.h>
  20. #include <miiphy.h>
  21. #include <netdev.h>
  22. #include <asm/arch/mxc_hdmi.h>
  23. #include <asm/arch/crm_regs.h>
  24. #include <asm/io.h>
  25. #include <asm/arch/sys_proto.h>
  26. #include <i2c.h>
  27. #include <input.h>
  28. #include <pwm.h>
  29. DECLARE_GLOBAL_DATA_PTR;
  30. #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  31. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  32. PAD_CTL_HYS)
  33. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  34. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  35. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  36. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  37. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  38. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  39. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  40. PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  41. #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  42. PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  43. #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  44. PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
  45. #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  46. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  47. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  48. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  49. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  50. #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  51. int dram_init(void)
  52. {
  53. gd->ram_size = imx_ddr_size();
  54. return 0;
  55. }
  56. static iomux_v3_cfg_t const uart3_pads[] = {
  57. MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  58. MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  59. MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  60. MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  61. };
  62. static iomux_v3_cfg_t const uart4_pads[] = {
  63. MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  64. MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  65. };
  66. static iomux_v3_cfg_t const enet_pads[] = {
  67. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  68. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  69. MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  70. MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  71. MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  72. MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  73. MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  74. MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  75. MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  76. MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  77. MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  78. MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  79. MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  80. MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  81. MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  82. /* AR8033 PHY Reset */
  83. MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
  84. };
  85. static void setup_iomux_enet(void)
  86. {
  87. imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  88. /* Reset AR8033 PHY */
  89. gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
  90. mdelay(10);
  91. gpio_set_value(IMX_GPIO_NR(1, 28), 1);
  92. mdelay(1);
  93. }
  94. static iomux_v3_cfg_t const usdhc2_pads[] = {
  95. MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  96. MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  97. MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  98. MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  99. MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  100. MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  101. MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
  102. };
  103. static iomux_v3_cfg_t const usdhc3_pads[] = {
  104. MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  105. MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  106. MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  107. MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  108. MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  109. MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  110. MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  111. MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  112. MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  113. MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  114. MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  115. };
  116. static iomux_v3_cfg_t const usdhc4_pads[] = {
  117. MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  118. MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  119. MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  120. MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  121. MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  122. MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  123. MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  124. MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  125. MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  126. MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  127. MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  128. MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
  129. };
  130. static iomux_v3_cfg_t const ecspi1_pads[] = {
  131. MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  132. MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  133. MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  134. MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
  135. };
  136. static struct i2c_pads_info i2c_pad_info1 = {
  137. .scl = {
  138. .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
  139. .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
  140. .gp = IMX_GPIO_NR(5, 27)
  141. },
  142. .sda = {
  143. .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
  144. .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
  145. .gp = IMX_GPIO_NR(5, 26)
  146. }
  147. };
  148. static struct i2c_pads_info i2c_pad_info2 = {
  149. .scl = {
  150. .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
  151. .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
  152. .gp = IMX_GPIO_NR(4, 12)
  153. },
  154. .sda = {
  155. .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
  156. .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
  157. .gp = IMX_GPIO_NR(4, 13)
  158. }
  159. };
  160. static struct i2c_pads_info i2c_pad_info3 = {
  161. .scl = {
  162. .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
  163. .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
  164. .gp = IMX_GPIO_NR(1, 3)
  165. },
  166. .sda = {
  167. .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
  168. .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
  169. .gp = IMX_GPIO_NR(1, 6)
  170. }
  171. };
  172. #ifdef CONFIG_MXC_SPI
  173. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  174. {
  175. return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
  176. }
  177. static void setup_spi(void)
  178. {
  179. imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
  180. }
  181. #endif
  182. static iomux_v3_cfg_t const pcie_pads[] = {
  183. MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
  184. MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
  185. };
  186. static void setup_pcie(void)
  187. {
  188. imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
  189. }
  190. static void setup_iomux_uart(void)
  191. {
  192. imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
  193. imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
  194. }
  195. #ifdef CONFIG_FSL_ESDHC_IMX
  196. struct fsl_esdhc_cfg usdhc_cfg[3] = {
  197. {USDHC2_BASE_ADDR},
  198. {USDHC3_BASE_ADDR},
  199. {USDHC4_BASE_ADDR},
  200. };
  201. #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
  202. #define USDHC4_CD_GPIO IMX_GPIO_NR(6, 11)
  203. int board_mmc_getcd(struct mmc *mmc)
  204. {
  205. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  206. int ret = 0;
  207. switch (cfg->esdhc_base) {
  208. case USDHC2_BASE_ADDR:
  209. ret = !gpio_get_value(USDHC2_CD_GPIO);
  210. break;
  211. case USDHC3_BASE_ADDR:
  212. ret = 1; /* eMMC is always present */
  213. break;
  214. case USDHC4_BASE_ADDR:
  215. ret = !gpio_get_value(USDHC4_CD_GPIO);
  216. break;
  217. }
  218. return ret;
  219. }
  220. int board_mmc_init(bd_t *bis)
  221. {
  222. int ret;
  223. int i;
  224. for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  225. switch (i) {
  226. case 0:
  227. imx_iomux_v3_setup_multiple_pads(
  228. usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  229. gpio_direction_input(USDHC2_CD_GPIO);
  230. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  231. break;
  232. case 1:
  233. imx_iomux_v3_setup_multiple_pads(
  234. usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  235. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  236. break;
  237. case 2:
  238. imx_iomux_v3_setup_multiple_pads(
  239. usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
  240. gpio_direction_input(USDHC4_CD_GPIO);
  241. usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  242. break;
  243. default:
  244. printf("Warning: you configured more USDHC controllers\n"
  245. "(%d) then supported by the board (%d)\n",
  246. i + 1, CONFIG_SYS_FSL_USDHC_NUM);
  247. return -EINVAL;
  248. }
  249. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  250. if (ret)
  251. return ret;
  252. }
  253. return 0;
  254. }
  255. #endif
  256. static int mx6_rgmii_rework(struct phy_device *phydev)
  257. {
  258. /* set device address 0x7 */
  259. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  260. /* offset 0x8016: CLK_25M Clock Select */
  261. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  262. /* enable register write, no post increment, address 0x7 */
  263. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  264. /* set to 125 MHz from local PLL source */
  265. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
  266. /* set debug port address: SerDes Test and System Mode Control */
  267. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  268. /* enable rgmii tx clock delay */
  269. /* set the reserved bits to avoid board specific voltage peak issue*/
  270. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
  271. return 0;
  272. }
  273. int board_phy_config(struct phy_device *phydev)
  274. {
  275. mx6_rgmii_rework(phydev);
  276. if (phydev->drv->config)
  277. phydev->drv->config(phydev);
  278. return 0;
  279. }
  280. #if defined(CONFIG_VIDEO_IPUV3)
  281. static iomux_v3_cfg_t const backlight_pads[] = {
  282. /* Power for LVDS Display */
  283. MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
  284. #define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
  285. /* Backlight enable for LVDS display */
  286. MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
  287. #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
  288. /* backlight PWM brightness control */
  289. MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
  290. };
  291. static void do_enable_hdmi(struct display_info_t const *dev)
  292. {
  293. imx_enable_hdmi_phy();
  294. }
  295. int board_cfb_skip(void)
  296. {
  297. gpio_direction_output(LVDS_POWER_GP, 1);
  298. return 0;
  299. }
  300. static int detect_baseboard(struct display_info_t const *dev)
  301. {
  302. return 0 == dev->addr;
  303. }
  304. struct display_info_t const displays[] = {{
  305. .bus = -1,
  306. .addr = 0,
  307. .pixfmt = IPU_PIX_FMT_RGB24,
  308. .detect = detect_baseboard,
  309. .enable = NULL,
  310. .mode = {
  311. .name = "SHARP-LQ156M1LG21",
  312. .refresh = 60,
  313. .xres = 1920,
  314. .yres = 1080,
  315. .pixclock = 7851,
  316. .left_margin = 100,
  317. .right_margin = 40,
  318. .upper_margin = 30,
  319. .lower_margin = 3,
  320. .hsync_len = 10,
  321. .vsync_len = 2,
  322. .sync = FB_SYNC_EXT,
  323. .vmode = FB_VMODE_NONINTERLACED
  324. } }, {
  325. .bus = -1,
  326. .addr = 3,
  327. .pixfmt = IPU_PIX_FMT_RGB24,
  328. .detect = detect_hdmi,
  329. .enable = do_enable_hdmi,
  330. .mode = {
  331. .name = "HDMI",
  332. .refresh = 60,
  333. .xres = 1024,
  334. .yres = 768,
  335. .pixclock = 15385,
  336. .left_margin = 220,
  337. .right_margin = 40,
  338. .upper_margin = 21,
  339. .lower_margin = 7,
  340. .hsync_len = 60,
  341. .vsync_len = 10,
  342. .sync = FB_SYNC_EXT,
  343. .vmode = FB_VMODE_NONINTERLACED
  344. } } };
  345. size_t display_count = ARRAY_SIZE(displays);
  346. static void setup_display(void)
  347. {
  348. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  349. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  350. clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
  351. imx_setup_hdmi();
  352. /* Set LDB_DI0 as clock source for IPU_DI0 */
  353. clrsetbits_le32(&mxc_ccm->chsccdr,
  354. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
  355. (CHSCCDR_CLK_SEL_LDB_DI0 <<
  356. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
  357. /* Turn on IPU LDB DI0 clocks */
  358. setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
  359. enable_ipu_clock();
  360. writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
  361. IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
  362. IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
  363. IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
  364. IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
  365. IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
  366. IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
  367. IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
  368. IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
  369. IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
  370. &iomux->gpr[2]);
  371. clrsetbits_le32(&iomux->gpr[3],
  372. IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
  373. IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
  374. IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
  375. (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
  376. IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
  377. /* backlights off until needed */
  378. imx_iomux_v3_setup_multiple_pads(backlight_pads,
  379. ARRAY_SIZE(backlight_pads));
  380. gpio_direction_input(LVDS_POWER_GP);
  381. gpio_direction_input(LVDS_BACKLIGHT_GP);
  382. }
  383. #endif /* CONFIG_VIDEO_IPUV3 */
  384. /*
  385. * Do not overwrite the console
  386. * Use always serial for U-Boot console
  387. */
  388. int overwrite_console(void)
  389. {
  390. return 1;
  391. }
  392. int board_eth_init(bd_t *bis)
  393. {
  394. setup_iomux_enet();
  395. setup_pcie();
  396. return cpu_eth_init(bis);
  397. }
  398. static iomux_v3_cfg_t const misc_pads[] = {
  399. MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  400. MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL),
  401. MX6_PAD_EIM_CS0__GPIO2_IO23 | MUX_PAD_CTRL(NC_PAD_CTRL),
  402. MX6_PAD_EIM_CS1__GPIO2_IO24 | MUX_PAD_CTRL(NC_PAD_CTRL),
  403. MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL),
  404. MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL),
  405. MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL),
  406. };
  407. #define SUS_S3_OUT IMX_GPIO_NR(4, 11)
  408. #define WIFI_EN IMX_GPIO_NR(6, 14)
  409. int setup_ba16_sata(void)
  410. {
  411. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  412. int ret;
  413. ret = enable_sata_clock();
  414. if (ret)
  415. return ret;
  416. clrsetbits_le32(&iomuxc_regs->gpr[13],
  417. IOMUXC_GPR13_SATA_MASK,
  418. IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
  419. |IOMUXC_GPR13_SATA_PHY_7_SATA2M
  420. |IOMUXC_GPR13_SATA_SPEED_3G
  421. |(1<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
  422. |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
  423. |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16
  424. |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB
  425. |IOMUXC_GPR13_SATA_PHY_2_TX_1P133V
  426. |IOMUXC_GPR13_SATA_PHY_1_SLOW);
  427. return 0;
  428. }
  429. int board_early_init_f(void)
  430. {
  431. imx_iomux_v3_setup_multiple_pads(misc_pads,
  432. ARRAY_SIZE(misc_pads));
  433. setup_iomux_uart();
  434. #if defined(CONFIG_VIDEO_IPUV3)
  435. /* Set LDB clock to PLL2 PFD0 */
  436. select_ldb_di_clock_source(MXC_PLL2_PFD0_CLK);
  437. #endif
  438. return 0;
  439. }
  440. int board_init(void)
  441. {
  442. gpio_direction_output(SUS_S3_OUT, 1);
  443. gpio_direction_output(WIFI_EN, 1);
  444. #if defined(CONFIG_VIDEO_IPUV3)
  445. setup_display();
  446. #endif
  447. /* address of boot parameters */
  448. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  449. #ifdef CONFIG_MXC_SPI
  450. setup_spi();
  451. #endif
  452. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  453. setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  454. setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
  455. return 0;
  456. }
  457. #ifdef CONFIG_CMD_BMODE
  458. static const struct boot_mode board_boot_modes[] = {
  459. /* 4 bit bus width */
  460. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  461. {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  462. {NULL, 0},
  463. };
  464. #endif
  465. void pmic_init(void)
  466. {
  467. #define DA9063_ADDR 0x58
  468. #define BCORE2_CONF 0x9D
  469. #define BCORE1_CONF 0x9E
  470. #define BPRO_CONF 0x9F
  471. #define BIO_CONF 0xA0
  472. #define BMEM_CONF 0xA1
  473. #define BPERI_CONF 0xA2
  474. #define MODE_BIT_H 7
  475. #define MODE_BIT_L 6
  476. uchar val;
  477. i2c_set_bus_num(2);
  478. i2c_read(DA9063_ADDR, BCORE2_CONF, 1, &val, 1);
  479. val |= (1 << MODE_BIT_H);
  480. val &= ~(1 << MODE_BIT_L);
  481. i2c_write(DA9063_ADDR, BCORE2_CONF , 1, &val, 1);
  482. i2c_read(DA9063_ADDR, BCORE1_CONF, 1, &val, 1);
  483. val |= (1 << MODE_BIT_H);
  484. val &= ~(1 << MODE_BIT_L);
  485. i2c_write(DA9063_ADDR, BCORE1_CONF , 1, &val, 1);
  486. i2c_read(DA9063_ADDR, BPRO_CONF, 1, &val, 1);
  487. val |= (1 << MODE_BIT_H);
  488. val &= ~(1 << MODE_BIT_L);
  489. i2c_write(DA9063_ADDR, BPRO_CONF , 1, &val, 1);
  490. i2c_read(DA9063_ADDR, BIO_CONF, 1, &val, 1);
  491. val |= (1 << MODE_BIT_H);
  492. val &= ~(1 << MODE_BIT_L);
  493. i2c_write(DA9063_ADDR, BIO_CONF , 1, &val, 1);
  494. i2c_read(DA9063_ADDR, BMEM_CONF, 1, &val, 1);
  495. val |= (1 << MODE_BIT_H);
  496. val &= ~(1 << MODE_BIT_L);
  497. i2c_write(DA9063_ADDR, BMEM_CONF , 1, &val, 1);
  498. i2c_read(DA9063_ADDR, BPERI_CONF, 1, &val, 1);
  499. val |= (1 << MODE_BIT_H);
  500. val &= ~(1 << MODE_BIT_L);
  501. i2c_write(DA9063_ADDR, BPERI_CONF , 1, &val, 1);
  502. }
  503. int board_late_init(void)
  504. {
  505. #ifdef CONFIG_CMD_BMODE
  506. add_board_boot_modes(board_boot_modes);
  507. #endif
  508. #if defined(CONFIG_VIDEO_IPUV3)
  509. /*
  510. * We need at least 200ms between power on and backlight on
  511. * as per specifications from CHI MEI
  512. */
  513. mdelay(250);
  514. /* enable backlight PWM 1 */
  515. pwm_init(0, 0, 0);
  516. /* duty cycle 5000000ns, period: 5000000ns */
  517. pwm_config(0, 5000000, 5000000);
  518. /* Backlight Power */
  519. gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
  520. pwm_enable(0);
  521. #endif
  522. #ifdef CONFIG_SATA
  523. setup_ba16_sata();
  524. #endif
  525. /* board specific pmic init */
  526. pmic_init();
  527. return 0;
  528. }
  529. int checkboard(void)
  530. {
  531. printf("BOARD: %s\n", CONFIG_BOARD_NAME);
  532. return 0;
  533. }