turris_omnia.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
  4. * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz>
  5. *
  6. * Derived from the code for
  7. * Marvell/db-88f6820-gp by Stefan Roese <sr@denx.de>
  8. */
  9. #include <common.h>
  10. #include <env.h>
  11. #include <i2c.h>
  12. #include <init.h>
  13. #include <miiphy.h>
  14. #include <netdev.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/cpu.h>
  17. #include <asm/arch/soc.h>
  18. #include <dm/uclass.h>
  19. #include <fdt_support.h>
  20. #include <time.h>
  21. #include <u-boot/crc.h>
  22. # include <atsha204a-i2c.h>
  23. #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
  24. #include <../serdes/a38x/high_speed_env_spec.h>
  25. DECLARE_GLOBAL_DATA_PTR;
  26. #define OMNIA_I2C_BUS_NAME "i2c@11000->i2cmux@70->i2c@0"
  27. #define OMNIA_I2C_MCU_CHIP_ADDR 0x2a
  28. #define OMNIA_I2C_MCU_CHIP_LEN 1
  29. #define OMNIA_I2C_EEPROM_CHIP_ADDR 0x54
  30. #define OMNIA_I2C_EEPROM_CHIP_LEN 2
  31. #define OMNIA_I2C_EEPROM_MAGIC 0x0341a034
  32. enum mcu_commands {
  33. CMD_GET_STATUS_WORD = 0x01,
  34. CMD_GET_RESET = 0x09,
  35. CMD_WATCHDOG_STATE = 0x0b,
  36. };
  37. enum status_word_bits {
  38. CARD_DET_STSBIT = 0x0010,
  39. MSATA_IND_STSBIT = 0x0020,
  40. };
  41. #define OMNIA_ATSHA204_OTP_VERSION 0
  42. #define OMNIA_ATSHA204_OTP_SERIAL 1
  43. #define OMNIA_ATSHA204_OTP_MAC0 3
  44. #define OMNIA_ATSHA204_OTP_MAC1 4
  45. /*
  46. * Those values and defines are taken from the Marvell U-Boot version
  47. * "u-boot-2013.01-2014_T3.0"
  48. */
  49. #define OMNIA_GPP_OUT_ENA_LOW \
  50. (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
  51. BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
  52. BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
  53. #define OMNIA_GPP_OUT_ENA_MID \
  54. (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
  55. BIT(16) | BIT(17) | BIT(18)))
  56. #define OMNIA_GPP_OUT_VAL_LOW 0x0
  57. #define OMNIA_GPP_OUT_VAL_MID 0x0
  58. #define OMNIA_GPP_POL_LOW 0x0
  59. #define OMNIA_GPP_POL_MID 0x0
  60. static struct serdes_map board_serdes_map_pex[] = {
  61. {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  62. {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  63. {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  64. {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  65. {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  66. {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
  67. };
  68. static struct serdes_map board_serdes_map_sata[] = {
  69. {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  70. {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  71. {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  72. {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  73. {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  74. {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
  75. };
  76. static struct udevice *omnia_get_i2c_chip(const char *name, uint addr,
  77. uint offset_len)
  78. {
  79. struct udevice *bus, *dev;
  80. int ret;
  81. ret = uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_BUS_NAME, &bus);
  82. if (ret) {
  83. printf("Cannot get I2C bus %s: uclass_get_device_by_name failed: %i\n",
  84. OMNIA_I2C_BUS_NAME, ret);
  85. return NULL;
  86. }
  87. ret = i2c_get_chip(bus, addr, offset_len, &dev);
  88. if (ret) {
  89. printf("Cannot get %s I2C chip: i2c_get_chip failed: %i\n",
  90. name, ret);
  91. return NULL;
  92. }
  93. return dev;
  94. }
  95. static int omnia_mcu_read(u8 cmd, void *buf, int len)
  96. {
  97. struct udevice *chip;
  98. chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
  99. OMNIA_I2C_MCU_CHIP_LEN);
  100. if (!chip)
  101. return -ENODEV;
  102. return dm_i2c_read(chip, cmd, buf, len);
  103. }
  104. #ifndef CONFIG_SPL_BUILD
  105. static int omnia_mcu_write(u8 cmd, const void *buf, int len)
  106. {
  107. struct udevice *chip;
  108. chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
  109. OMNIA_I2C_MCU_CHIP_LEN);
  110. if (!chip)
  111. return -ENODEV;
  112. return dm_i2c_write(chip, cmd, buf, len);
  113. }
  114. static bool disable_mcu_watchdog(void)
  115. {
  116. int ret;
  117. puts("Disabling MCU watchdog... ");
  118. ret = omnia_mcu_write(CMD_WATCHDOG_STATE, "\x00", 1);
  119. if (ret) {
  120. printf("omnia_mcu_write failed: %i\n", ret);
  121. return false;
  122. }
  123. puts("disabled\n");
  124. return true;
  125. }
  126. #endif
  127. static bool omnia_detect_sata(void)
  128. {
  129. int ret;
  130. u16 stsword;
  131. puts("MiniPCIe/mSATA card detection... ");
  132. ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword));
  133. if (ret) {
  134. printf("omnia_mcu_read failed: %i, defaulting to MiniPCIe card\n",
  135. ret);
  136. return false;
  137. }
  138. if (!(stsword & CARD_DET_STSBIT)) {
  139. puts("none\n");
  140. return false;
  141. }
  142. if (stsword & MSATA_IND_STSBIT)
  143. puts("mSATA\n");
  144. else
  145. puts("MiniPCIe\n");
  146. return stsword & MSATA_IND_STSBIT ? true : false;
  147. }
  148. int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
  149. {
  150. if (omnia_detect_sata()) {
  151. *serdes_map_array = board_serdes_map_sata;
  152. *count = ARRAY_SIZE(board_serdes_map_sata);
  153. } else {
  154. *serdes_map_array = board_serdes_map_pex;
  155. *count = ARRAY_SIZE(board_serdes_map_pex);
  156. }
  157. return 0;
  158. }
  159. struct omnia_eeprom {
  160. u32 magic;
  161. u32 ramsize;
  162. char region[4];
  163. u32 crc;
  164. };
  165. static bool omnia_read_eeprom(struct omnia_eeprom *oep)
  166. {
  167. struct udevice *chip;
  168. u32 crc;
  169. int ret;
  170. chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR,
  171. OMNIA_I2C_EEPROM_CHIP_LEN);
  172. if (!chip)
  173. return false;
  174. ret = dm_i2c_read(chip, 0, (void *)oep, sizeof(*oep));
  175. if (ret) {
  176. printf("dm_i2c_read failed: %i, cannot read EEPROM\n", ret);
  177. return false;
  178. }
  179. if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) {
  180. printf("bad EEPROM magic number (%08x, should be %08x)\n",
  181. oep->magic, OMNIA_I2C_EEPROM_MAGIC);
  182. return false;
  183. }
  184. crc = crc32(0, (void *)oep, sizeof(*oep) - 4);
  185. if (crc != oep->crc) {
  186. printf("bad EEPROM CRC (stored %08x, computed %08x)\n",
  187. oep->crc, crc);
  188. return false;
  189. }
  190. return true;
  191. }
  192. static int omnia_get_ram_size_gb(void)
  193. {
  194. static int ram_size;
  195. struct omnia_eeprom oep;
  196. if (!ram_size) {
  197. /* Get the board config from EEPROM */
  198. if (omnia_read_eeprom(&oep)) {
  199. debug("Memory config in EEPROM: 0x%02x\n", oep.ramsize);
  200. if (oep.ramsize == 0x2)
  201. ram_size = 2;
  202. else
  203. ram_size = 1;
  204. } else {
  205. /* Hardcoded fallback */
  206. puts("Memory config from EEPROM read failed!\n");
  207. puts("Falling back to default 1 GiB!\n");
  208. ram_size = 1;
  209. }
  210. }
  211. return ram_size;
  212. }
  213. /*
  214. * Define the DDR layout / topology here in the board file. This will
  215. * be used by the DDR3 init code in the SPL U-Boot version to configure
  216. * the DDR3 controller.
  217. */
  218. static struct mv_ddr_topology_map board_topology_map_1g = {
  219. DEBUG_LEVEL_ERROR,
  220. 0x1, /* active interfaces */
  221. /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
  222. { { { {0x1, 0, 0, 0},
  223. {0x1, 0, 0, 0},
  224. {0x1, 0, 0, 0},
  225. {0x1, 0, 0, 0},
  226. {0x1, 0, 0, 0} },
  227. SPEED_BIN_DDR_1600K, /* speed_bin */
  228. MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
  229. MV_DDR_DIE_CAP_4GBIT, /* mem_size */
  230. MV_DDR_FREQ_800, /* frequency */
  231. 0, 0, /* cas_wl cas_l */
  232. MV_DDR_TEMP_NORMAL, /* temperature */
  233. MV_DDR_TIM_2T} }, /* timing */
  234. BUS_MASK_32BIT, /* Busses mask */
  235. MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
  236. { {0} }, /* raw spd data */
  237. {0} /* timing parameters */
  238. };
  239. static struct mv_ddr_topology_map board_topology_map_2g = {
  240. DEBUG_LEVEL_ERROR,
  241. 0x1, /* active interfaces */
  242. /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
  243. { { { {0x1, 0, 0, 0},
  244. {0x1, 0, 0, 0},
  245. {0x1, 0, 0, 0},
  246. {0x1, 0, 0, 0},
  247. {0x1, 0, 0, 0} },
  248. SPEED_BIN_DDR_1600K, /* speed_bin */
  249. MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
  250. MV_DDR_DIE_CAP_8GBIT, /* mem_size */
  251. MV_DDR_FREQ_800, /* frequency */
  252. 0, 0, /* cas_wl cas_l */
  253. MV_DDR_TEMP_NORMAL, /* temperature */
  254. MV_DDR_TIM_2T} }, /* timing */
  255. BUS_MASK_32BIT, /* Busses mask */
  256. MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
  257. { {0} }, /* raw spd data */
  258. {0} /* timing parameters */
  259. };
  260. struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
  261. {
  262. if (omnia_get_ram_size_gb() == 2)
  263. return &board_topology_map_2g;
  264. else
  265. return &board_topology_map_1g;
  266. }
  267. #ifndef CONFIG_SPL_BUILD
  268. static int set_regdomain(void)
  269. {
  270. struct omnia_eeprom oep;
  271. char rd[3] = {' ', ' ', 0};
  272. if (omnia_read_eeprom(&oep))
  273. memcpy(rd, &oep.region, 2);
  274. else
  275. puts("EEPROM regdomain read failed.\n");
  276. printf("Regdomain set to %s\n", rd);
  277. return env_set("regdomain", rd);
  278. }
  279. /*
  280. * default factory reset bootcommand on Omnia first sets all the front LEDs
  281. * to green and then tries to load the rescue image from SPI flash memory and
  282. * boot it
  283. */
  284. #define OMNIA_FACTORY_RESET_BOOTCMD \
  285. "i2c dev 2; " \
  286. "i2c mw 0x2a.1 0x3 0x1c 1; " \
  287. "i2c mw 0x2a.1 0x4 0x1c 1; " \
  288. "mw.l 0x01000000 0x00ff000c; " \
  289. "i2c write 0x01000000 0x2a.1 0x5 4 -s; " \
  290. "setenv bootargs \"earlyprintk console=ttyS0,115200" \
  291. " omniarescue=$omnia_reset\"; " \
  292. "sf probe; " \
  293. "sf read 0x1000000 0x100000 0x700000; " \
  294. "bootm 0x1000000; " \
  295. "bootz 0x1000000"
  296. static void handle_reset_button(void)
  297. {
  298. int ret;
  299. u8 reset_status;
  300. ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1);
  301. if (ret) {
  302. printf("omnia_mcu_read failed: %i, reset status unknown!\n",
  303. ret);
  304. return;
  305. }
  306. env_set_ulong("omnia_reset", reset_status);
  307. if (reset_status) {
  308. printf("RESET button was pressed, overwriting bootcmd!\n");
  309. env_set("bootcmd", OMNIA_FACTORY_RESET_BOOTCMD);
  310. }
  311. }
  312. #endif
  313. int board_early_init_f(void)
  314. {
  315. /* Configure MPP */
  316. writel(0x11111111, MVEBU_MPP_BASE + 0x00);
  317. writel(0x11111111, MVEBU_MPP_BASE + 0x04);
  318. writel(0x11244011, MVEBU_MPP_BASE + 0x08);
  319. writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
  320. writel(0x22200002, MVEBU_MPP_BASE + 0x10);
  321. writel(0x30042022, MVEBU_MPP_BASE + 0x14);
  322. writel(0x55550555, MVEBU_MPP_BASE + 0x18);
  323. writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
  324. /* Set GPP Out value */
  325. writel(OMNIA_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
  326. writel(OMNIA_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
  327. /* Set GPP Polarity */
  328. writel(OMNIA_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
  329. writel(OMNIA_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
  330. /* Set GPP Out Enable */
  331. writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
  332. writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
  333. return 0;
  334. }
  335. int board_init(void)
  336. {
  337. /* address of boot parameters */
  338. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  339. #ifndef CONFIG_SPL_BUILD
  340. disable_mcu_watchdog();
  341. #endif
  342. return 0;
  343. }
  344. int board_late_init(void)
  345. {
  346. #ifndef CONFIG_SPL_BUILD
  347. set_regdomain();
  348. handle_reset_button();
  349. #endif
  350. pci_init();
  351. return 0;
  352. }
  353. static struct udevice *get_atsha204a_dev(void)
  354. {
  355. static struct udevice *dev;
  356. if (dev)
  357. return dev;
  358. if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) {
  359. puts("Cannot find ATSHA204A on I2C bus!\n");
  360. dev = NULL;
  361. }
  362. return dev;
  363. }
  364. int checkboard(void)
  365. {
  366. u32 version_num, serial_num;
  367. int err = 1;
  368. struct udevice *dev = get_atsha204a_dev();
  369. if (dev) {
  370. err = atsha204a_wakeup(dev);
  371. if (err)
  372. goto out;
  373. err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
  374. OMNIA_ATSHA204_OTP_VERSION,
  375. (u8 *)&version_num);
  376. if (err)
  377. goto out;
  378. err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
  379. OMNIA_ATSHA204_OTP_SERIAL,
  380. (u8 *)&serial_num);
  381. if (err)
  382. goto out;
  383. atsha204a_sleep(dev);
  384. }
  385. out:
  386. printf("Turris Omnia:\n");
  387. printf(" RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024);
  388. if (err)
  389. printf(" Serial Number: unknown\n");
  390. else
  391. printf(" Serial Number: %08X%08X\n", be32_to_cpu(version_num),
  392. be32_to_cpu(serial_num));
  393. return 0;
  394. }
  395. static void increment_mac(u8 *mac)
  396. {
  397. int i;
  398. for (i = 5; i >= 3; i--) {
  399. mac[i] += 1;
  400. if (mac[i])
  401. break;
  402. }
  403. }
  404. int misc_init_r(void)
  405. {
  406. int err;
  407. struct udevice *dev = get_atsha204a_dev();
  408. u8 mac0[4], mac1[4], mac[6];
  409. if (!dev)
  410. goto out;
  411. err = atsha204a_wakeup(dev);
  412. if (err)
  413. goto out;
  414. err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
  415. OMNIA_ATSHA204_OTP_MAC0, mac0);
  416. if (err)
  417. goto out;
  418. err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
  419. OMNIA_ATSHA204_OTP_MAC1, mac1);
  420. if (err)
  421. goto out;
  422. atsha204a_sleep(dev);
  423. mac[0] = mac0[1];
  424. mac[1] = mac0[2];
  425. mac[2] = mac0[3];
  426. mac[3] = mac1[1];
  427. mac[4] = mac1[2];
  428. mac[5] = mac1[3];
  429. if (is_valid_ethaddr(mac))
  430. eth_env_set_enetaddr("eth1addr", mac);
  431. increment_mac(mac);
  432. if (is_valid_ethaddr(mac))
  433. eth_env_set_enetaddr("eth2addr", mac);
  434. increment_mac(mac);
  435. if (is_valid_ethaddr(mac))
  436. eth_env_set_enetaddr("ethaddr", mac);
  437. out:
  438. return 0;
  439. }