ucp1020.c 8.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013-2019 Arcturus Networks, Inc.
  4. * https://www.arcturusnetworks.com/products/ucp1020/
  5. * by Oleksandr G Zhadan et al.
  6. * based on board/freescale/p1_p2_rdb_pc/spl.c
  7. * original copyright follows:
  8. * Copyright 2013 Freescale Semiconductor, Inc.
  9. */
  10. #include <common.h>
  11. #include <command.h>
  12. #include <env.h>
  13. #include <hwconfig.h>
  14. #include <init.h>
  15. #include <pci.h>
  16. #include <i2c.h>
  17. #include <miiphy.h>
  18. #include <linux/libfdt.h>
  19. #include <fdt_support.h>
  20. #include <fsl_mdio.h>
  21. #include <tsec.h>
  22. #include <ioports.h>
  23. #include <netdev.h>
  24. #include <micrel.h>
  25. #include <spi_flash.h>
  26. #include <mmc.h>
  27. #include <linux/ctype.h>
  28. #include <asm/fsl_serdes.h>
  29. #include <asm/gpio.h>
  30. #include <asm/processor.h>
  31. #include <asm/mmu.h>
  32. #include <asm/cache.h>
  33. #include <asm/immap_85xx.h>
  34. #include <asm/fsl_pci.h>
  35. #include <fsl_ddr_sdram.h>
  36. #include <asm/io.h>
  37. #include <asm/fsl_law.h>
  38. #include <asm/fsl_lbc.h>
  39. #include <asm/mp.h>
  40. #include "ucp1020.h"
  41. void spi_set_speed(struct spi_slave *slave, uint hz)
  42. {
  43. /* TO DO: It's actially have to be in spi/ */
  44. }
  45. /*
  46. * To be compatible with cmd_gpio
  47. */
  48. int name_to_gpio(const char *name)
  49. {
  50. int gpio = 31 - simple_strtoul(name, NULL, 10);
  51. if (gpio < 16)
  52. gpio = -1;
  53. return gpio;
  54. }
  55. void board_gpio_init(void)
  56. {
  57. int i;
  58. char envname[8], *val;
  59. for (i = 0; i < GPIO_MAX_NUM; i++) {
  60. sprintf(envname, "GPIO%d", i);
  61. val = env_get(envname);
  62. if (val) {
  63. char direction = toupper(val[0]);
  64. char level = toupper(val[1]);
  65. if (direction == 'I') {
  66. gpio_direction_input(i);
  67. } else {
  68. if (direction == 'O') {
  69. if (level == '1')
  70. gpio_direction_output(i, 1);
  71. else
  72. gpio_direction_output(i, 0);
  73. }
  74. }
  75. }
  76. }
  77. val = env_get("PCIE_OFF");
  78. if (val) {
  79. gpio_direction_input(GPIO_PCIE1_EN);
  80. gpio_direction_input(GPIO_PCIE2_EN);
  81. } else {
  82. gpio_direction_output(GPIO_PCIE1_EN, 1);
  83. gpio_direction_output(GPIO_PCIE2_EN, 1);
  84. }
  85. val = env_get("SDHC_CDWP_OFF");
  86. if (!val) {
  87. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  88. setbits_be32(&gur->pmuxcr,
  89. (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
  90. }
  91. }
  92. int board_early_init_f(void)
  93. {
  94. return 0; /* Just in case. Could be disable in config file */
  95. }
  96. int checkboard(void)
  97. {
  98. printf("Board: %s\n", CONFIG_BOARDNAME_LOCAL);
  99. board_gpio_init();
  100. #ifdef CONFIG_MMC
  101. printf("SD/MMC: 4-bit Mode\n");
  102. #endif
  103. return 0;
  104. }
  105. #ifdef CONFIG_PCI
  106. void pci_init_board(void)
  107. {
  108. fsl_pcie_init_board(0);
  109. }
  110. #endif
  111. int board_early_init_r(void)
  112. {
  113. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  114. const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  115. /*
  116. * Remap Boot flash region to caching-inhibited
  117. * so that flash can be erased properly.
  118. */
  119. /* Flush d-cache and invalidate i-cache of any FLASH data */
  120. flush_dcache();
  121. invalidate_icache();
  122. /* invalidate existing TLB entry for flash */
  123. disable_tlb(flash_esel);
  124. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
  125. MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, /* perms, wimge */
  126. 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
  127. return 0;
  128. }
  129. int board_phy_config(struct phy_device *phydev)
  130. {
  131. #if defined(CONFIG_PHY_MICREL_KSZ9021)
  132. int regval;
  133. static int cnt;
  134. if (cnt++ == 0)
  135. printf("PHYs address [");
  136. if (phydev->addr == TSEC1_PHY_ADDR || phydev->addr == TSEC3_PHY_ADDR) {
  137. regval =
  138. ksz9021_phy_extended_read(phydev,
  139. MII_KSZ9021_EXT_STRAP_STATUS);
  140. /*
  141. * min rx data delay
  142. */
  143. ksz9021_phy_extended_write(phydev,
  144. MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
  145. 0x6666);
  146. /*
  147. * max rx/tx clock delay, min rx/tx control
  148. */
  149. ksz9021_phy_extended_write(phydev,
  150. MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
  151. 0xf6f6);
  152. printf("0x%x", (regval & 0x1f));
  153. } else {
  154. printf("0x%x", (TSEC2_PHY_ADDR & 0x1f));
  155. }
  156. if (cnt == 3)
  157. printf("] ");
  158. else
  159. printf(",");
  160. #endif
  161. #if defined(CONFIG_PHY_MICREL_KSZ9031_DEBUG)
  162. regval = ksz9031_phy_extended_read(phydev, 2, 0x01, 0x4000);
  163. if (regval >= 0)
  164. printf(" (ADDR 0x%x) ", regval & 0x1f);
  165. #endif
  166. return 0;
  167. }
  168. int last_stage_init(void)
  169. {
  170. static char newkernelargs[256];
  171. static u8 id1[16];
  172. static u8 id2;
  173. #ifdef CONFIG_MMC
  174. struct mmc *mmc;
  175. #endif
  176. char *sval, *kval;
  177. if (i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 7, 1, &id1[0], 2) < 0) {
  178. printf("Error reading i2c IDT6V49205B information!\n");
  179. } else {
  180. printf("IDT6V49205B(0x%02x): ready\n", id1[1]);
  181. i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
  182. if (!(id1[1] & 0x02)) {
  183. id1[1] |= 0x02;
  184. i2c_write(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
  185. asm("nop; nop");
  186. }
  187. }
  188. if (i2c_read(CONFIG_SYS_I2C_NCT72_ADDR, 0xFE, 1, &id2, 1) < 0)
  189. printf("Error reading i2c NCT72 information!\n");
  190. else
  191. printf("NCT72(0x%x): ready\n", id2);
  192. kval = env_get("kernelargs");
  193. #ifdef CONFIG_MMC
  194. mmc = find_mmc_device(0);
  195. if (mmc)
  196. if (!mmc_init(mmc)) {
  197. printf("MMC/SD card detected\n");
  198. if (kval) {
  199. int n = strlen(defkargs);
  200. char *tmp = strstr(kval, defkargs);
  201. *tmp = 0;
  202. strcpy(newkernelargs, kval);
  203. strcat(newkernelargs, " ");
  204. strcat(newkernelargs, mmckargs);
  205. strcat(newkernelargs, " ");
  206. strcat(newkernelargs, &tmp[n]);
  207. env_set("kernelargs", newkernelargs);
  208. } else {
  209. env_set("kernelargs", mmckargs);
  210. }
  211. }
  212. #endif
  213. get_arc_info();
  214. if (kval) {
  215. sval = env_get("SERIAL");
  216. if (sval) {
  217. strcpy(newkernelargs, "SN=");
  218. strcat(newkernelargs, sval);
  219. strcat(newkernelargs, " ");
  220. strcat(newkernelargs, kval);
  221. env_set("kernelargs", newkernelargs);
  222. }
  223. } else {
  224. printf("Error reading kernelargs env variable!\n");
  225. }
  226. return 0;
  227. }
  228. int board_eth_init(bd_t *bis)
  229. {
  230. struct fsl_pq_mdio_info mdio_info;
  231. struct tsec_info_struct tsec_info[4];
  232. #ifdef CONFIG_TSEC2
  233. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  234. #endif
  235. int num = 0;
  236. #ifdef CONFIG_TSEC1
  237. SET_STD_TSEC_INFO(tsec_info[num], 1);
  238. num++;
  239. #endif
  240. #ifdef CONFIG_TSEC2
  241. SET_STD_TSEC_INFO(tsec_info[num], 2);
  242. if (is_serdes_configured(SGMII_TSEC2)) {
  243. if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_SGMII2_DIS)) {
  244. puts("eTSEC2 is in sgmii mode.\n");
  245. tsec_info[num].flags |= TSEC_SGMII;
  246. tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
  247. }
  248. }
  249. num++;
  250. #endif
  251. #ifdef CONFIG_TSEC3
  252. SET_STD_TSEC_INFO(tsec_info[num], 3);
  253. num++;
  254. #endif
  255. if (!num) {
  256. printf("No TSECs initialized\n");
  257. return 0;
  258. }
  259. mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
  260. mdio_info.name = DEFAULT_MII_NAME;
  261. fsl_pq_mdio_init(bis, &mdio_info);
  262. tsec_eth_init(bis, tsec_info, num);
  263. return pci_eth_init(bis);
  264. }
  265. #ifdef CONFIG_OF_BOARD_SETUP
  266. int ft_board_setup(void *blob, bd_t *bd)
  267. {
  268. phys_addr_t base;
  269. phys_size_t size;
  270. const char *soc_usb_compat = "fsl-usb2-dr";
  271. int err, usb1_off, usb2_off;
  272. ft_cpu_setup(blob, bd);
  273. base = env_get_bootm_low();
  274. size = env_get_bootm_size();
  275. fdt_fixup_memory(blob, (u64)base, (u64)size);
  276. FT_FSL_PCI_SETUP;
  277. #if defined(CONFIG_HAS_FSL_DR_USB)
  278. fsl_fdt_fixup_dr_usb(blob, bd);
  279. #endif
  280. #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
  281. /* Delete eLBC node as it is muxed with USB2 controller */
  282. if (hwconfig("usb2")) {
  283. const char *soc_elbc_compat = "fsl,p1020-elbc";
  284. int off = fdt_node_offset_by_compatible(blob, -1,
  285. soc_elbc_compat);
  286. if (off < 0) {
  287. printf
  288. ("WARNING: could not find compatible node %s: %s\n",
  289. soc_elbc_compat, fdt_strerror(off));
  290. return off;
  291. }
  292. err = fdt_del_node(blob, off);
  293. if (err < 0) {
  294. printf("WARNING: could not remove %s: %s\n",
  295. soc_elbc_compat, fdt_strerror(err));
  296. }
  297. return err;
  298. }
  299. #endif
  300. /* Delete USB2 node as it is muxed with eLBC */
  301. usb1_off = fdt_node_offset_by_compatible(blob, -1, soc_usb_compat);
  302. if (usb1_off < 0) {
  303. printf("WARNING: could not find compatible node %s: %s.\n",
  304. soc_usb_compat, fdt_strerror(usb1_off));
  305. return usb1_off;
  306. }
  307. usb2_off =
  308. fdt_node_offset_by_compatible(blob, usb1_off, soc_usb_compat);
  309. if (usb2_off < 0) {
  310. printf("WARNING: could not find compatible node %s: %s.\n",
  311. soc_usb_compat, fdt_strerror(usb2_off));
  312. return usb2_off;
  313. }
  314. err = fdt_del_node(blob, usb2_off);
  315. if (err < 0) {
  316. printf("WARNING: could not remove %s: %s.\n",
  317. soc_usb_compat, fdt_strerror(err));
  318. }
  319. return 0;
  320. }
  321. #endif