spl.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 - 2016 Xilinx, Inc.
  4. *
  5. * Michal Simek <michal.simek@xilinx.com>
  6. */
  7. #include <common.h>
  8. #include <debug_uart.h>
  9. #include <init.h>
  10. #include <spl.h>
  11. #include <asm/io.h>
  12. #include <asm/spl.h>
  13. #include <asm/arch/hardware.h>
  14. #include <asm/arch/sys_proto.h>
  15. void board_init_f(ulong dummy)
  16. {
  17. board_early_init_f();
  18. board_early_init_r();
  19. #ifdef CONFIG_DEBUG_UART
  20. /* Uart debug for sure */
  21. debug_uart_init();
  22. puts("Debug uart enabled\n"); /* or printch() */
  23. #endif
  24. /* Delay is required for clocks to be propagated */
  25. udelay(1000000);
  26. debug("Clearing BSS 0x%p - 0x%p\n", __bss_start, __bss_end);
  27. /* Clear the BSS */
  28. memset(__bss_start, 0, __bss_end - __bss_start);
  29. /* No need to call timer init - it is empty for ZynqMP */
  30. board_init_r(NULL, 0);
  31. }
  32. static void ps_mode_reset(ulong mode)
  33. {
  34. writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
  35. &crlapb_base->boot_pin_ctrl);
  36. udelay(5);
  37. writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT |
  38. mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
  39. &crlapb_base->boot_pin_ctrl);
  40. }
  41. /*
  42. * Set default PS_MODE1 which is used for USB ULPI phy reset
  43. * Also other resets can be connected to this certain pin
  44. */
  45. #ifndef MODE_RESET
  46. # define MODE_RESET PS_MODE1
  47. #endif
  48. #ifdef CONFIG_SPL_BOARD_INIT
  49. void spl_board_init(void)
  50. {
  51. preloader_console_init();
  52. ps_mode_reset(MODE_RESET);
  53. board_init();
  54. }
  55. #endif
  56. u32 spl_boot_device(void)
  57. {
  58. u32 reg = 0;
  59. u8 bootmode;
  60. #if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED)
  61. /* Change default boot mode at run-time */
  62. writel(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT,
  63. &crlapb_base->boot_mode);
  64. #endif
  65. reg = readl(&crlapb_base->boot_mode);
  66. if (reg >> BOOT_MODE_ALT_SHIFT)
  67. reg >>= BOOT_MODE_ALT_SHIFT;
  68. bootmode = reg & BOOT_MODES_MASK;
  69. switch (bootmode) {
  70. case JTAG_MODE:
  71. return BOOT_DEVICE_RAM;
  72. #ifdef CONFIG_SPL_MMC_SUPPORT
  73. case SD_MODE1:
  74. case SD1_LSHFT_MODE: /* not working on silicon v1 */
  75. /* if both controllers enabled, then these two are the second controller */
  76. #ifdef CONFIG_SPL_ZYNQMP_TWO_SDHCI
  77. return BOOT_DEVICE_MMC2;
  78. /* else, fall through, the one SDHCI controller that is enabled is number 1 */
  79. #endif
  80. case SD_MODE:
  81. case EMMC_MODE:
  82. return BOOT_DEVICE_MMC1;
  83. #endif
  84. #ifdef CONFIG_SPL_DFU
  85. case USB_MODE:
  86. return BOOT_DEVICE_DFU;
  87. #endif
  88. #ifdef CONFIG_SPL_SATA_SUPPORT
  89. case SW_SATA_MODE:
  90. return BOOT_DEVICE_SATA;
  91. #endif
  92. #ifdef CONFIG_SPL_SPI_SUPPORT
  93. case QSPI_MODE_24BIT:
  94. case QSPI_MODE_32BIT:
  95. return BOOT_DEVICE_SPI;
  96. #endif
  97. default:
  98. printf("Invalid Boot Mode:0x%x\n", bootmode);
  99. break;
  100. }
  101. return 0;
  102. }
  103. #ifdef CONFIG_SPL_OS_BOOT
  104. int spl_start_uboot(void)
  105. {
  106. handoff_setup();
  107. return 0;
  108. }
  109. #endif
  110. #ifdef CONFIG_SPL_LOAD_FIT
  111. int board_fit_config_name_match(const char *name)
  112. {
  113. /* Just empty function now - can't decide what to choose */
  114. debug("%s: %s\n", __func__, name);
  115. return 0;
  116. }
  117. #endif