soc.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014-2015 Freescale Semiconductor
  4. * Copyright 2019 NXP
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <fsl_immap.h>
  9. #include <fsl_ifc.h>
  10. #include <init.h>
  11. #include <asm/arch/fsl_serdes.h>
  12. #include <asm/arch/soc.h>
  13. #include <asm/io.h>
  14. #include <asm/global_data.h>
  15. #include <asm/arch-fsl-layerscape/config.h>
  16. #include <asm/arch-fsl-layerscape/ns_access.h>
  17. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  18. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  19. #include <fsl_csu.h>
  20. #endif
  21. #ifdef CONFIG_SYS_FSL_DDR
  22. #include <fsl_ddr_sdram.h>
  23. #include <fsl_ddr.h>
  24. #endif
  25. #ifdef CONFIG_CHAIN_OF_TRUST
  26. #include <fsl_validate.h>
  27. #endif
  28. #include <fsl_immap.h>
  29. #ifdef CONFIG_TFABOOT
  30. #include <env_internal.h>
  31. DECLARE_GLOBAL_DATA_PTR;
  32. #endif
  33. bool soc_has_dp_ddr(void)
  34. {
  35. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  36. u32 svr = gur_in32(&gur->svr);
  37. /* LS2085A, LS2088A, LS2048A has DP_DDR */
  38. if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
  39. (SVR_SOC_VER(svr) == SVR_LS2088A) ||
  40. (SVR_SOC_VER(svr) == SVR_LS2048A))
  41. return true;
  42. return false;
  43. }
  44. bool soc_has_aiop(void)
  45. {
  46. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  47. u32 svr = gur_in32(&gur->svr);
  48. /* LS2085A has AIOP */
  49. if (SVR_SOC_VER(svr) == SVR_LS2085A)
  50. return true;
  51. return false;
  52. }
  53. static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
  54. {
  55. scfg_clrsetbits32(scfg + offset / 4,
  56. 0xF << 6,
  57. SCFG_USB_TXVREFTUNE << 6);
  58. }
  59. static void erratum_a009008(void)
  60. {
  61. #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
  62. u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  63. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  64. defined(CONFIG_ARCH_LS1012A)
  65. set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
  66. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  67. set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
  68. set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
  69. #endif
  70. #elif defined(CONFIG_ARCH_LS2080A)
  71. set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
  72. #endif
  73. #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
  74. }
  75. static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
  76. {
  77. scfg_clrbits32(scfg + offset / 4,
  78. SCFG_USB_SQRXTUNE_MASK << 23);
  79. }
  80. static void erratum_a009798(void)
  81. {
  82. #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
  83. u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  84. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  85. defined(CONFIG_ARCH_LS1012A)
  86. set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
  87. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  88. set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
  89. set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
  90. #endif
  91. #elif defined(CONFIG_ARCH_LS2080A)
  92. set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
  93. #endif
  94. #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
  95. }
  96. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  97. defined(CONFIG_ARCH_LS1012A)
  98. static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
  99. {
  100. scfg_clrsetbits32(scfg + offset / 4,
  101. 0x7F << 9,
  102. SCFG_USB_PCSTXSWINGFULL << 9);
  103. }
  104. #endif
  105. static void erratum_a008997(void)
  106. {
  107. #ifdef CONFIG_SYS_FSL_ERRATUM_A008997
  108. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  109. defined(CONFIG_ARCH_LS1012A)
  110. u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  111. set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
  112. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  113. set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
  114. set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
  115. #endif
  116. #elif defined(CONFIG_ARCH_LS1028A)
  117. clrsetbits_le32(DCSR_BASE + DCSR_USB_IOCR1,
  118. 0x7F << 11,
  119. DCSR_USB_PCSTXSWINGFULL << 11);
  120. #endif
  121. #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
  122. }
  123. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  124. defined(CONFIG_ARCH_LS1012A)
  125. #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
  126. out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
  127. out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
  128. out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
  129. out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
  130. #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
  131. defined(CONFIG_ARCH_LS1028A)
  132. #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
  133. out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
  134. out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
  135. out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
  136. out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
  137. #endif
  138. static void erratum_a009007(void)
  139. {
  140. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
  141. defined(CONFIG_ARCH_LS1012A)
  142. void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
  143. PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
  144. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  145. usb_phy = (void __iomem *)SCFG_USB_PHY2;
  146. PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
  147. usb_phy = (void __iomem *)SCFG_USB_PHY3;
  148. PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
  149. #endif
  150. #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
  151. defined(CONFIG_ARCH_LS1028A)
  152. void __iomem *dcsr = (void __iomem *)DCSR_BASE;
  153. PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
  154. PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
  155. #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
  156. }
  157. #if defined(CONFIG_FSL_LSCH3)
  158. /*
  159. * This erratum requires setting a value to eddrtqcr1 to
  160. * optimal the DDR performance.
  161. */
  162. static void erratum_a008336(void)
  163. {
  164. #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
  165. u32 *eddrtqcr1;
  166. #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
  167. eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
  168. if (fsl_ddr_get_version(0) == 0x50200)
  169. out_le32(eddrtqcr1, 0x63b30002);
  170. #endif
  171. #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
  172. eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
  173. if (fsl_ddr_get_version(0) == 0x50200)
  174. out_le32(eddrtqcr1, 0x63b30002);
  175. #endif
  176. #endif
  177. }
  178. /*
  179. * This erratum requires a register write before being Memory
  180. * controller 3 being enabled.
  181. */
  182. static void erratum_a008514(void)
  183. {
  184. #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
  185. u32 *eddrtqcr1;
  186. #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
  187. eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
  188. out_le32(eddrtqcr1, 0x63b20002);
  189. #endif
  190. #endif
  191. }
  192. #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
  193. #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
  194. static unsigned long get_internval_val_mhz(void)
  195. {
  196. char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
  197. /*
  198. * interval is the number of platform cycles(MHz) between
  199. * wake up events generated by EPU.
  200. */
  201. ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
  202. if (interval)
  203. interval_mhz = simple_strtoul(interval, NULL, 10);
  204. return interval_mhz;
  205. }
  206. void erratum_a009635(void)
  207. {
  208. u32 val;
  209. unsigned long interval_mhz = get_internval_val_mhz();
  210. if (!interval_mhz)
  211. return;
  212. val = in_le32(DCSR_CGACRE5);
  213. writel(val | 0x00000200, DCSR_CGACRE5);
  214. val = in_le32(EPU_EPCMPR5);
  215. writel(interval_mhz, EPU_EPCMPR5);
  216. val = in_le32(EPU_EPCCR5);
  217. writel(val | 0x82820000, EPU_EPCCR5);
  218. val = in_le32(EPU_EPSMCR5);
  219. writel(val | 0x002f0000, EPU_EPSMCR5);
  220. val = in_le32(EPU_EPECR5);
  221. writel(val | 0x20000000, EPU_EPECR5);
  222. val = in_le32(EPU_EPGCR);
  223. writel(val | 0x80000000, EPU_EPGCR);
  224. }
  225. #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
  226. static void erratum_rcw_src(void)
  227. {
  228. #if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
  229. u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
  230. u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
  231. u32 val;
  232. val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
  233. val &= ~DCFG_PORSR1_RCW_SRC;
  234. val |= DCFG_PORSR1_RCW_SRC_NOR;
  235. out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
  236. #endif
  237. }
  238. #define I2C_DEBUG_REG 0x6
  239. #define I2C_GLITCH_EN 0x8
  240. /*
  241. * This erratum requires setting glitch_en bit to enable
  242. * digital glitch filter to improve clock stability.
  243. */
  244. #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
  245. static void erratum_a009203(void)
  246. {
  247. #ifdef CONFIG_SYS_I2C
  248. u8 __iomem *ptr;
  249. #ifdef I2C1_BASE_ADDR
  250. ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
  251. writeb(I2C_GLITCH_EN, ptr);
  252. #endif
  253. #ifdef I2C2_BASE_ADDR
  254. ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
  255. writeb(I2C_GLITCH_EN, ptr);
  256. #endif
  257. #ifdef I2C3_BASE_ADDR
  258. ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
  259. writeb(I2C_GLITCH_EN, ptr);
  260. #endif
  261. #ifdef I2C4_BASE_ADDR
  262. ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
  263. writeb(I2C_GLITCH_EN, ptr);
  264. #endif
  265. #endif
  266. }
  267. #endif
  268. void bypass_smmu(void)
  269. {
  270. u32 val;
  271. val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  272. out_le32(SMMU_SCR0, val);
  273. val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  274. out_le32(SMMU_NSCR0, val);
  275. }
  276. void fsl_lsch3_early_init_f(void)
  277. {
  278. erratum_rcw_src();
  279. #ifdef CONFIG_FSL_IFC
  280. init_early_memctl_regs(); /* tighten IFC timing */
  281. #endif
  282. #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
  283. erratum_a009203();
  284. #endif
  285. erratum_a008514();
  286. erratum_a008336();
  287. erratum_a009008();
  288. erratum_a009798();
  289. erratum_a008997();
  290. erratum_a009007();
  291. #ifdef CONFIG_CHAIN_OF_TRUST
  292. /* In case of Secure Boot, the IBR configures the SMMU
  293. * to allow only Secure transactions.
  294. * SMMU must be reset in bypass mode.
  295. * Set the ClientPD bit and Clear the USFCFG Bit
  296. */
  297. if (fsl_check_boot_mode_secure() == 1)
  298. bypass_smmu();
  299. #endif
  300. #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
  301. defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
  302. set_icids();
  303. #endif
  304. }
  305. /* Get VDD in the unit mV from voltage ID */
  306. int get_core_volt_from_fuse(void)
  307. {
  308. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  309. int vdd;
  310. u32 fusesr;
  311. u8 vid;
  312. /* get the voltage ID from fuse status register */
  313. fusesr = in_le32(&gur->dcfg_fusesr);
  314. debug("%s: fusesr = 0x%x\n", __func__, fusesr);
  315. vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
  316. FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
  317. if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
  318. vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
  319. FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
  320. }
  321. debug("%s: VID = 0x%x\n", __func__, vid);
  322. switch (vid) {
  323. case 0x00: /* VID isn't supported */
  324. vdd = -EINVAL;
  325. debug("%s: The VID feature is not supported\n", __func__);
  326. break;
  327. case 0x08: /* 0.9V silicon */
  328. vdd = 900;
  329. break;
  330. case 0x10: /* 1.0V silicon */
  331. vdd = 1000;
  332. break;
  333. default: /* Other core voltage */
  334. vdd = -EINVAL;
  335. debug("%s: The VID(%x) isn't supported\n", __func__, vid);
  336. break;
  337. }
  338. debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
  339. return vdd;
  340. }
  341. #elif defined(CONFIG_FSL_LSCH2)
  342. static void erratum_a009929(void)
  343. {
  344. #ifdef CONFIG_SYS_FSL_ERRATUM_A009929
  345. struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  346. u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
  347. u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
  348. rstrqmr1 |= 0x00000400;
  349. gur_out32(&gur->rstrqmr1, rstrqmr1);
  350. writel(0x01000000, dcsr_cop_ccp);
  351. #endif
  352. }
  353. /*
  354. * This erratum requires setting a value to eddrtqcr1 to optimal
  355. * the DDR performance. The eddrtqcr1 register is in SCFG space
  356. * of LS1043A and the offset is 0x157_020c.
  357. */
  358. #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
  359. && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
  360. #error A009660 and A008514 can not be both enabled.
  361. #endif
  362. static void erratum_a009660(void)
  363. {
  364. #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
  365. u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
  366. out_be32(eddrtqcr1, 0x63b20042);
  367. #endif
  368. }
  369. static void erratum_a008850_early(void)
  370. {
  371. #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
  372. /* part 1 of 2 */
  373. struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
  374. CONFIG_SYS_CCI400_OFFSET);
  375. struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  376. /* Skip if running at lower exception level */
  377. if (current_el() < 3)
  378. return;
  379. /* disables propagation of barrier transactions to DDRC from CCI400 */
  380. out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
  381. /* disable the re-ordering in DDRC */
  382. ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
  383. #endif
  384. }
  385. void erratum_a008850_post(void)
  386. {
  387. #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
  388. /* part 2 of 2 */
  389. struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
  390. CONFIG_SYS_CCI400_OFFSET);
  391. struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  392. u32 tmp;
  393. /* Skip if running at lower exception level */
  394. if (current_el() < 3)
  395. return;
  396. /* enable propagation of barrier transactions to DDRC from CCI400 */
  397. out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
  398. /* enable the re-ordering in DDRC */
  399. tmp = ddr_in32(&ddr->eor);
  400. tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
  401. ddr_out32(&ddr->eor, tmp);
  402. #endif
  403. }
  404. #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  405. void erratum_a010315(void)
  406. {
  407. int i;
  408. for (i = PCIE1; i <= PCIE4; i++)
  409. if (!is_serdes_configured(i)) {
  410. debug("PCIe%d: disabled all R/W permission!\n", i);
  411. set_pcie_ns_access(i, 0);
  412. }
  413. }
  414. #endif
  415. static void erratum_a010539(void)
  416. {
  417. #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
  418. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  419. u32 porsr1;
  420. porsr1 = in_be32(&gur->porsr1);
  421. porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
  422. out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
  423. porsr1);
  424. out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
  425. #endif
  426. }
  427. /* Get VDD in the unit mV from voltage ID */
  428. int get_core_volt_from_fuse(void)
  429. {
  430. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  431. int vdd;
  432. u32 fusesr;
  433. u8 vid;
  434. fusesr = in_be32(&gur->dcfg_fusesr);
  435. debug("%s: fusesr = 0x%x\n", __func__, fusesr);
  436. vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
  437. FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
  438. if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
  439. vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
  440. FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
  441. }
  442. debug("%s: VID = 0x%x\n", __func__, vid);
  443. switch (vid) {
  444. case 0x00: /* VID isn't supported */
  445. vdd = -EINVAL;
  446. debug("%s: The VID feature is not supported\n", __func__);
  447. break;
  448. case 0x08: /* 0.9V silicon */
  449. vdd = 900;
  450. break;
  451. case 0x10: /* 1.0V silicon */
  452. vdd = 1000;
  453. break;
  454. default: /* Other core voltage */
  455. vdd = -EINVAL;
  456. printf("%s: The VID(%x) isn't supported\n", __func__, vid);
  457. break;
  458. }
  459. debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
  460. return vdd;
  461. }
  462. __weak int board_switch_core_volt(u32 vdd)
  463. {
  464. return 0;
  465. }
  466. static int setup_core_volt(u32 vdd)
  467. {
  468. return board_setup_core_volt(vdd);
  469. }
  470. #ifdef CONFIG_SYS_FSL_DDR
  471. static void ddr_enable_0v9_volt(bool en)
  472. {
  473. struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  474. u32 tmp;
  475. tmp = ddr_in32(&ddr->ddr_cdr1);
  476. if (en)
  477. tmp |= DDR_CDR1_V0PT9_EN;
  478. else
  479. tmp &= ~DDR_CDR1_V0PT9_EN;
  480. ddr_out32(&ddr->ddr_cdr1, tmp);
  481. }
  482. #endif
  483. int setup_chip_volt(void)
  484. {
  485. int vdd;
  486. vdd = get_core_volt_from_fuse();
  487. /* Nothing to do for silicons doesn't support VID */
  488. if (vdd < 0)
  489. return vdd;
  490. if (setup_core_volt(vdd))
  491. printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
  492. #ifdef CONFIG_SYS_HAS_SERDES
  493. if (setup_serdes_volt(vdd))
  494. printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
  495. #endif
  496. #ifdef CONFIG_SYS_FSL_DDR
  497. if (vdd == 900)
  498. ddr_enable_0v9_volt(true);
  499. #endif
  500. return 0;
  501. }
  502. #ifdef CONFIG_FSL_PFE
  503. void init_pfe_scfg_dcfg_regs(void)
  504. {
  505. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  506. u32 ecccr2;
  507. out_be32(&scfg->pfeasbcr,
  508. in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
  509. out_be32(&scfg->pfebsbcr,
  510. in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
  511. /* CCI-400 QoS settings for PFE */
  512. out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
  513. | SCFG_WR_QOS1_PFE2_QOS));
  514. out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
  515. | SCFG_RD_QOS1_PFE2_QOS));
  516. ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
  517. out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
  518. ecccr2 | (unsigned int)DISABLE_PFE_ECC);
  519. }
  520. #endif
  521. void fsl_lsch2_early_init_f(void)
  522. {
  523. struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
  524. CONFIG_SYS_CCI400_OFFSET);
  525. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  526. #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
  527. enum boot_src src;
  528. #endif
  529. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  530. enable_layerscape_ns_access();
  531. #endif
  532. #ifdef CONFIG_FSL_IFC
  533. init_early_memctl_regs(); /* tighten IFC timing */
  534. #endif
  535. #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
  536. src = get_boot_src();
  537. if (src != BOOT_SOURCE_QSPI_NOR)
  538. out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
  539. #else
  540. #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
  541. out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
  542. #endif
  543. #endif
  544. /* Make SEC reads and writes snoopable */
  545. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  546. setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
  547. SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
  548. SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
  549. SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
  550. SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
  551. SCFG_SNPCNFGCR_SATAWRSNP);
  552. #else
  553. setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
  554. SCFG_SNPCNFGCR_SECWRSNP |
  555. SCFG_SNPCNFGCR_SATARDSNP |
  556. SCFG_SNPCNFGCR_SATAWRSNP);
  557. #endif
  558. /*
  559. * Enable snoop requests and DVM message requests for
  560. * Slave insterface S4 (A53 core cluster)
  561. */
  562. if (current_el() == 3) {
  563. out_le32(&cci->slave[4].snoop_ctrl,
  564. CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
  565. }
  566. /*
  567. * Program Central Security Unit (CSU) to grant access
  568. * permission for USB 2.0 controller
  569. */
  570. #if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL)
  571. if (current_el() == 3)
  572. set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW);
  573. #endif
  574. /* Erratum */
  575. erratum_a008850_early(); /* part 1 of 2 */
  576. erratum_a009929();
  577. erratum_a009660();
  578. erratum_a010539();
  579. erratum_a009008();
  580. erratum_a009798();
  581. erratum_a008997();
  582. erratum_a009007();
  583. #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
  584. set_icids();
  585. #endif
  586. }
  587. #endif
  588. #ifdef CONFIG_QSPI_AHB_INIT
  589. /* Enable 4bytes address support and fast read */
  590. int qspi_ahb_init(void)
  591. {
  592. u32 *qspi_lut, lut_key, *qspi_key;
  593. qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
  594. qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
  595. lut_key = in_be32(qspi_key);
  596. if (lut_key == 0x5af05af0) {
  597. /* That means the register is BE */
  598. out_be32(qspi_key, 0x5af05af0);
  599. /* Unlock the lut table */
  600. out_be32(qspi_key + 1, 0x00000002);
  601. out_be32(qspi_lut, 0x0820040c);
  602. out_be32(qspi_lut + 1, 0x1c080c08);
  603. out_be32(qspi_lut + 2, 0x00002400);
  604. /* Lock the lut table */
  605. out_be32(qspi_key, 0x5af05af0);
  606. out_be32(qspi_key + 1, 0x00000001);
  607. } else {
  608. /* That means the register is LE */
  609. out_le32(qspi_key, 0x5af05af0);
  610. /* Unlock the lut table */
  611. out_le32(qspi_key + 1, 0x00000002);
  612. out_le32(qspi_lut, 0x0820040c);
  613. out_le32(qspi_lut + 1, 0x1c080c08);
  614. out_le32(qspi_lut + 2, 0x00002400);
  615. /* Lock the lut table */
  616. out_le32(qspi_key, 0x5af05af0);
  617. out_le32(qspi_key + 1, 0x00000001);
  618. }
  619. return 0;
  620. }
  621. #endif
  622. #ifdef CONFIG_TFABOOT
  623. #define MAX_BOOTCMD_SIZE 512
  624. int fsl_setenv_bootcmd(void)
  625. {
  626. int ret;
  627. enum boot_src src = get_boot_src();
  628. char bootcmd_str[MAX_BOOTCMD_SIZE];
  629. switch (src) {
  630. #ifdef IFC_NOR_BOOTCOMMAND
  631. case BOOT_SOURCE_IFC_NOR:
  632. sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND);
  633. break;
  634. #endif
  635. #ifdef QSPI_NOR_BOOTCOMMAND
  636. case BOOT_SOURCE_QSPI_NOR:
  637. sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
  638. break;
  639. #endif
  640. #ifdef XSPI_NOR_BOOTCOMMAND
  641. case BOOT_SOURCE_XSPI_NOR:
  642. sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND);
  643. break;
  644. #endif
  645. #ifdef IFC_NAND_BOOTCOMMAND
  646. case BOOT_SOURCE_IFC_NAND:
  647. sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND);
  648. break;
  649. #endif
  650. #ifdef QSPI_NAND_BOOTCOMMAND
  651. case BOOT_SOURCE_QSPI_NAND:
  652. sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND);
  653. break;
  654. #endif
  655. #ifdef XSPI_NAND_BOOTCOMMAND
  656. case BOOT_SOURCE_XSPI_NAND:
  657. sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND);
  658. break;
  659. #endif
  660. #ifdef SD_BOOTCOMMAND
  661. case BOOT_SOURCE_SD_MMC:
  662. sprintf(bootcmd_str, SD_BOOTCOMMAND);
  663. break;
  664. #endif
  665. #ifdef SD2_BOOTCOMMAND
  666. case BOOT_SOURCE_SD_MMC2:
  667. sprintf(bootcmd_str, SD2_BOOTCOMMAND);
  668. break;
  669. #endif
  670. default:
  671. #ifdef QSPI_NOR_BOOTCOMMAND
  672. sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
  673. #endif
  674. break;
  675. }
  676. ret = env_set("bootcmd", bootcmd_str);
  677. if (ret) {
  678. printf("Failed to set bootcmd: ret = %d\n", ret);
  679. return ret;
  680. }
  681. return 0;
  682. }
  683. int fsl_setenv_mcinitcmd(void)
  684. {
  685. int ret = 0;
  686. enum boot_src src = get_boot_src();
  687. switch (src) {
  688. #ifdef IFC_MC_INIT_CMD
  689. case BOOT_SOURCE_IFC_NAND:
  690. case BOOT_SOURCE_IFC_NOR:
  691. ret = env_set("mcinitcmd", IFC_MC_INIT_CMD);
  692. break;
  693. #endif
  694. #ifdef QSPI_MC_INIT_CMD
  695. case BOOT_SOURCE_QSPI_NAND:
  696. case BOOT_SOURCE_QSPI_NOR:
  697. ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
  698. break;
  699. #endif
  700. #ifdef XSPI_MC_INIT_CMD
  701. case BOOT_SOURCE_XSPI_NAND:
  702. case BOOT_SOURCE_XSPI_NOR:
  703. ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD);
  704. break;
  705. #endif
  706. #ifdef SD_MC_INIT_CMD
  707. case BOOT_SOURCE_SD_MMC:
  708. ret = env_set("mcinitcmd", SD_MC_INIT_CMD);
  709. break;
  710. #endif
  711. #ifdef SD2_MC_INIT_CMD
  712. case BOOT_SOURCE_SD_MMC2:
  713. ret = env_set("mcinitcmd", SD2_MC_INIT_CMD);
  714. break;
  715. #endif
  716. default:
  717. #ifdef QSPI_MC_INIT_CMD
  718. ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
  719. #endif
  720. break;
  721. }
  722. if (ret) {
  723. printf("Failed to set mcinitcmd: ret = %d\n", ret);
  724. return ret;
  725. }
  726. return 0;
  727. }
  728. #endif
  729. #ifdef CONFIG_BOARD_LATE_INIT
  730. __weak int fsl_board_late_init(void)
  731. {
  732. return 0;
  733. }
  734. int board_late_init(void)
  735. {
  736. #ifdef CONFIG_CHAIN_OF_TRUST
  737. fsl_setenv_chain_of_trust();
  738. #endif
  739. #ifdef CONFIG_TFABOOT
  740. /*
  741. * check if gd->env_addr is default_environment; then setenv bootcmd
  742. * and mcinitcmd.
  743. */
  744. #ifdef CONFIG_SYS_RELOC_GD_ENV_ADDR
  745. if (gd->env_addr == (ulong)&default_environment[0]) {
  746. #else
  747. if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) {
  748. #endif
  749. fsl_setenv_bootcmd();
  750. fsl_setenv_mcinitcmd();
  751. }
  752. /*
  753. * If the boot mode is secure, default environment is not present then
  754. * setenv command needs to be run by default
  755. */
  756. #ifdef CONFIG_CHAIN_OF_TRUST
  757. if ((fsl_check_boot_mode_secure() == 1)) {
  758. fsl_setenv_bootcmd();
  759. fsl_setenv_mcinitcmd();
  760. }
  761. #endif
  762. #endif
  763. #ifdef CONFIG_QSPI_AHB_INIT
  764. qspi_ahb_init();
  765. #endif
  766. return fsl_board_late_init();
  767. }
  768. #endif