sdram_rk3399.c 92 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * (C) Copyright 2016-2017 Rockchip Inc.
  4. *
  5. * Adapted from coreboot.
  6. */
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <dm.h>
  10. #include <dt-structs.h>
  11. #include <init.h>
  12. #include <log.h>
  13. #include <ram.h>
  14. #include <regmap.h>
  15. #include <syscon.h>
  16. #include <asm/io.h>
  17. #include <asm/arch-rockchip/clock.h>
  18. #include <asm/arch-rockchip/cru.h>
  19. #include <asm/arch-rockchip/grf_rk3399.h>
  20. #include <asm/arch-rockchip/pmu_rk3399.h>
  21. #include <asm/arch-rockchip/hardware.h>
  22. #include <asm/arch-rockchip/sdram.h>
  23. #include <asm/arch-rockchip/sdram_rk3399.h>
  24. #include <linux/delay.h>
  25. #include <linux/err.h>
  26. #include <time.h>
  27. #define PRESET_SGRF_HOLD(n) ((0x1 << (6 + 16)) | ((n) << 6))
  28. #define PRESET_GPIO0_HOLD(n) ((0x1 << (7 + 16)) | ((n) << 7))
  29. #define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8))
  30. #define PHY_DRV_ODT_HI_Z 0x0
  31. #define PHY_DRV_ODT_240 0x1
  32. #define PHY_DRV_ODT_120 0x8
  33. #define PHY_DRV_ODT_80 0x9
  34. #define PHY_DRV_ODT_60 0xc
  35. #define PHY_DRV_ODT_48 0xd
  36. #define PHY_DRV_ODT_40 0xe
  37. #define PHY_DRV_ODT_34_3 0xf
  38. #define PHY_BOOSTP_EN 0x1
  39. #define PHY_BOOSTN_EN 0x1
  40. #define PHY_SLEWP_EN 0x1
  41. #define PHY_SLEWN_EN 0x1
  42. #define PHY_RX_CM_INPUT 0x1
  43. #define CS0_MR22_VAL 0
  44. #define CS1_MR22_VAL 3
  45. /* LPDDR3 DRAM DS */
  46. #define LPDDR3_DS_34 0x1
  47. #define LPDDR3_DS_40 0x2
  48. #define LPDDR3_DS_48 0x3
  49. #define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \
  50. ((n) << (8 + (ch) * 4)))
  51. #define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \
  52. ((n) << (9 + (ch) * 4)))
  53. struct chan_info {
  54. struct rk3399_ddr_pctl_regs *pctl;
  55. struct rk3399_ddr_pi_regs *pi;
  56. struct rk3399_ddr_publ_regs *publ;
  57. struct msch_regs *msch;
  58. };
  59. struct dram_info {
  60. #if defined(CONFIG_TPL_BUILD) || \
  61. (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
  62. u32 pwrup_srefresh_exit[2];
  63. struct chan_info chan[2];
  64. struct clk ddr_clk;
  65. struct rockchip_cru *cru;
  66. struct rk3399_grf_regs *grf;
  67. struct rk3399_pmu_regs *pmu;
  68. struct rk3399_pmucru *pmucru;
  69. struct rk3399_pmusgrf_regs *pmusgrf;
  70. struct rk3399_ddr_cic_regs *cic;
  71. const struct sdram_rk3399_ops *ops;
  72. #endif
  73. struct ram_info info;
  74. struct rk3399_pmugrf_regs *pmugrf;
  75. };
  76. struct sdram_rk3399_ops {
  77. int (*data_training_first)(struct dram_info *dram, u32 channel, u8 rank,
  78. struct rk3399_sdram_params *sdram);
  79. int (*set_rate_index)(struct dram_info *dram,
  80. struct rk3399_sdram_params *params);
  81. void (*modify_param)(const struct chan_info *chan,
  82. struct rk3399_sdram_params *params);
  83. struct rk3399_sdram_params *
  84. (*get_phy_index_params)(u32 phy_fn,
  85. struct rk3399_sdram_params *params);
  86. };
  87. #if defined(CONFIG_TPL_BUILD) || \
  88. (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
  89. struct rockchip_dmc_plat {
  90. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  91. struct dtd_rockchip_rk3399_dmc dtplat;
  92. #else
  93. struct rk3399_sdram_params sdram_params;
  94. #endif
  95. struct regmap *map;
  96. };
  97. struct io_setting {
  98. u32 mhz;
  99. u32 mr5;
  100. /* dram side */
  101. u32 dq_odt;
  102. u32 ca_odt;
  103. u32 pdds;
  104. u32 dq_vref;
  105. u32 ca_vref;
  106. /* phy side */
  107. u32 rd_odt;
  108. u32 wr_dq_drv;
  109. u32 wr_ca_drv;
  110. u32 wr_ckcs_drv;
  111. u32 rd_odt_en;
  112. u32 rd_vref;
  113. } lpddr4_io_setting[] = {
  114. {
  115. 50 * MHz,
  116. 0,
  117. /* dram side */
  118. 0, /* dq_odt; */
  119. 0, /* ca_odt; */
  120. 6, /* pdds; */
  121. 0x72, /* dq_vref; */
  122. 0x72, /* ca_vref; */
  123. /* phy side */
  124. PHY_DRV_ODT_HI_Z, /* rd_odt; */
  125. PHY_DRV_ODT_40, /* wr_dq_drv; */
  126. PHY_DRV_ODT_40, /* wr_ca_drv; */
  127. PHY_DRV_ODT_40, /* wr_ckcs_drv; */
  128. 0, /* rd_odt_en;*/
  129. 41, /* rd_vref; (unit %, range 3.3% - 48.7%) */
  130. },
  131. {
  132. 600 * MHz,
  133. 0,
  134. /* dram side */
  135. 1, /* dq_odt; */
  136. 0, /* ca_odt; */
  137. 6, /* pdds; */
  138. 0x72, /* dq_vref; */
  139. 0x72, /* ca_vref; */
  140. /* phy side */
  141. PHY_DRV_ODT_HI_Z, /* rd_odt; */
  142. PHY_DRV_ODT_48, /* wr_dq_drv; */
  143. PHY_DRV_ODT_40, /* wr_ca_drv; */
  144. PHY_DRV_ODT_40, /* wr_ckcs_drv; */
  145. 0, /* rd_odt_en; */
  146. 32, /* rd_vref; (unit %, range 3.3% - 48.7%) */
  147. },
  148. {
  149. 933 * MHz,
  150. 0,
  151. /* dram side */
  152. 1, /* dq_odt; */
  153. 0, /* ca_odt; */
  154. 3, /* pdds; */
  155. 0x72, /* dq_vref; */
  156. 0x72, /* ca_vref; */
  157. /* phy side */
  158. PHY_DRV_ODT_80, /* rd_odt; */
  159. PHY_DRV_ODT_40, /* wr_dq_drv; */
  160. PHY_DRV_ODT_40, /* wr_ca_drv; */
  161. PHY_DRV_ODT_40, /* wr_ckcs_drv; */
  162. 1, /* rd_odt_en; */
  163. 20, /* rd_vref; (unit %, range 3.3% - 48.7%) */
  164. },
  165. {
  166. 1066 * MHz,
  167. 0,
  168. /* dram side */
  169. 6, /* dq_odt; */
  170. 0, /* ca_odt; */
  171. 3, /* pdds; */
  172. 0x10, /* dq_vref; */
  173. 0x72, /* ca_vref; */
  174. /* phy side */
  175. PHY_DRV_ODT_80, /* rd_odt; */
  176. PHY_DRV_ODT_60, /* wr_dq_drv; */
  177. PHY_DRV_ODT_40, /* wr_ca_drv; */
  178. PHY_DRV_ODT_40, /* wr_ckcs_drv; */
  179. 1, /* rd_odt_en; */
  180. 20, /* rd_vref; (unit %, range 3.3% - 48.7%) */
  181. },
  182. };
  183. static struct io_setting *
  184. lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5)
  185. {
  186. struct io_setting *io = NULL;
  187. u32 n;
  188. for (n = 0; n < ARRAY_SIZE(lpddr4_io_setting); n++) {
  189. io = &lpddr4_io_setting[n];
  190. if (io->mr5 != 0) {
  191. if (io->mhz >= params->base.ddr_freq &&
  192. io->mr5 == mr5)
  193. break;
  194. } else {
  195. if (io->mhz >= params->base.ddr_freq)
  196. break;
  197. }
  198. }
  199. return io;
  200. }
  201. static void *get_denali_ctl(const struct chan_info *chan,
  202. struct rk3399_sdram_params *params, bool reg)
  203. {
  204. return reg ? &chan->pctl->denali_ctl : &params->pctl_regs.denali_ctl;
  205. }
  206. static void *get_denali_phy(const struct chan_info *chan,
  207. struct rk3399_sdram_params *params, bool reg)
  208. {
  209. return reg ? &chan->publ->denali_phy : &params->phy_regs.denali_phy;
  210. }
  211. static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
  212. {
  213. return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc1_con0;
  214. }
  215. static void rkclk_ddr_reset(struct rockchip_cru *cru, u32 channel, u32 ctl,
  216. u32 phy)
  217. {
  218. channel &= 0x1;
  219. ctl &= 0x1;
  220. phy &= 0x1;
  221. writel(CRU_SFTRST_DDR_CTRL(channel, ctl) |
  222. CRU_SFTRST_DDR_PHY(channel, phy),
  223. &cru->softrst_con[4]);
  224. }
  225. static void phy_pctrl_reset(struct rockchip_cru *cru, u32 channel)
  226. {
  227. rkclk_ddr_reset(cru, channel, 1, 1);
  228. udelay(10);
  229. rkclk_ddr_reset(cru, channel, 1, 0);
  230. udelay(10);
  231. rkclk_ddr_reset(cru, channel, 0, 0);
  232. udelay(10);
  233. }
  234. static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs,
  235. u32 freq)
  236. {
  237. u32 *denali_phy = ddr_publ_regs->denali_phy;
  238. /* From IP spec, only freq small than 125 can enter dll bypass mode */
  239. if (freq <= 125) {
  240. /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
  241. setbits_le32(&denali_phy[86], (0x3 << 2) << 8);
  242. setbits_le32(&denali_phy[214], (0x3 << 2) << 8);
  243. setbits_le32(&denali_phy[342], (0x3 << 2) << 8);
  244. setbits_le32(&denali_phy[470], (0x3 << 2) << 8);
  245. /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
  246. setbits_le32(&denali_phy[547], (0x3 << 2) << 16);
  247. setbits_le32(&denali_phy[675], (0x3 << 2) << 16);
  248. setbits_le32(&denali_phy[803], (0x3 << 2) << 16);
  249. } else {
  250. /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
  251. clrbits_le32(&denali_phy[86], (0x3 << 2) << 8);
  252. clrbits_le32(&denali_phy[214], (0x3 << 2) << 8);
  253. clrbits_le32(&denali_phy[342], (0x3 << 2) << 8);
  254. clrbits_le32(&denali_phy[470], (0x3 << 2) << 8);
  255. /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
  256. clrbits_le32(&denali_phy[547], (0x3 << 2) << 16);
  257. clrbits_le32(&denali_phy[675], (0x3 << 2) << 16);
  258. clrbits_le32(&denali_phy[803], (0x3 << 2) << 16);
  259. }
  260. }
  261. static void set_memory_map(const struct chan_info *chan, u32 channel,
  262. const struct rk3399_sdram_params *params)
  263. {
  264. const struct rk3399_sdram_channel *sdram_ch = &params->ch[channel];
  265. u32 *denali_ctl = chan->pctl->denali_ctl;
  266. u32 *denali_pi = chan->pi->denali_pi;
  267. u32 cs_map;
  268. u32 reduc;
  269. u32 row;
  270. /* Get row number from ddrconfig setting */
  271. if (sdram_ch->cap_info.ddrconfig < 2 ||
  272. sdram_ch->cap_info.ddrconfig == 4)
  273. row = 16;
  274. else if (sdram_ch->cap_info.ddrconfig == 3 ||
  275. sdram_ch->cap_info.ddrconfig == 5)
  276. row = 14;
  277. else
  278. row = 15;
  279. cs_map = (sdram_ch->cap_info.rank > 1) ? 3 : 1;
  280. reduc = (sdram_ch->cap_info.bw == 2) ? 0 : 1;
  281. /* Set the dram configuration to ctrl */
  282. clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->cap_info.col));
  283. clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24),
  284. ((3 - sdram_ch->cap_info.bk) << 16) |
  285. ((16 - row) << 24));
  286. clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16),
  287. cs_map | (reduc << 16));
  288. /* PI_199 PI_COL_DIFF:RW:0:4 */
  289. clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->cap_info.col));
  290. /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */
  291. clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
  292. ((3 - sdram_ch->cap_info.bk) << 16) |
  293. ((16 - row) << 24));
  294. if (params->base.dramtype == LPDDR4) {
  295. if (cs_map == 1)
  296. cs_map = 0x5;
  297. else if (cs_map == 2)
  298. cs_map = 0xa;
  299. else
  300. cs_map = 0xF;
  301. }
  302. /* PI_41 PI_CS_MAP:RW:24:4 */
  303. clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
  304. if (sdram_ch->cap_info.rank == 1 && params->base.dramtype == DDR3)
  305. writel(0x2EC7FFFF, &denali_pi[34]);
  306. }
  307. static int phy_io_config(u32 *denali_phy, u32 *denali_ctl,
  308. const struct rk3399_sdram_params *params, u32 mr5)
  309. {
  310. u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
  311. u32 mode_sel;
  312. u32 speed;
  313. u32 reg_value;
  314. u32 ds_value, odt_value;
  315. /* vref setting & mode setting */
  316. if (params->base.dramtype == LPDDR4) {
  317. struct io_setting *io = lpddr4_get_io_settings(params, mr5);
  318. u32 rd_vref = io->rd_vref * 1000;
  319. if (rd_vref < 36700) {
  320. /* MODE_LV[2:0] = LPDDR4 (Range 2)*/
  321. vref_mode_dq = 0x7;
  322. /* MODE[2:0]= LPDDR4 Range 2(0.4*VDDQ) */
  323. mode_sel = 0x5;
  324. vref_value_dq = (rd_vref - 3300) / 521;
  325. } else {
  326. /* MODE_LV[2:0] = LPDDR4 (Range 1)*/
  327. vref_mode_dq = 0x6;
  328. /* MODE[2:0]= LPDDR4 Range 1(0.33*VDDQ) */
  329. mode_sel = 0x4;
  330. vref_value_dq = (rd_vref - 15300) / 521;
  331. }
  332. vref_mode_ac = 0x6;
  333. /* VDDQ/3/2=16.8% */
  334. vref_value_ac = 0x3;
  335. } else if (params->base.dramtype == LPDDR3) {
  336. if (params->base.odt == 1) {
  337. vref_mode_dq = 0x5; /* LPDDR3 ODT */
  338. ds_value = readl(&denali_ctl[138]) & 0xf;
  339. odt_value = (readl(&denali_phy[6]) >> 4) & 0xf;
  340. if (ds_value == LPDDR3_DS_48) {
  341. switch (odt_value) {
  342. case PHY_DRV_ODT_240:
  343. vref_value_dq = 0x1B;
  344. break;
  345. case PHY_DRV_ODT_120:
  346. vref_value_dq = 0x26;
  347. break;
  348. case PHY_DRV_ODT_60:
  349. vref_value_dq = 0x36;
  350. break;
  351. default:
  352. debug("Invalid ODT value.\n");
  353. return -EINVAL;
  354. }
  355. } else if (ds_value == LPDDR3_DS_40) {
  356. switch (odt_value) {
  357. case PHY_DRV_ODT_240:
  358. vref_value_dq = 0x19;
  359. break;
  360. case PHY_DRV_ODT_120:
  361. vref_value_dq = 0x23;
  362. break;
  363. case PHY_DRV_ODT_60:
  364. vref_value_dq = 0x31;
  365. break;
  366. default:
  367. debug("Invalid ODT value.\n");
  368. return -EINVAL;
  369. }
  370. } else if (ds_value == LPDDR3_DS_34) {
  371. switch (odt_value) {
  372. case PHY_DRV_ODT_240:
  373. vref_value_dq = 0x17;
  374. break;
  375. case PHY_DRV_ODT_120:
  376. vref_value_dq = 0x20;
  377. break;
  378. case PHY_DRV_ODT_60:
  379. vref_value_dq = 0x2e;
  380. break;
  381. default:
  382. debug("Invalid ODT value.\n");
  383. return -EINVAL;
  384. }
  385. } else {
  386. debug("Invalid DRV value.\n");
  387. return -EINVAL;
  388. }
  389. } else {
  390. vref_mode_dq = 0x2; /* LPDDR3 */
  391. vref_value_dq = 0x1f;
  392. }
  393. vref_mode_ac = 0x2;
  394. vref_value_ac = 0x1f;
  395. mode_sel = 0x0;
  396. } else if (params->base.dramtype == DDR3) {
  397. /* DDR3L */
  398. vref_mode_dq = 0x1;
  399. vref_value_dq = 0x1f;
  400. vref_mode_ac = 0x1;
  401. vref_value_ac = 0x1f;
  402. mode_sel = 0x1;
  403. } else {
  404. debug("Unknown DRAM type.\n");
  405. return -EINVAL;
  406. }
  407. reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
  408. /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
  409. clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
  410. /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
  411. clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
  412. /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
  413. clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
  414. /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
  415. clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
  416. reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
  417. /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
  418. clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
  419. /* PHY_924 PHY_PAD_FDBK_DRIVE */
  420. clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
  421. /* PHY_926 PHY_PAD_DATA_DRIVE */
  422. clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
  423. /* PHY_927 PHY_PAD_DQS_DRIVE */
  424. clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
  425. /* PHY_928 PHY_PAD_ADDR_DRIVE */
  426. clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
  427. /* PHY_929 PHY_PAD_CLK_DRIVE */
  428. clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
  429. /* PHY_935 PHY_PAD_CKE_DRIVE */
  430. clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
  431. /* PHY_937 PHY_PAD_RST_DRIVE */
  432. clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
  433. /* PHY_939 PHY_PAD_CS_DRIVE */
  434. clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
  435. if (params->base.dramtype == LPDDR4) {
  436. /* BOOSTP_EN & BOOSTN_EN */
  437. reg_value = ((PHY_BOOSTP_EN << 4) | PHY_BOOSTN_EN);
  438. /* PHY_925 PHY_PAD_FDBK_DRIVE2 */
  439. clrsetbits_le32(&denali_phy[925], 0xff << 8, reg_value << 8);
  440. /* PHY_926 PHY_PAD_DATA_DRIVE */
  441. clrsetbits_le32(&denali_phy[926], 0xff << 12, reg_value << 12);
  442. /* PHY_927 PHY_PAD_DQS_DRIVE */
  443. clrsetbits_le32(&denali_phy[927], 0xff << 14, reg_value << 14);
  444. /* PHY_928 PHY_PAD_ADDR_DRIVE */
  445. clrsetbits_le32(&denali_phy[928], 0xff << 20, reg_value << 20);
  446. /* PHY_929 PHY_PAD_CLK_DRIVE */
  447. clrsetbits_le32(&denali_phy[929], 0xff << 22, reg_value << 22);
  448. /* PHY_935 PHY_PAD_CKE_DRIVE */
  449. clrsetbits_le32(&denali_phy[935], 0xff << 20, reg_value << 20);
  450. /* PHY_937 PHY_PAD_RST_DRIVE */
  451. clrsetbits_le32(&denali_phy[937], 0xff << 20, reg_value << 20);
  452. /* PHY_939 PHY_PAD_CS_DRIVE */
  453. clrsetbits_le32(&denali_phy[939], 0xff << 20, reg_value << 20);
  454. /* SLEWP_EN & SLEWN_EN */
  455. reg_value = ((PHY_SLEWP_EN << 3) | PHY_SLEWN_EN);
  456. /* PHY_924 PHY_PAD_FDBK_DRIVE */
  457. clrsetbits_le32(&denali_phy[924], 0x3f << 8, reg_value << 8);
  458. /* PHY_926 PHY_PAD_DATA_DRIVE */
  459. clrsetbits_le32(&denali_phy[926], 0x3f, reg_value);
  460. /* PHY_927 PHY_PAD_DQS_DRIVE */
  461. clrsetbits_le32(&denali_phy[927], 0x3f, reg_value);
  462. /* PHY_928 PHY_PAD_ADDR_DRIVE */
  463. clrsetbits_le32(&denali_phy[928], 0x3f << 8, reg_value << 8);
  464. /* PHY_929 PHY_PAD_CLK_DRIVE */
  465. clrsetbits_le32(&denali_phy[929], 0x3f << 8, reg_value << 8);
  466. /* PHY_935 PHY_PAD_CKE_DRIVE */
  467. clrsetbits_le32(&denali_phy[935], 0x3f << 8, reg_value << 8);
  468. /* PHY_937 PHY_PAD_RST_DRIVE */
  469. clrsetbits_le32(&denali_phy[937], 0x3f << 8, reg_value << 8);
  470. /* PHY_939 PHY_PAD_CS_DRIVE */
  471. clrsetbits_le32(&denali_phy[939], 0x3f << 8, reg_value << 8);
  472. }
  473. /* speed setting */
  474. speed = 0x2;
  475. /* PHY_924 PHY_PAD_FDBK_DRIVE */
  476. clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
  477. /* PHY_926 PHY_PAD_DATA_DRIVE */
  478. clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
  479. /* PHY_927 PHY_PAD_DQS_DRIVE */
  480. clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
  481. /* PHY_928 PHY_PAD_ADDR_DRIVE */
  482. clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
  483. /* PHY_929 PHY_PAD_CLK_DRIVE */
  484. clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
  485. /* PHY_935 PHY_PAD_CKE_DRIVE */
  486. clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
  487. /* PHY_937 PHY_PAD_RST_DRIVE */
  488. clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
  489. /* PHY_939 PHY_PAD_CS_DRIVE */
  490. clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
  491. if (params->base.dramtype == LPDDR4) {
  492. /* RX_CM_INPUT */
  493. reg_value = PHY_RX_CM_INPUT;
  494. /* PHY_924 PHY_PAD_FDBK_DRIVE */
  495. clrsetbits_le32(&denali_phy[924], 0x1 << 14, reg_value << 14);
  496. /* PHY_926 PHY_PAD_DATA_DRIVE */
  497. clrsetbits_le32(&denali_phy[926], 0x1 << 11, reg_value << 11);
  498. /* PHY_927 PHY_PAD_DQS_DRIVE */
  499. clrsetbits_le32(&denali_phy[927], 0x1 << 13, reg_value << 13);
  500. /* PHY_928 PHY_PAD_ADDR_DRIVE */
  501. clrsetbits_le32(&denali_phy[928], 0x1 << 19, reg_value << 19);
  502. /* PHY_929 PHY_PAD_CLK_DRIVE */
  503. clrsetbits_le32(&denali_phy[929], 0x1 << 21, reg_value << 21);
  504. /* PHY_935 PHY_PAD_CKE_DRIVE */
  505. clrsetbits_le32(&denali_phy[935], 0x1 << 19, reg_value << 19);
  506. /* PHY_937 PHY_PAD_RST_DRIVE */
  507. clrsetbits_le32(&denali_phy[937], 0x1 << 19, reg_value << 19);
  508. /* PHY_939 PHY_PAD_CS_DRIVE */
  509. clrsetbits_le32(&denali_phy[939], 0x1 << 19, reg_value << 19);
  510. }
  511. return 0;
  512. }
  513. static void set_ds_odt(const struct chan_info *chan,
  514. struct rk3399_sdram_params *params,
  515. bool ctl_phy_reg, u32 mr5)
  516. {
  517. u32 *denali_phy = get_denali_phy(chan, params, ctl_phy_reg);
  518. u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
  519. u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
  520. u32 tsel_idle_select_p, tsel_rd_select_p;
  521. u32 tsel_idle_select_n, tsel_rd_select_n;
  522. u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
  523. u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
  524. u32 tsel_ckcs_select_p, tsel_ckcs_select_n;
  525. struct io_setting *io = NULL;
  526. u32 soc_odt = 0;
  527. u32 reg_value;
  528. if (params->base.dramtype == LPDDR4) {
  529. io = lpddr4_get_io_settings(params, mr5);
  530. tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
  531. tsel_rd_select_n = io->rd_odt;
  532. tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
  533. tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
  534. tsel_wr_select_dq_p = io->wr_dq_drv;
  535. tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
  536. tsel_wr_select_ca_p = io->wr_ca_drv;
  537. tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
  538. tsel_ckcs_select_p = io->wr_ckcs_drv;
  539. tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
  540. switch (tsel_rd_select_n) {
  541. case PHY_DRV_ODT_240:
  542. soc_odt = 1;
  543. break;
  544. case PHY_DRV_ODT_120:
  545. soc_odt = 2;
  546. break;
  547. case PHY_DRV_ODT_80:
  548. soc_odt = 3;
  549. break;
  550. case PHY_DRV_ODT_60:
  551. soc_odt = 4;
  552. break;
  553. case PHY_DRV_ODT_48:
  554. soc_odt = 5;
  555. break;
  556. case PHY_DRV_ODT_40:
  557. soc_odt = 6;
  558. break;
  559. case PHY_DRV_ODT_34_3:
  560. soc_odt = 6;
  561. printf("%s: Unable to support LPDDR4 MR22 Soc ODT\n",
  562. __func__);
  563. break;
  564. case PHY_DRV_ODT_HI_Z:
  565. default:
  566. soc_odt = 0;
  567. break;
  568. }
  569. } else if (params->base.dramtype == LPDDR3) {
  570. tsel_rd_select_p = PHY_DRV_ODT_240;
  571. tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
  572. tsel_idle_select_p = PHY_DRV_ODT_240;
  573. tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
  574. tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
  575. tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
  576. tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
  577. tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
  578. tsel_ckcs_select_p = PHY_DRV_ODT_34_3;
  579. tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
  580. } else {
  581. tsel_rd_select_p = PHY_DRV_ODT_240;
  582. tsel_rd_select_n = PHY_DRV_ODT_240;
  583. tsel_idle_select_p = PHY_DRV_ODT_240;
  584. tsel_idle_select_n = PHY_DRV_ODT_240;
  585. tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
  586. tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
  587. tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
  588. tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
  589. tsel_ckcs_select_p = PHY_DRV_ODT_34_3;
  590. tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
  591. }
  592. if (params->base.odt == 1) {
  593. tsel_rd_en = 1;
  594. if (params->base.dramtype == LPDDR4)
  595. tsel_rd_en = io->rd_odt_en;
  596. } else {
  597. tsel_rd_en = 0;
  598. }
  599. tsel_wr_en = 0;
  600. tsel_idle_en = 0;
  601. /* F0_0 */
  602. clrsetbits_le32(&denali_ctl[145], 0xFF << 16,
  603. (soc_odt | (CS0_MR22_VAL << 3)) << 16);
  604. /* F2_0, F1_0 */
  605. clrsetbits_le32(&denali_ctl[146], 0xFF00FF,
  606. ((soc_odt | (CS0_MR22_VAL << 3)) << 16) |
  607. (soc_odt | (CS0_MR22_VAL << 3)));
  608. /* F0_1 */
  609. clrsetbits_le32(&denali_ctl[159], 0xFF << 16,
  610. (soc_odt | (CS1_MR22_VAL << 3)) << 16);
  611. /* F2_1, F1_1 */
  612. clrsetbits_le32(&denali_ctl[160], 0xFF00FF,
  613. ((soc_odt | (CS1_MR22_VAL << 3)) << 16) |
  614. (soc_odt | (CS1_MR22_VAL << 3)));
  615. /*
  616. * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0
  617. * sets termination values for read/idle cycles and drive strength
  618. * for write cycles for DQ/DM
  619. */
  620. reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
  621. (tsel_wr_select_dq_n << 8) | (tsel_wr_select_dq_p << 12) |
  622. (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20);
  623. clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value);
  624. clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value);
  625. clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value);
  626. clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value);
  627. /*
  628. * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0
  629. * sets termination values for read/idle cycles and drive strength
  630. * for write cycles for DQS
  631. */
  632. clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value);
  633. clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value);
  634. clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value);
  635. clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value);
  636. /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
  637. reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4);
  638. if (params->base.dramtype == LPDDR4) {
  639. /* LPDDR4 these register read always return 0, so
  640. * can not use clrsetbits_le32(), need to write32
  641. */
  642. writel((0x300 << 8) | reg_value, &denali_phy[544]);
  643. writel((0x300 << 8) | reg_value, &denali_phy[672]);
  644. writel((0x300 << 8) | reg_value, &denali_phy[800]);
  645. } else {
  646. clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
  647. clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
  648. clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
  649. }
  650. /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */
  651. clrsetbits_le32(&denali_phy[928], 0xff, reg_value);
  652. /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */
  653. if (!ctl_phy_reg)
  654. clrsetbits_le32(&denali_phy[937], 0xff, reg_value);
  655. /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */
  656. clrsetbits_le32(&denali_phy[935], 0xff, reg_value);
  657. /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */
  658. clrsetbits_le32(&denali_phy[939], 0xff,
  659. tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4));
  660. /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */
  661. clrsetbits_le32(&denali_phy[929], 0xff,
  662. tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4));
  663. /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
  664. clrsetbits_le32(&denali_phy[924], 0xff,
  665. tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 4));
  666. clrsetbits_le32(&denali_phy[925], 0xff,
  667. tsel_wr_select_dq_n | (tsel_wr_select_dq_p << 4));
  668. /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */
  669. reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
  670. << 16;
  671. clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value);
  672. clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value);
  673. clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value);
  674. clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value);
  675. /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */
  676. reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
  677. << 24;
  678. clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value);
  679. clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value);
  680. clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value);
  681. clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value);
  682. /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */
  683. reg_value = tsel_wr_en << 8;
  684. clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value);
  685. clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value);
  686. clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value);
  687. /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */
  688. reg_value = tsel_wr_en << 17;
  689. clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value);
  690. /*
  691. * pad_rst/cke/cs/clk_term tsel 1bits
  692. * DENALI_PHY_938/936/940/934 offset_17
  693. */
  694. clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value);
  695. clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value);
  696. clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value);
  697. clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value);
  698. /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
  699. clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
  700. phy_io_config(denali_phy, denali_ctl, params, mr5);
  701. }
  702. static void pctl_start(struct dram_info *dram,
  703. struct rk3399_sdram_params *params,
  704. u32 channel_mask)
  705. {
  706. const struct chan_info *chan_0 = &dram->chan[0];
  707. const struct chan_info *chan_1 = &dram->chan[1];
  708. u32 *denali_ctl_0 = chan_0->pctl->denali_ctl;
  709. u32 *denali_phy_0 = chan_0->publ->denali_phy;
  710. u32 *ddrc0_con_0 = get_ddrc0_con(dram, 0);
  711. u32 *denali_ctl_1 = chan_1->pctl->denali_ctl;
  712. u32 *denali_phy_1 = chan_1->publ->denali_phy;
  713. u32 *ddrc1_con_0 = get_ddrc0_con(dram, 1);
  714. u32 count = 0;
  715. u32 byte, tmp;
  716. /* PHY_DLL_RST_EN */
  717. if (channel_mask & 1) {
  718. writel(0x01000000, &ddrc0_con_0);
  719. clrsetbits_le32(&denali_phy_0[957], 0x3 << 24, 0x2 << 24);
  720. }
  721. if (channel_mask & 1) {
  722. count = 0;
  723. while (!(readl(&denali_ctl_0[203]) & (1 << 3))) {
  724. if (count > 1000) {
  725. printf("%s: Failed to init pctl channel 0\n",
  726. __func__);
  727. while (1)
  728. ;
  729. }
  730. udelay(1);
  731. count++;
  732. }
  733. writel(0x01000100, &ddrc0_con_0);
  734. for (byte = 0; byte < 4; byte++) {
  735. tmp = 0x820;
  736. writel((tmp << 16) | tmp,
  737. &denali_phy_0[53 + (128 * byte)]);
  738. writel((tmp << 16) | tmp,
  739. &denali_phy_0[54 + (128 * byte)]);
  740. writel((tmp << 16) | tmp,
  741. &denali_phy_0[55 + (128 * byte)]);
  742. writel((tmp << 16) | tmp,
  743. &denali_phy_0[56 + (128 * byte)]);
  744. writel((tmp << 16) | tmp,
  745. &denali_phy_0[57 + (128 * byte)]);
  746. clrsetbits_le32(&denali_phy_0[58 + (128 * byte)],
  747. 0xffff, tmp);
  748. }
  749. clrsetbits_le32(&denali_ctl_0[68], PWRUP_SREFRESH_EXIT,
  750. dram->pwrup_srefresh_exit[0]);
  751. }
  752. if (channel_mask & 2) {
  753. writel(0x01000000, &ddrc1_con_0);
  754. clrsetbits_le32(&denali_phy_1[957], 0x3 << 24, 0x2 << 24);
  755. }
  756. if (channel_mask & 2) {
  757. count = 0;
  758. while (!(readl(&denali_ctl_1[203]) & (1 << 3))) {
  759. if (count > 1000) {
  760. printf("%s: Failed to init pctl channel 1\n",
  761. __func__);
  762. while (1)
  763. ;
  764. }
  765. udelay(1);
  766. count++;
  767. }
  768. writel(0x01000100, &ddrc1_con_0);
  769. for (byte = 0; byte < 4; byte++) {
  770. tmp = 0x820;
  771. writel((tmp << 16) | tmp,
  772. &denali_phy_1[53 + (128 * byte)]);
  773. writel((tmp << 16) | tmp,
  774. &denali_phy_1[54 + (128 * byte)]);
  775. writel((tmp << 16) | tmp,
  776. &denali_phy_1[55 + (128 * byte)]);
  777. writel((tmp << 16) | tmp,
  778. &denali_phy_1[56 + (128 * byte)]);
  779. writel((tmp << 16) | tmp,
  780. &denali_phy_1[57 + (128 * byte)]);
  781. clrsetbits_le32(&denali_phy_1[58 + (128 * byte)],
  782. 0xffff, tmp);
  783. }
  784. clrsetbits_le32(&denali_ctl_1[68], PWRUP_SREFRESH_EXIT,
  785. dram->pwrup_srefresh_exit[1]);
  786. /*
  787. * restore channel 1 RESET original setting
  788. * to avoid 240ohm too weak to prevent ESD test
  789. */
  790. if (params->base.dramtype == LPDDR4)
  791. clrsetbits_le32(&denali_phy_1[937], 0xff,
  792. params->phy_regs.denali_phy[937] &
  793. 0xFF);
  794. }
  795. }
  796. static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
  797. u32 channel, struct rk3399_sdram_params *params)
  798. {
  799. u32 *denali_ctl = chan->pctl->denali_ctl;
  800. u32 *denali_pi = chan->pi->denali_pi;
  801. u32 *denali_phy = chan->publ->denali_phy;
  802. const u32 *params_ctl = params->pctl_regs.denali_ctl;
  803. const u32 *params_phy = params->phy_regs.denali_phy;
  804. u32 tmp, tmp1, tmp2;
  805. struct rk3399_sdram_params *params_cfg;
  806. u32 byte;
  807. dram->ops->modify_param(chan, params);
  808. /*
  809. * work around controller bug:
  810. * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed
  811. */
  812. sdram_copy_to_reg(&denali_ctl[1], &params_ctl[1],
  813. sizeof(struct rk3399_ddr_pctl_regs) - 4);
  814. writel(params_ctl[0], &denali_ctl[0]);
  815. /*
  816. * two channel init at the same time, then ZQ Cal Start
  817. * at the same time, it will use the same RZQ, but cannot
  818. * start at the same time.
  819. *
  820. * So, increase tINIT3 for channel 1, will avoid two
  821. * channel ZQ Cal Start at the same time
  822. */
  823. if (params->base.dramtype == LPDDR4 && channel == 1) {
  824. tmp = ((params->base.ddr_freq * MHz + 999) / 1000);
  825. tmp1 = readl(&denali_ctl[14]);
  826. writel(tmp + tmp1, &denali_ctl[14]);
  827. }
  828. sdram_copy_to_reg(denali_pi, &params->pi_regs.denali_pi[0],
  829. sizeof(struct rk3399_ddr_pi_regs));
  830. /* rank count need to set for init */
  831. set_memory_map(chan, channel, params);
  832. writel(params->phy_regs.denali_phy[910], &denali_phy[910]);
  833. writel(params->phy_regs.denali_phy[911], &denali_phy[911]);
  834. writel(params->phy_regs.denali_phy[912], &denali_phy[912]);
  835. if (params->base.dramtype == LPDDR4) {
  836. writel(params->phy_regs.denali_phy[898], &denali_phy[898]);
  837. writel(params->phy_regs.denali_phy[919], &denali_phy[919]);
  838. }
  839. dram->pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) &
  840. PWRUP_SREFRESH_EXIT;
  841. clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
  842. /* PHY_DLL_RST_EN */
  843. clrsetbits_le32(&denali_phy[957], 0x3 << 24, 1 << 24);
  844. setbits_le32(&denali_pi[0], START);
  845. setbits_le32(&denali_ctl[0], START);
  846. /**
  847. * LPDDR4 use PLL bypass mode for init
  848. * not need to wait for the PLL to lock
  849. */
  850. if (params->base.dramtype != LPDDR4) {
  851. /* Waiting for phy DLL lock */
  852. while (1) {
  853. tmp = readl(&denali_phy[920]);
  854. tmp1 = readl(&denali_phy[921]);
  855. tmp2 = readl(&denali_phy[922]);
  856. if ((((tmp >> 16) & 0x1) == 0x1) &&
  857. (((tmp1 >> 16) & 0x1) == 0x1) &&
  858. (((tmp1 >> 0) & 0x1) == 0x1) &&
  859. (((tmp2 >> 0) & 0x1) == 0x1))
  860. break;
  861. }
  862. }
  863. sdram_copy_to_reg(&denali_phy[896], &params_phy[896], (958 - 895) * 4);
  864. sdram_copy_to_reg(&denali_phy[0], &params_phy[0], (90 - 0 + 1) * 4);
  865. sdram_copy_to_reg(&denali_phy[128], &params_phy[128],
  866. (218 - 128 + 1) * 4);
  867. sdram_copy_to_reg(&denali_phy[256], &params_phy[256],
  868. (346 - 256 + 1) * 4);
  869. sdram_copy_to_reg(&denali_phy[384], &params_phy[384],
  870. (474 - 384 + 1) * 4);
  871. sdram_copy_to_reg(&denali_phy[512], &params_phy[512],
  872. (549 - 512 + 1) * 4);
  873. sdram_copy_to_reg(&denali_phy[640], &params_phy[640],
  874. (677 - 640 + 1) * 4);
  875. sdram_copy_to_reg(&denali_phy[768], &params_phy[768],
  876. (805 - 768 + 1) * 4);
  877. if (params->base.dramtype == LPDDR4)
  878. params_cfg = dram->ops->get_phy_index_params(1, params);
  879. else
  880. params_cfg = dram->ops->get_phy_index_params(0, params);
  881. clrsetbits_le32(&params_cfg->phy_regs.denali_phy[896], 0x3 << 8,
  882. 0 << 8);
  883. writel(params_cfg->phy_regs.denali_phy[896], &denali_phy[896]);
  884. writel(params->phy_regs.denali_phy[83] + (0x10 << 16),
  885. &denali_phy[83]);
  886. writel(params->phy_regs.denali_phy[84] + (0x10 << 8),
  887. &denali_phy[84]);
  888. writel(params->phy_regs.denali_phy[211] + (0x10 << 16),
  889. &denali_phy[211]);
  890. writel(params->phy_regs.denali_phy[212] + (0x10 << 8),
  891. &denali_phy[212]);
  892. writel(params->phy_regs.denali_phy[339] + (0x10 << 16),
  893. &denali_phy[339]);
  894. writel(params->phy_regs.denali_phy[340] + (0x10 << 8),
  895. &denali_phy[340]);
  896. writel(params->phy_regs.denali_phy[467] + (0x10 << 16),
  897. &denali_phy[467]);
  898. writel(params->phy_regs.denali_phy[468] + (0x10 << 8),
  899. &denali_phy[468]);
  900. if (params->base.dramtype == LPDDR4) {
  901. /*
  902. * to improve write dqs and dq phase from 1.5ns to 3.5ns
  903. * at 50MHz. this's the measure result from oscilloscope
  904. * of dqs and dq write signal.
  905. */
  906. for (byte = 0; byte < 4; byte++) {
  907. tmp = 0x680;
  908. clrsetbits_le32(&denali_phy[1 + (128 * byte)],
  909. 0xfff << 8, tmp << 8);
  910. }
  911. /*
  912. * to workaround 366ball two channel's RESET connect to
  913. * one RESET signal of die
  914. */
  915. if (channel == 1)
  916. clrsetbits_le32(&denali_phy[937], 0xff,
  917. PHY_DRV_ODT_240 |
  918. (PHY_DRV_ODT_240 << 0x4));
  919. }
  920. return 0;
  921. }
  922. static void select_per_cs_training_index(const struct chan_info *chan,
  923. u32 rank)
  924. {
  925. u32 *denali_phy = chan->publ->denali_phy;
  926. /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */
  927. if ((readl(&denali_phy[84]) >> 16) & 1) {
  928. /*
  929. * PHY_8/136/264/392
  930. * phy_per_cs_training_index_X 1bit offset_24
  931. */
  932. clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24);
  933. clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24);
  934. clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24);
  935. clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24);
  936. }
  937. }
  938. static void override_write_leveling_value(const struct chan_info *chan)
  939. {
  940. u32 *denali_ctl = chan->pctl->denali_ctl;
  941. u32 *denali_phy = chan->publ->denali_phy;
  942. u32 byte;
  943. /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
  944. setbits_le32(&denali_phy[896], 1);
  945. /*
  946. * PHY_8/136/264/392
  947. * phy_per_cs_training_multicast_en_X 1bit offset_16
  948. */
  949. clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16);
  950. clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16);
  951. clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16);
  952. clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16);
  953. for (byte = 0; byte < 4; byte++)
  954. clrsetbits_le32(&denali_phy[63 + (128 * byte)], 0xffff << 16,
  955. 0x200 << 16);
  956. /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
  957. clrbits_le32(&denali_phy[896], 1);
  958. /* CTL_200 ctrlupd_req 1bit offset_8 */
  959. clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8);
  960. }
  961. static int data_training_ca(const struct chan_info *chan, u32 channel,
  962. const struct rk3399_sdram_params *params)
  963. {
  964. u32 *denali_pi = chan->pi->denali_pi;
  965. u32 *denali_phy = chan->publ->denali_phy;
  966. u32 i, tmp;
  967. u32 obs_0, obs_1, obs_2, obs_err = 0;
  968. u32 rank = params->ch[channel].cap_info.rank;
  969. u32 rank_mask;
  970. /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
  971. writel(0x00003f7c, (&denali_pi[175]));
  972. if (params->base.dramtype == LPDDR4)
  973. rank_mask = (rank == 1) ? 0x5 : 0xf;
  974. else
  975. rank_mask = (rank == 1) ? 0x1 : 0x3;
  976. for (i = 0; i < 4; i++) {
  977. if (!(rank_mask & (1 << i)))
  978. continue;
  979. select_per_cs_training_index(chan, i);
  980. /* PI_100 PI_CALVL_EN:RW:8:2 */
  981. clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8);
  982. /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */
  983. clrsetbits_le32(&denali_pi[92],
  984. (0x1 << 16) | (0x3 << 24),
  985. (0x1 << 16) | (i << 24));
  986. /* Waiting for training complete */
  987. while (1) {
  988. /* PI_174 PI_INT_STATUS:RD:8:18 */
  989. tmp = readl(&denali_pi[174]) >> 8;
  990. /*
  991. * check status obs
  992. * PHY_532/660/789 phy_adr_calvl_obs1_:0:32
  993. */
  994. obs_0 = readl(&denali_phy[532]);
  995. obs_1 = readl(&denali_phy[660]);
  996. obs_2 = readl(&denali_phy[788]);
  997. if (((obs_0 >> 30) & 0x3) ||
  998. ((obs_1 >> 30) & 0x3) ||
  999. ((obs_2 >> 30) & 0x3))
  1000. obs_err = 1;
  1001. if ((((tmp >> 11) & 0x1) == 0x1) &&
  1002. (((tmp >> 13) & 0x1) == 0x1) &&
  1003. (((tmp >> 5) & 0x1) == 0x0) &&
  1004. obs_err == 0)
  1005. break;
  1006. else if ((((tmp >> 5) & 0x1) == 0x1) ||
  1007. (obs_err == 1))
  1008. return -EIO;
  1009. }
  1010. /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
  1011. writel(0x00003f7c, (&denali_pi[175]));
  1012. }
  1013. clrbits_le32(&denali_pi[100], 0x3 << 8);
  1014. return 0;
  1015. }
  1016. static int data_training_wl(const struct chan_info *chan, u32 channel,
  1017. const struct rk3399_sdram_params *params)
  1018. {
  1019. u32 *denali_pi = chan->pi->denali_pi;
  1020. u32 *denali_phy = chan->publ->denali_phy;
  1021. u32 i, tmp;
  1022. u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
  1023. u32 rank = params->ch[channel].cap_info.rank;
  1024. /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
  1025. writel(0x00003f7c, (&denali_pi[175]));
  1026. for (i = 0; i < rank; i++) {
  1027. select_per_cs_training_index(chan, i);
  1028. /* PI_60 PI_WRLVL_EN:RW:8:2 */
  1029. clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8);
  1030. /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */
  1031. clrsetbits_le32(&denali_pi[59],
  1032. (0x1 << 8) | (0x3 << 16),
  1033. (0x1 << 8) | (i << 16));
  1034. /* Waiting for training complete */
  1035. while (1) {
  1036. /* PI_174 PI_INT_STATUS:RD:8:18 */
  1037. tmp = readl(&denali_pi[174]) >> 8;
  1038. /*
  1039. * check status obs, if error maybe can not
  1040. * get leveling done PHY_40/168/296/424
  1041. * phy_wrlvl_status_obs_X:0:13
  1042. */
  1043. obs_0 = readl(&denali_phy[40]);
  1044. obs_1 = readl(&denali_phy[168]);
  1045. obs_2 = readl(&denali_phy[296]);
  1046. obs_3 = readl(&denali_phy[424]);
  1047. if (((obs_0 >> 12) & 0x1) ||
  1048. ((obs_1 >> 12) & 0x1) ||
  1049. ((obs_2 >> 12) & 0x1) ||
  1050. ((obs_3 >> 12) & 0x1))
  1051. obs_err = 1;
  1052. if ((((tmp >> 10) & 0x1) == 0x1) &&
  1053. (((tmp >> 13) & 0x1) == 0x1) &&
  1054. (((tmp >> 4) & 0x1) == 0x0) &&
  1055. obs_err == 0)
  1056. break;
  1057. else if ((((tmp >> 4) & 0x1) == 0x1) ||
  1058. (obs_err == 1))
  1059. return -EIO;
  1060. }
  1061. /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
  1062. writel(0x00003f7c, (&denali_pi[175]));
  1063. }
  1064. override_write_leveling_value(chan);
  1065. clrbits_le32(&denali_pi[60], 0x3 << 8);
  1066. return 0;
  1067. }
  1068. static int data_training_rg(const struct chan_info *chan, u32 channel,
  1069. const struct rk3399_sdram_params *params)
  1070. {
  1071. u32 *denali_pi = chan->pi->denali_pi;
  1072. u32 *denali_phy = chan->publ->denali_phy;
  1073. u32 i, tmp;
  1074. u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
  1075. u32 rank = params->ch[channel].cap_info.rank;
  1076. /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
  1077. writel(0x00003f7c, (&denali_pi[175]));
  1078. for (i = 0; i < rank; i++) {
  1079. select_per_cs_training_index(chan, i);
  1080. /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */
  1081. clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24);
  1082. /*
  1083. * PI_74 PI_RDLVL_GATE_REQ:WR:16:1
  1084. * PI_RDLVL_CS:RW:24:2
  1085. */
  1086. clrsetbits_le32(&denali_pi[74],
  1087. (0x1 << 16) | (0x3 << 24),
  1088. (0x1 << 16) | (i << 24));
  1089. /* Waiting for training complete */
  1090. while (1) {
  1091. /* PI_174 PI_INT_STATUS:RD:8:18 */
  1092. tmp = readl(&denali_pi[174]) >> 8;
  1093. /*
  1094. * check status obs
  1095. * PHY_43/171/299/427
  1096. * PHY_GTLVL_STATUS_OBS_x:16:8
  1097. */
  1098. obs_0 = readl(&denali_phy[43]);
  1099. obs_1 = readl(&denali_phy[171]);
  1100. obs_2 = readl(&denali_phy[299]);
  1101. obs_3 = readl(&denali_phy[427]);
  1102. if (((obs_0 >> (16 + 6)) & 0x3) ||
  1103. ((obs_1 >> (16 + 6)) & 0x3) ||
  1104. ((obs_2 >> (16 + 6)) & 0x3) ||
  1105. ((obs_3 >> (16 + 6)) & 0x3))
  1106. obs_err = 1;
  1107. if ((((tmp >> 9) & 0x1) == 0x1) &&
  1108. (((tmp >> 13) & 0x1) == 0x1) &&
  1109. (((tmp >> 3) & 0x1) == 0x0) &&
  1110. obs_err == 0)
  1111. break;
  1112. else if ((((tmp >> 3) & 0x1) == 0x1) ||
  1113. (obs_err == 1))
  1114. return -EIO;
  1115. }
  1116. /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
  1117. writel(0x00003f7c, (&denali_pi[175]));
  1118. }
  1119. clrbits_le32(&denali_pi[80], 0x3 << 24);
  1120. return 0;
  1121. }
  1122. static int data_training_rl(const struct chan_info *chan, u32 channel,
  1123. const struct rk3399_sdram_params *params)
  1124. {
  1125. u32 *denali_pi = chan->pi->denali_pi;
  1126. u32 i, tmp;
  1127. u32 rank = params->ch[channel].cap_info.rank;
  1128. /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
  1129. writel(0x00003f7c, (&denali_pi[175]));
  1130. for (i = 0; i < rank; i++) {
  1131. select_per_cs_training_index(chan, i);
  1132. /* PI_80 PI_RDLVL_EN:RW:16:2 */
  1133. clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16);
  1134. /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */
  1135. clrsetbits_le32(&denali_pi[74],
  1136. (0x1 << 8) | (0x3 << 24),
  1137. (0x1 << 8) | (i << 24));
  1138. /* Waiting for training complete */
  1139. while (1) {
  1140. /* PI_174 PI_INT_STATUS:RD:8:18 */
  1141. tmp = readl(&denali_pi[174]) >> 8;
  1142. /*
  1143. * make sure status obs not report error bit
  1144. * PHY_46/174/302/430
  1145. * phy_rdlvl_status_obs_X:16:8
  1146. */
  1147. if ((((tmp >> 8) & 0x1) == 0x1) &&
  1148. (((tmp >> 13) & 0x1) == 0x1) &&
  1149. (((tmp >> 2) & 0x1) == 0x0))
  1150. break;
  1151. else if (((tmp >> 2) & 0x1) == 0x1)
  1152. return -EIO;
  1153. }
  1154. /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
  1155. writel(0x00003f7c, (&denali_pi[175]));
  1156. }
  1157. clrbits_le32(&denali_pi[80], 0x3 << 16);
  1158. return 0;
  1159. }
  1160. static int data_training_wdql(const struct chan_info *chan, u32 channel,
  1161. const struct rk3399_sdram_params *params)
  1162. {
  1163. u32 *denali_pi = chan->pi->denali_pi;
  1164. u32 i, tmp;
  1165. u32 rank = params->ch[channel].cap_info.rank;
  1166. u32 rank_mask;
  1167. /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
  1168. writel(0x00003f7c, (&denali_pi[175]));
  1169. if (params->base.dramtype == LPDDR4)
  1170. rank_mask = (rank == 1) ? 0x5 : 0xf;
  1171. else
  1172. rank_mask = (rank == 1) ? 0x1 : 0x3;
  1173. for (i = 0; i < 4; i++) {
  1174. if (!(rank_mask & (1 << i)))
  1175. continue;
  1176. select_per_cs_training_index(chan, i);
  1177. /*
  1178. * disable PI_WDQLVL_VREF_EN before wdq leveling?
  1179. * PI_117 PI_WDQLVL_VREF_EN:RW:8:1
  1180. */
  1181. clrbits_le32(&denali_pi[117], 0x1 << 8);
  1182. /* PI_124 PI_WDQLVL_EN:RW:16:2 */
  1183. clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16);
  1184. /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */
  1185. clrsetbits_le32(&denali_pi[121],
  1186. (0x1 << 8) | (0x3 << 16),
  1187. (0x1 << 8) | (i << 16));
  1188. /* Waiting for training complete */
  1189. while (1) {
  1190. /* PI_174 PI_INT_STATUS:RD:8:18 */
  1191. tmp = readl(&denali_pi[174]) >> 8;
  1192. if ((((tmp >> 12) & 0x1) == 0x1) &&
  1193. (((tmp >> 13) & 0x1) == 0x1) &&
  1194. (((tmp >> 6) & 0x1) == 0x0))
  1195. break;
  1196. else if (((tmp >> 6) & 0x1) == 0x1)
  1197. return -EIO;
  1198. }
  1199. /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
  1200. writel(0x00003f7c, (&denali_pi[175]));
  1201. }
  1202. clrbits_le32(&denali_pi[124], 0x3 << 16);
  1203. return 0;
  1204. }
  1205. static int data_training(struct dram_info *dram, u32 channel,
  1206. const struct rk3399_sdram_params *params,
  1207. u32 training_flag)
  1208. {
  1209. struct chan_info *chan = &dram->chan[channel];
  1210. u32 *denali_phy = chan->publ->denali_phy;
  1211. int ret;
  1212. /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */
  1213. setbits_le32(&denali_phy[927], (1 << 22));
  1214. if (training_flag == PI_FULL_TRAINING) {
  1215. if (params->base.dramtype == LPDDR4) {
  1216. training_flag = PI_WRITE_LEVELING |
  1217. PI_READ_GATE_TRAINING |
  1218. PI_READ_LEVELING | PI_WDQ_LEVELING;
  1219. } else if (params->base.dramtype == LPDDR3) {
  1220. training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
  1221. PI_READ_GATE_TRAINING;
  1222. } else if (params->base.dramtype == DDR3) {
  1223. training_flag = PI_WRITE_LEVELING |
  1224. PI_READ_GATE_TRAINING |
  1225. PI_READ_LEVELING;
  1226. }
  1227. }
  1228. /* ca training(LPDDR4,LPDDR3 support) */
  1229. if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) {
  1230. ret = data_training_ca(chan, channel, params);
  1231. if (ret < 0) {
  1232. debug("%s: data training ca failed\n", __func__);
  1233. return ret;
  1234. }
  1235. }
  1236. /* write leveling(LPDDR4,LPDDR3,DDR3 support) */
  1237. if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) {
  1238. ret = data_training_wl(chan, channel, params);
  1239. if (ret < 0) {
  1240. debug("%s: data training wl failed\n", __func__);
  1241. return ret;
  1242. }
  1243. }
  1244. /* read gate training(LPDDR4,LPDDR3,DDR3 support) */
  1245. if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) {
  1246. ret = data_training_rg(chan, channel, params);
  1247. if (ret < 0) {
  1248. debug("%s: data training rg failed\n", __func__);
  1249. return ret;
  1250. }
  1251. }
  1252. /* read leveling(LPDDR4,LPDDR3,DDR3 support) */
  1253. if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) {
  1254. ret = data_training_rl(chan, channel, params);
  1255. if (ret < 0) {
  1256. debug("%s: data training rl failed\n", __func__);
  1257. return ret;
  1258. }
  1259. }
  1260. /* wdq leveling(LPDDR4 support) */
  1261. if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) {
  1262. ret = data_training_wdql(chan, channel, params);
  1263. if (ret < 0) {
  1264. debug("%s: data training wdql failed\n", __func__);
  1265. return ret;
  1266. }
  1267. }
  1268. /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */
  1269. clrbits_le32(&denali_phy[927], (1 << 22));
  1270. return 0;
  1271. }
  1272. static void set_ddrconfig(const struct chan_info *chan,
  1273. const struct rk3399_sdram_params *params,
  1274. unsigned char channel, u32 ddrconfig)
  1275. {
  1276. /* only need to set ddrconfig */
  1277. struct msch_regs *ddr_msch_regs = chan->msch;
  1278. unsigned int cs0_cap = 0;
  1279. unsigned int cs1_cap = 0;
  1280. cs0_cap = (1 << (params->ch[channel].cap_info.cs0_row
  1281. + params->ch[channel].cap_info.col
  1282. + params->ch[channel].cap_info.bk
  1283. + params->ch[channel].cap_info.bw - 20));
  1284. if (params->ch[channel].cap_info.rank > 1)
  1285. cs1_cap = cs0_cap >> (params->ch[channel].cap_info.cs0_row
  1286. - params->ch[channel].cap_info.cs1_row);
  1287. if (params->ch[channel].cap_info.row_3_4) {
  1288. cs0_cap = cs0_cap * 3 / 4;
  1289. cs1_cap = cs1_cap * 3 / 4;
  1290. }
  1291. writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf);
  1292. writel(((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8),
  1293. &ddr_msch_regs->ddrsize);
  1294. }
  1295. static void sdram_msch_config(struct msch_regs *msch,
  1296. struct sdram_msch_timings *noc_timings)
  1297. {
  1298. writel(noc_timings->ddrtiminga0.d32,
  1299. &msch->ddrtiminga0.d32);
  1300. writel(noc_timings->ddrtimingb0.d32,
  1301. &msch->ddrtimingb0.d32);
  1302. writel(noc_timings->ddrtimingc0.d32,
  1303. &msch->ddrtimingc0.d32);
  1304. writel(noc_timings->devtodev0.d32,
  1305. &msch->devtodev0.d32);
  1306. writel(noc_timings->ddrmode.d32,
  1307. &msch->ddrmode.d32);
  1308. }
  1309. static void dram_all_config(struct dram_info *dram,
  1310. struct rk3399_sdram_params *params)
  1311. {
  1312. u32 sys_reg2 = 0;
  1313. u32 sys_reg3 = 0;
  1314. unsigned int channel, idx;
  1315. for (channel = 0, idx = 0;
  1316. (idx < params->base.num_channels) && (channel < 2);
  1317. channel++) {
  1318. struct msch_regs *ddr_msch_regs;
  1319. struct sdram_msch_timings *noc_timing;
  1320. if (params->ch[channel].cap_info.col == 0)
  1321. continue;
  1322. idx++;
  1323. sdram_org_config(&params->ch[channel].cap_info,
  1324. &params->base, &sys_reg2,
  1325. &sys_reg3, channel);
  1326. ddr_msch_regs = dram->chan[channel].msch;
  1327. noc_timing = &params->ch[channel].noc_timings;
  1328. sdram_msch_config(ddr_msch_regs, noc_timing);
  1329. /**
  1330. * rank 1 memory clock disable (dfi_dram_clk_disable = 1)
  1331. *
  1332. * The hardware for LPDDR4 with
  1333. * - CLK0P/N connect to lower 16-bits
  1334. * - CLK1P/N connect to higher 16-bits
  1335. *
  1336. * dfi dram clk is configured via CLK1P/N, so disabling
  1337. * dfi dram clk will disable the CLK1P/N as well for lpddr4.
  1338. */
  1339. if (params->ch[channel].cap_info.rank == 1 &&
  1340. params->base.dramtype != LPDDR4)
  1341. setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
  1342. 1 << 17);
  1343. }
  1344. writel(sys_reg2, &dram->pmugrf->os_reg2);
  1345. writel(sys_reg3, &dram->pmugrf->os_reg3);
  1346. rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,
  1347. params->base.stride << 10);
  1348. /* reboot hold register set */
  1349. writel(PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) |
  1350. PRESET_GPIO1_HOLD(1),
  1351. &dram->pmucru->pmucru_rstnhold_con[1]);
  1352. clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3);
  1353. }
  1354. static void set_cap_relate_config(const struct chan_info *chan,
  1355. struct rk3399_sdram_params *params,
  1356. unsigned int channel)
  1357. {
  1358. u32 *denali_ctl = chan->pctl->denali_ctl;
  1359. u32 tmp;
  1360. struct sdram_msch_timings *noc_timing;
  1361. if (params->base.dramtype == LPDDR3) {
  1362. tmp = (8 << params->ch[channel].cap_info.bw) /
  1363. (8 << params->ch[channel].cap_info.dbw);
  1364. /**
  1365. * memdata_ratio
  1366. * 1 -> 0, 2 -> 1, 4 -> 2
  1367. */
  1368. clrsetbits_le32(&denali_ctl[197], 0x7,
  1369. (tmp >> 1));
  1370. clrsetbits_le32(&denali_ctl[198], 0x7 << 8,
  1371. (tmp >> 1) << 8);
  1372. }
  1373. noc_timing = &params->ch[channel].noc_timings;
  1374. /*
  1375. * noc timing bw relate timing is 32 bit, and real bw is 16bit
  1376. * actually noc reg is setting at function dram_all_config
  1377. */
  1378. if (params->ch[channel].cap_info.bw == 16 &&
  1379. noc_timing->ddrmode.b.mwrsize == 2) {
  1380. if (noc_timing->ddrmode.b.burstsize)
  1381. noc_timing->ddrmode.b.burstsize -= 1;
  1382. noc_timing->ddrmode.b.mwrsize -= 1;
  1383. noc_timing->ddrtimingc0.b.burstpenalty *= 2;
  1384. noc_timing->ddrtimingc0.b.wrtomwr *= 2;
  1385. }
  1386. }
  1387. static u32 calculate_ddrconfig(struct rk3399_sdram_params *params, u32 channel)
  1388. {
  1389. unsigned int cs0_row = params->ch[channel].cap_info.cs0_row;
  1390. unsigned int col = params->ch[channel].cap_info.col;
  1391. unsigned int bw = params->ch[channel].cap_info.bw;
  1392. u16 ddr_cfg_2_rbc[] = {
  1393. /*
  1394. * [6] highest bit col
  1395. * [5:3] max row(14+n)
  1396. * [2] insertion row
  1397. * [1:0] col(9+n),col, data bus 32bit
  1398. *
  1399. * highbitcol, max_row, insertion_row, col
  1400. */
  1401. ((0 << 6) | (2 << 3) | (0 << 2) | 0), /* 0 */
  1402. ((0 << 6) | (2 << 3) | (0 << 2) | 1), /* 1 */
  1403. ((0 << 6) | (1 << 3) | (0 << 2) | 2), /* 2 */
  1404. ((0 << 6) | (0 << 3) | (0 << 2) | 3), /* 3 */
  1405. ((0 << 6) | (2 << 3) | (1 << 2) | 1), /* 4 */
  1406. ((0 << 6) | (1 << 3) | (1 << 2) | 2), /* 5 */
  1407. ((1 << 6) | (0 << 3) | (0 << 2) | 2), /* 6 */
  1408. ((1 << 6) | (1 << 3) | (0 << 2) | 2), /* 7 */
  1409. };
  1410. u32 i;
  1411. col -= (bw == 2) ? 0 : 1;
  1412. col -= 9;
  1413. for (i = 0; i < 4; i++) {
  1414. if ((col == (ddr_cfg_2_rbc[i] & 0x3)) &&
  1415. (cs0_row <= (((ddr_cfg_2_rbc[i] >> 3) & 0x7) + 14)))
  1416. break;
  1417. }
  1418. if (i >= 4)
  1419. i = -EINVAL;
  1420. return i;
  1421. }
  1422. static void set_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf, u32 stride)
  1423. {
  1424. rk_clrsetreg(&pmusgrf->soc_con4, 0x1f << 10, stride << 10);
  1425. }
  1426. #if !defined(CONFIG_RAM_RK3399_LPDDR4)
  1427. static int data_training_first(struct dram_info *dram, u32 channel, u8 rank,
  1428. struct rk3399_sdram_params *params)
  1429. {
  1430. u8 training_flag = PI_READ_GATE_TRAINING;
  1431. /*
  1432. * LPDDR3 CA training msut be trigger before
  1433. * other training.
  1434. * DDR3 is not have CA training.
  1435. */
  1436. if (params->base.dramtype == LPDDR3)
  1437. training_flag |= PI_CA_TRAINING;
  1438. return data_training(dram, channel, params, training_flag);
  1439. }
  1440. static int switch_to_phy_index1(struct dram_info *dram,
  1441. struct rk3399_sdram_params *params)
  1442. {
  1443. u32 channel;
  1444. u32 *denali_phy;
  1445. u32 ch_count = params->base.num_channels;
  1446. int ret;
  1447. int i = 0;
  1448. writel(RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1,
  1449. 1 << 4 | 1 << 2 | 1),
  1450. &dram->cic->cic_ctrl0);
  1451. while (!(readl(&dram->cic->cic_status0) & (1 << 2))) {
  1452. mdelay(10);
  1453. i++;
  1454. if (i > 10) {
  1455. debug("index1 frequency change overtime\n");
  1456. return -ETIME;
  1457. }
  1458. }
  1459. i = 0;
  1460. writel(RK_CLRSETBITS(1 << 1, 1 << 1), &dram->cic->cic_ctrl0);
  1461. while (!(readl(&dram->cic->cic_status0) & (1 << 0))) {
  1462. mdelay(10);
  1463. i++;
  1464. if (i > 10) {
  1465. debug("index1 frequency done overtime\n");
  1466. return -ETIME;
  1467. }
  1468. }
  1469. for (channel = 0; channel < ch_count; channel++) {
  1470. denali_phy = dram->chan[channel].publ->denali_phy;
  1471. clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
  1472. ret = data_training(dram, channel, params, PI_FULL_TRAINING);
  1473. if (ret < 0) {
  1474. debug("index1 training failed\n");
  1475. return ret;
  1476. }
  1477. }
  1478. return 0;
  1479. }
  1480. struct rk3399_sdram_params
  1481. *get_phy_index_params(u32 phy_fn,
  1482. struct rk3399_sdram_params *params)
  1483. {
  1484. if (phy_fn == 0)
  1485. return params;
  1486. else
  1487. return NULL;
  1488. }
  1489. void modify_param(const struct chan_info *chan,
  1490. struct rk3399_sdram_params *params)
  1491. {
  1492. struct rk3399_sdram_params *params_cfg;
  1493. u32 *denali_pi_params;
  1494. denali_pi_params = params->pi_regs.denali_pi;
  1495. /* modify PHY F0/F1/F2 params */
  1496. params_cfg = get_phy_index_params(0, params);
  1497. set_ds_odt(chan, params_cfg, false, 0);
  1498. clrsetbits_le32(&denali_pi_params[45], 0x1 << 24, 0x1 << 24);
  1499. clrsetbits_le32(&denali_pi_params[61], 0x1 << 24, 0x1 << 24);
  1500. clrsetbits_le32(&denali_pi_params[76], 0x1 << 24, 0x1 << 24);
  1501. clrsetbits_le32(&denali_pi_params[77], 0x1, 0x1);
  1502. }
  1503. #else
  1504. struct rk3399_sdram_params dfs_cfgs_lpddr4[] = {
  1505. #include "sdram-rk3399-lpddr4-400.inc"
  1506. #include "sdram-rk3399-lpddr4-800.inc"
  1507. };
  1508. static struct rk3399_sdram_params
  1509. *lpddr4_get_phy_index_params(u32 phy_fn,
  1510. struct rk3399_sdram_params *params)
  1511. {
  1512. if (phy_fn == 0)
  1513. return params;
  1514. else if (phy_fn == 1)
  1515. return &dfs_cfgs_lpddr4[1];
  1516. else if (phy_fn == 2)
  1517. return &dfs_cfgs_lpddr4[0];
  1518. else
  1519. return NULL;
  1520. }
  1521. static void *get_denali_pi(const struct chan_info *chan,
  1522. struct rk3399_sdram_params *params, bool reg)
  1523. {
  1524. return reg ? &chan->pi->denali_pi : &params->pi_regs.denali_pi;
  1525. }
  1526. static u32 lpddr4_get_phy_fn(struct rk3399_sdram_params *params, u32 ctl_fn)
  1527. {
  1528. u32 lpddr4_phy_fn[] = {1, 0, 0xb};
  1529. return lpddr4_phy_fn[ctl_fn];
  1530. }
  1531. static u32 lpddr4_get_ctl_fn(struct rk3399_sdram_params *params, u32 phy_fn)
  1532. {
  1533. u32 lpddr4_ctl_fn[] = {1, 0, 2};
  1534. return lpddr4_ctl_fn[phy_fn];
  1535. }
  1536. static u32 get_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf)
  1537. {
  1538. return ((readl(&pmusgrf->soc_con4) >> 10) & 0x1F);
  1539. }
  1540. /*
  1541. * read mr_num mode register
  1542. * rank = 1: cs0
  1543. * rank = 2: cs1
  1544. */
  1545. static int read_mr(struct rk3399_ddr_pctl_regs *ddr_pctl_regs, u32 rank,
  1546. u32 mr_num, u32 *buf)
  1547. {
  1548. s32 timeout = 100;
  1549. writel(((1 << 16) | (((rank == 2) ? 1 : 0) << 8) | mr_num) << 8,
  1550. &ddr_pctl_regs->denali_ctl[118]);
  1551. while (0 == (readl(&ddr_pctl_regs->denali_ctl[203]) &
  1552. ((1 << 21) | (1 << 12)))) {
  1553. udelay(1);
  1554. if (timeout <= 0) {
  1555. printf("%s: pctl timeout!\n", __func__);
  1556. return -ETIMEDOUT;
  1557. }
  1558. timeout--;
  1559. }
  1560. if (!(readl(&ddr_pctl_regs->denali_ctl[203]) & (1 << 12))) {
  1561. *buf = readl(&ddr_pctl_regs->denali_ctl[119]) & 0xFF;
  1562. } else {
  1563. printf("%s: read mr failed with 0x%x status\n", __func__,
  1564. readl(&ddr_pctl_regs->denali_ctl[17]) & 0x3);
  1565. *buf = 0;
  1566. }
  1567. setbits_le32(&ddr_pctl_regs->denali_ctl[205], (1 << 21) | (1 << 12));
  1568. return 0;
  1569. }
  1570. static int lpddr4_mr_detect(struct dram_info *dram, u32 channel, u8 rank,
  1571. struct rk3399_sdram_params *params)
  1572. {
  1573. u64 cs0_cap;
  1574. u32 stride;
  1575. u32 cs = 0, col = 0, bk = 0, bw = 0, row_3_4 = 0;
  1576. u32 cs0_row = 0, cs1_row = 0, ddrconfig = 0;
  1577. u32 mr5, mr12, mr14;
  1578. struct chan_info *chan = &dram->chan[channel];
  1579. struct rk3399_ddr_pctl_regs *ddr_pctl_regs = chan->pctl;
  1580. void __iomem *addr = NULL;
  1581. int ret = 0;
  1582. u32 val;
  1583. stride = get_ddr_stride(dram->pmusgrf);
  1584. if (params->ch[channel].cap_info.col == 0) {
  1585. ret = -EPERM;
  1586. goto end;
  1587. }
  1588. cs = params->ch[channel].cap_info.rank;
  1589. col = params->ch[channel].cap_info.col;
  1590. bk = params->ch[channel].cap_info.bk;
  1591. bw = params->ch[channel].cap_info.bw;
  1592. row_3_4 = params->ch[channel].cap_info.row_3_4;
  1593. cs0_row = params->ch[channel].cap_info.cs0_row;
  1594. cs1_row = params->ch[channel].cap_info.cs1_row;
  1595. ddrconfig = params->ch[channel].cap_info.ddrconfig;
  1596. /* 2GB */
  1597. params->ch[channel].cap_info.rank = 2;
  1598. params->ch[channel].cap_info.col = 10;
  1599. params->ch[channel].cap_info.bk = 3;
  1600. params->ch[channel].cap_info.bw = 2;
  1601. params->ch[channel].cap_info.row_3_4 = 0;
  1602. params->ch[channel].cap_info.cs0_row = 15;
  1603. params->ch[channel].cap_info.cs1_row = 15;
  1604. params->ch[channel].cap_info.ddrconfig = 1;
  1605. set_memory_map(chan, channel, params);
  1606. params->ch[channel].cap_info.ddrconfig =
  1607. calculate_ddrconfig(params, channel);
  1608. set_ddrconfig(chan, params, channel,
  1609. params->ch[channel].cap_info.ddrconfig);
  1610. set_cap_relate_config(chan, params, channel);
  1611. cs0_cap = (1 << (params->ch[channel].cap_info.bw
  1612. + params->ch[channel].cap_info.col
  1613. + params->ch[channel].cap_info.bk
  1614. + params->ch[channel].cap_info.cs0_row));
  1615. if (params->ch[channel].cap_info.row_3_4)
  1616. cs0_cap = cs0_cap * 3 / 4;
  1617. if (channel == 0)
  1618. set_ddr_stride(dram->pmusgrf, 0x17);
  1619. else
  1620. set_ddr_stride(dram->pmusgrf, 0x18);
  1621. /* read and write data to DRAM, avoid be optimized by compiler. */
  1622. if (rank == 1)
  1623. addr = (void __iomem *)0x100;
  1624. else if (rank == 2)
  1625. addr = (void __iomem *)(cs0_cap + 0x100);
  1626. val = readl(addr);
  1627. writel(val + 1, addr);
  1628. read_mr(ddr_pctl_regs, rank, 5, &mr5);
  1629. read_mr(ddr_pctl_regs, rank, 12, &mr12);
  1630. read_mr(ddr_pctl_regs, rank, 14, &mr14);
  1631. if (mr5 == 0 || mr12 != 0x4d || mr14 != 0x4d) {
  1632. ret = -EINVAL;
  1633. goto end;
  1634. }
  1635. end:
  1636. params->ch[channel].cap_info.rank = cs;
  1637. params->ch[channel].cap_info.col = col;
  1638. params->ch[channel].cap_info.bk = bk;
  1639. params->ch[channel].cap_info.bw = bw;
  1640. params->ch[channel].cap_info.row_3_4 = row_3_4;
  1641. params->ch[channel].cap_info.cs0_row = cs0_row;
  1642. params->ch[channel].cap_info.cs1_row = cs1_row;
  1643. params->ch[channel].cap_info.ddrconfig = ddrconfig;
  1644. set_ddr_stride(dram->pmusgrf, stride);
  1645. return ret;
  1646. }
  1647. static void set_lpddr4_dq_odt(const struct chan_info *chan,
  1648. struct rk3399_sdram_params *params, u32 ctl_fn,
  1649. bool en, bool ctl_phy_reg, u32 mr5)
  1650. {
  1651. u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
  1652. u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
  1653. struct io_setting *io;
  1654. u32 reg_value;
  1655. io = lpddr4_get_io_settings(params, mr5);
  1656. if (en)
  1657. reg_value = io->dq_odt;
  1658. else
  1659. reg_value = 0;
  1660. switch (ctl_fn) {
  1661. case 0:
  1662. clrsetbits_le32(&denali_ctl[139], 0x7 << 24, reg_value << 24);
  1663. clrsetbits_le32(&denali_ctl[153], 0x7 << 24, reg_value << 24);
  1664. clrsetbits_le32(&denali_pi[132], 0x7 << 0, (reg_value << 0));
  1665. clrsetbits_le32(&denali_pi[139], 0x7 << 16, (reg_value << 16));
  1666. clrsetbits_le32(&denali_pi[147], 0x7 << 0, (reg_value << 0));
  1667. clrsetbits_le32(&denali_pi[154], 0x7 << 16, (reg_value << 16));
  1668. break;
  1669. case 1:
  1670. clrsetbits_le32(&denali_ctl[140], 0x7 << 0, reg_value << 0);
  1671. clrsetbits_le32(&denali_ctl[154], 0x7 << 0, reg_value << 0);
  1672. clrsetbits_le32(&denali_pi[129], 0x7 << 16, (reg_value << 16));
  1673. clrsetbits_le32(&denali_pi[137], 0x7 << 0, (reg_value << 0));
  1674. clrsetbits_le32(&denali_pi[144], 0x7 << 16, (reg_value << 16));
  1675. clrsetbits_le32(&denali_pi[152], 0x7 << 0, (reg_value << 0));
  1676. break;
  1677. case 2:
  1678. default:
  1679. clrsetbits_le32(&denali_ctl[140], 0x7 << 8, (reg_value << 8));
  1680. clrsetbits_le32(&denali_ctl[154], 0x7 << 8, (reg_value << 8));
  1681. clrsetbits_le32(&denali_pi[127], 0x7 << 0, (reg_value << 0));
  1682. clrsetbits_le32(&denali_pi[134], 0x7 << 16, (reg_value << 16));
  1683. clrsetbits_le32(&denali_pi[142], 0x7 << 0, (reg_value << 0));
  1684. clrsetbits_le32(&denali_pi[149], 0x7 << 16, (reg_value << 16));
  1685. break;
  1686. }
  1687. }
  1688. static void set_lpddr4_ca_odt(const struct chan_info *chan,
  1689. struct rk3399_sdram_params *params, u32 ctl_fn,
  1690. bool en, bool ctl_phy_reg, u32 mr5)
  1691. {
  1692. u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
  1693. u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
  1694. struct io_setting *io;
  1695. u32 reg_value;
  1696. io = lpddr4_get_io_settings(params, mr5);
  1697. if (en)
  1698. reg_value = io->ca_odt;
  1699. else
  1700. reg_value = 0;
  1701. switch (ctl_fn) {
  1702. case 0:
  1703. clrsetbits_le32(&denali_ctl[139], 0x7 << 28, reg_value << 28);
  1704. clrsetbits_le32(&denali_ctl[153], 0x7 << 28, reg_value << 28);
  1705. clrsetbits_le32(&denali_pi[132], 0x7 << 4, reg_value << 4);
  1706. clrsetbits_le32(&denali_pi[139], 0x7 << 20, reg_value << 20);
  1707. clrsetbits_le32(&denali_pi[147], 0x7 << 4, reg_value << 4);
  1708. clrsetbits_le32(&denali_pi[154], 0x7 << 20, reg_value << 20);
  1709. break;
  1710. case 1:
  1711. clrsetbits_le32(&denali_ctl[140], 0x7 << 4, reg_value << 4);
  1712. clrsetbits_le32(&denali_ctl[154], 0x7 << 4, reg_value << 4);
  1713. clrsetbits_le32(&denali_pi[129], 0x7 << 20, reg_value << 20);
  1714. clrsetbits_le32(&denali_pi[137], 0x7 << 4, reg_value << 4);
  1715. clrsetbits_le32(&denali_pi[144], 0x7 << 20, reg_value << 20);
  1716. clrsetbits_le32(&denali_pi[152], 0x7 << 4, reg_value << 4);
  1717. break;
  1718. case 2:
  1719. default:
  1720. clrsetbits_le32(&denali_ctl[140], 0x7 << 12, (reg_value << 12));
  1721. clrsetbits_le32(&denali_ctl[154], 0x7 << 12, (reg_value << 12));
  1722. clrsetbits_le32(&denali_pi[127], 0x7 << 4, reg_value << 4);
  1723. clrsetbits_le32(&denali_pi[134], 0x7 << 20, reg_value << 20);
  1724. clrsetbits_le32(&denali_pi[142], 0x7 << 4, reg_value << 4);
  1725. clrsetbits_le32(&denali_pi[149], 0x7 << 20, reg_value << 20);
  1726. break;
  1727. }
  1728. }
  1729. static void set_lpddr4_MR3(const struct chan_info *chan,
  1730. struct rk3399_sdram_params *params, u32 ctl_fn,
  1731. bool ctl_phy_reg, u32 mr5)
  1732. {
  1733. u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
  1734. u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
  1735. struct io_setting *io;
  1736. u32 reg_value;
  1737. io = lpddr4_get_io_settings(params, mr5);
  1738. reg_value = ((io->pdds << 3) | 1);
  1739. switch (ctl_fn) {
  1740. case 0:
  1741. clrsetbits_le32(&denali_ctl[138], 0xFFFF, reg_value);
  1742. clrsetbits_le32(&denali_ctl[152], 0xFFFF, reg_value);
  1743. clrsetbits_le32(&denali_pi[131], 0xFFFF << 16, reg_value << 16);
  1744. clrsetbits_le32(&denali_pi[139], 0xFFFF, reg_value);
  1745. clrsetbits_le32(&denali_pi[146], 0xFFFF << 16, reg_value << 16);
  1746. clrsetbits_le32(&denali_pi[154], 0xFFFF, reg_value);
  1747. break;
  1748. case 1:
  1749. clrsetbits_le32(&denali_ctl[138], 0xFFFF << 16,
  1750. reg_value << 16);
  1751. clrsetbits_le32(&denali_ctl[152], 0xFFFF << 16,
  1752. reg_value << 16);
  1753. clrsetbits_le32(&denali_pi[129], 0xFFFF, reg_value);
  1754. clrsetbits_le32(&denali_pi[136], 0xFFFF << 16, reg_value << 16);
  1755. clrsetbits_le32(&denali_pi[144], 0xFFFF, reg_value);
  1756. clrsetbits_le32(&denali_pi[151], 0xFFFF << 16, reg_value << 16);
  1757. break;
  1758. case 2:
  1759. default:
  1760. clrsetbits_le32(&denali_ctl[139], 0xFFFF, reg_value);
  1761. clrsetbits_le32(&denali_ctl[153], 0xFFFF, reg_value);
  1762. clrsetbits_le32(&denali_pi[126], 0xFFFF << 16, reg_value << 16);
  1763. clrsetbits_le32(&denali_pi[134], 0xFFFF, reg_value);
  1764. clrsetbits_le32(&denali_pi[141], 0xFFFF << 16, reg_value << 16);
  1765. clrsetbits_le32(&denali_pi[149], 0xFFFF, reg_value);
  1766. break;
  1767. }
  1768. }
  1769. static void set_lpddr4_MR12(const struct chan_info *chan,
  1770. struct rk3399_sdram_params *params, u32 ctl_fn,
  1771. bool ctl_phy_reg, u32 mr5)
  1772. {
  1773. u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
  1774. u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
  1775. struct io_setting *io;
  1776. u32 reg_value;
  1777. io = lpddr4_get_io_settings(params, mr5);
  1778. reg_value = io->ca_vref;
  1779. switch (ctl_fn) {
  1780. case 0:
  1781. clrsetbits_le32(&denali_ctl[140], 0xFFFF << 16,
  1782. reg_value << 16);
  1783. clrsetbits_le32(&denali_ctl[154], 0xFFFF << 16,
  1784. reg_value << 16);
  1785. clrsetbits_le32(&denali_pi[132], 0xFF << 8, reg_value << 8);
  1786. clrsetbits_le32(&denali_pi[139], 0xFF << 24, reg_value << 24);
  1787. clrsetbits_le32(&denali_pi[147], 0xFF << 8, reg_value << 8);
  1788. clrsetbits_le32(&denali_pi[154], 0xFF << 24, reg_value << 24);
  1789. break;
  1790. case 1:
  1791. clrsetbits_le32(&denali_ctl[141], 0xFFFF, reg_value);
  1792. clrsetbits_le32(&denali_ctl[155], 0xFFFF, reg_value);
  1793. clrsetbits_le32(&denali_pi[129], 0xFF << 24, reg_value << 24);
  1794. clrsetbits_le32(&denali_pi[137], 0xFF << 8, reg_value << 8);
  1795. clrsetbits_le32(&denali_pi[144], 0xFF << 24, reg_value << 24);
  1796. clrsetbits_le32(&denali_pi[152], 0xFF << 8, reg_value << 8);
  1797. break;
  1798. case 2:
  1799. default:
  1800. clrsetbits_le32(&denali_ctl[141], 0xFFFF << 16,
  1801. reg_value << 16);
  1802. clrsetbits_le32(&denali_ctl[155], 0xFFFF << 16,
  1803. reg_value << 16);
  1804. clrsetbits_le32(&denali_pi[127], 0xFF << 8, reg_value << 8);
  1805. clrsetbits_le32(&denali_pi[134], 0xFF << 24, reg_value << 24);
  1806. clrsetbits_le32(&denali_pi[142], 0xFF << 8, reg_value << 8);
  1807. clrsetbits_le32(&denali_pi[149], 0xFF << 24, reg_value << 24);
  1808. break;
  1809. }
  1810. }
  1811. static void set_lpddr4_MR14(const struct chan_info *chan,
  1812. struct rk3399_sdram_params *params, u32 ctl_fn,
  1813. bool ctl_phy_reg, u32 mr5)
  1814. {
  1815. u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
  1816. u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
  1817. struct io_setting *io;
  1818. u32 reg_value;
  1819. io = lpddr4_get_io_settings(params, mr5);
  1820. reg_value = io->dq_vref;
  1821. switch (ctl_fn) {
  1822. case 0:
  1823. clrsetbits_le32(&denali_ctl[142], 0xFFFF << 16,
  1824. reg_value << 16);
  1825. clrsetbits_le32(&denali_ctl[156], 0xFFFF << 16,
  1826. reg_value << 16);
  1827. clrsetbits_le32(&denali_pi[132], 0xFF << 16, reg_value << 16);
  1828. clrsetbits_le32(&denali_pi[140], 0xFF << 0, reg_value << 0);
  1829. clrsetbits_le32(&denali_pi[147], 0xFF << 16, reg_value << 16);
  1830. clrsetbits_le32(&denali_pi[155], 0xFF << 0, reg_value << 0);
  1831. break;
  1832. case 1:
  1833. clrsetbits_le32(&denali_ctl[143], 0xFFFF, reg_value);
  1834. clrsetbits_le32(&denali_ctl[157], 0xFFFF, reg_value);
  1835. clrsetbits_le32(&denali_pi[130], 0xFF << 0, reg_value << 0);
  1836. clrsetbits_le32(&denali_pi[137], 0xFF << 16, reg_value << 16);
  1837. clrsetbits_le32(&denali_pi[145], 0xFF << 0, reg_value << 0);
  1838. clrsetbits_le32(&denali_pi[152], 0xFF << 16, reg_value << 16);
  1839. break;
  1840. case 2:
  1841. default:
  1842. clrsetbits_le32(&denali_ctl[143], 0xFFFF << 16,
  1843. reg_value << 16);
  1844. clrsetbits_le32(&denali_ctl[157], 0xFFFF << 16,
  1845. reg_value << 16);
  1846. clrsetbits_le32(&denali_pi[127], 0xFF << 16, reg_value << 16);
  1847. clrsetbits_le32(&denali_pi[135], 0xFF << 0, reg_value << 0);
  1848. clrsetbits_le32(&denali_pi[142], 0xFF << 16, reg_value << 16);
  1849. clrsetbits_le32(&denali_pi[150], 0xFF << 0, reg_value << 0);
  1850. break;
  1851. }
  1852. }
  1853. void lpddr4_modify_param(const struct chan_info *chan,
  1854. struct rk3399_sdram_params *params)
  1855. {
  1856. struct rk3399_sdram_params *params_cfg;
  1857. u32 *denali_ctl_params;
  1858. u32 *denali_pi_params;
  1859. u32 *denali_phy_params;
  1860. denali_ctl_params = params->pctl_regs.denali_ctl;
  1861. denali_pi_params = params->pi_regs.denali_pi;
  1862. denali_phy_params = params->phy_regs.denali_phy;
  1863. set_lpddr4_dq_odt(chan, params, 2, true, false, 0);
  1864. set_lpddr4_ca_odt(chan, params, 2, true, false, 0);
  1865. set_lpddr4_MR3(chan, params, 2, false, 0);
  1866. set_lpddr4_MR12(chan, params, 2, false, 0);
  1867. set_lpddr4_MR14(chan, params, 2, false, 0);
  1868. params_cfg = lpddr4_get_phy_index_params(0, params);
  1869. set_ds_odt(chan, params_cfg, false, 0);
  1870. /* read two cycle preamble */
  1871. clrsetbits_le32(&denali_ctl_params[200], 0x3 << 24, 0x3 << 24);
  1872. clrsetbits_le32(&denali_phy_params[7], 0x3 << 24, 0x3 << 24);
  1873. clrsetbits_le32(&denali_phy_params[135], 0x3 << 24, 0x3 << 24);
  1874. clrsetbits_le32(&denali_phy_params[263], 0x3 << 24, 0x3 << 24);
  1875. clrsetbits_le32(&denali_phy_params[391], 0x3 << 24, 0x3 << 24);
  1876. /* boot frequency two cycle preamble */
  1877. clrsetbits_le32(&denali_phy_params[2], 0x3 << 16, 0x3 << 16);
  1878. clrsetbits_le32(&denali_phy_params[130], 0x3 << 16, 0x3 << 16);
  1879. clrsetbits_le32(&denali_phy_params[258], 0x3 << 16, 0x3 << 16);
  1880. clrsetbits_le32(&denali_phy_params[386], 0x3 << 16, 0x3 << 16);
  1881. clrsetbits_le32(&denali_pi_params[45], 0x3 << 8, 0x3 << 8);
  1882. clrsetbits_le32(&denali_pi_params[58], 0x1, 0x1);
  1883. /*
  1884. * bypass mode need PHY_SLICE_PWR_RDC_DISABLE_x = 1,
  1885. * boot frequency mode use bypass mode
  1886. */
  1887. setbits_le32(&denali_phy_params[10], 1 << 16);
  1888. setbits_le32(&denali_phy_params[138], 1 << 16);
  1889. setbits_le32(&denali_phy_params[266], 1 << 16);
  1890. setbits_le32(&denali_phy_params[394], 1 << 16);
  1891. clrsetbits_le32(&denali_pi_params[45], 0x1 << 24, 0x1 << 24);
  1892. clrsetbits_le32(&denali_pi_params[61], 0x1 << 24, 0x1 << 24);
  1893. clrsetbits_le32(&denali_pi_params[76], 0x1 << 24, 0x1 << 24);
  1894. clrsetbits_le32(&denali_pi_params[77], 0x1, 0x1);
  1895. }
  1896. static void lpddr4_copy_phy(struct dram_info *dram,
  1897. struct rk3399_sdram_params *params, u32 phy_fn,
  1898. struct rk3399_sdram_params *params_cfg,
  1899. u32 channel)
  1900. {
  1901. u32 *denali_ctl, *denali_phy;
  1902. u32 *denali_phy_params;
  1903. u32 speed = 0;
  1904. u32 ctl_fn, mr5;
  1905. denali_ctl = dram->chan[channel].pctl->denali_ctl;
  1906. denali_phy = dram->chan[channel].publ->denali_phy;
  1907. denali_phy_params = params_cfg->phy_regs.denali_phy;
  1908. /* switch index */
  1909. clrsetbits_le32(&denali_phy_params[896], 0x3 << 8,
  1910. phy_fn << 8);
  1911. writel(denali_phy_params[896], &denali_phy[896]);
  1912. /* phy_pll_ctrl_ca, phy_pll_ctrl */
  1913. writel(denali_phy_params[911], &denali_phy[911]);
  1914. /* phy_low_freq_sel */
  1915. clrsetbits_le32(&denali_phy[913], 0x1,
  1916. denali_phy_params[913] & 0x1);
  1917. /* phy_grp_slave_delay_x, phy_cslvl_dly_step */
  1918. writel(denali_phy_params[916], &denali_phy[916]);
  1919. writel(denali_phy_params[917], &denali_phy[917]);
  1920. writel(denali_phy_params[918], &denali_phy[918]);
  1921. /* phy_adrz_sw_wraddr_shift_x */
  1922. writel(denali_phy_params[512], &denali_phy[512]);
  1923. clrsetbits_le32(&denali_phy[513], 0xffff,
  1924. denali_phy_params[513] & 0xffff);
  1925. writel(denali_phy_params[640], &denali_phy[640]);
  1926. clrsetbits_le32(&denali_phy[641], 0xffff,
  1927. denali_phy_params[641] & 0xffff);
  1928. writel(denali_phy_params[768], &denali_phy[768]);
  1929. clrsetbits_le32(&denali_phy[769], 0xffff,
  1930. denali_phy_params[769] & 0xffff);
  1931. writel(denali_phy_params[544], &denali_phy[544]);
  1932. writel(denali_phy_params[545], &denali_phy[545]);
  1933. writel(denali_phy_params[546], &denali_phy[546]);
  1934. writel(denali_phy_params[547], &denali_phy[547]);
  1935. writel(denali_phy_params[672], &denali_phy[672]);
  1936. writel(denali_phy_params[673], &denali_phy[673]);
  1937. writel(denali_phy_params[674], &denali_phy[674]);
  1938. writel(denali_phy_params[675], &denali_phy[675]);
  1939. writel(denali_phy_params[800], &denali_phy[800]);
  1940. writel(denali_phy_params[801], &denali_phy[801]);
  1941. writel(denali_phy_params[802], &denali_phy[802]);
  1942. writel(denali_phy_params[803], &denali_phy[803]);
  1943. /*
  1944. * phy_adr_master_delay_start_x
  1945. * phy_adr_master_delay_step_x
  1946. * phy_adr_master_delay_wait_x
  1947. */
  1948. writel(denali_phy_params[548], &denali_phy[548]);
  1949. writel(denali_phy_params[676], &denali_phy[676]);
  1950. writel(denali_phy_params[804], &denali_phy[804]);
  1951. /* phy_adr_calvl_dly_step_x */
  1952. writel(denali_phy_params[549], &denali_phy[549]);
  1953. writel(denali_phy_params[677], &denali_phy[677]);
  1954. writel(denali_phy_params[805], &denali_phy[805]);
  1955. /*
  1956. * phy_clk_wrdm_slave_delay_x
  1957. * phy_clk_wrdqz_slave_delay_x
  1958. * phy_clk_wrdqs_slave_delay_x
  1959. */
  1960. sdram_copy_to_reg((u32 *)&denali_phy[59],
  1961. (u32 *)&denali_phy_params[59], (63 - 58) * 4);
  1962. sdram_copy_to_reg((u32 *)&denali_phy[187],
  1963. (u32 *)&denali_phy_params[187], (191 - 186) * 4);
  1964. sdram_copy_to_reg((u32 *)&denali_phy[315],
  1965. (u32 *)&denali_phy_params[315], (319 - 314) * 4);
  1966. sdram_copy_to_reg((u32 *)&denali_phy[443],
  1967. (u32 *)&denali_phy_params[443], (447 - 442) * 4);
  1968. /*
  1969. * phy_dqs_tsel_wr_timing_x 8bits denali_phy_84/212/340/468 offset_8
  1970. * dqs_tsel_wr_end[7:4] add half cycle
  1971. * phy_dq_tsel_wr_timing_x 8bits denali_phy_83/211/339/467 offset_8
  1972. * dq_tsel_wr_end[7:4] add half cycle
  1973. */
  1974. writel(denali_phy_params[83] + (0x10 << 16), &denali_phy[83]);
  1975. writel(denali_phy_params[84] + (0x10 << 8), &denali_phy[84]);
  1976. writel(denali_phy_params[85], &denali_phy[85]);
  1977. writel(denali_phy_params[211] + (0x10 << 16), &denali_phy[211]);
  1978. writel(denali_phy_params[212] + (0x10 << 8), &denali_phy[212]);
  1979. writel(denali_phy_params[213], &denali_phy[213]);
  1980. writel(denali_phy_params[339] + (0x10 << 16), &denali_phy[339]);
  1981. writel(denali_phy_params[340] + (0x10 << 8), &denali_phy[340]);
  1982. writel(denali_phy_params[341], &denali_phy[341]);
  1983. writel(denali_phy_params[467] + (0x10 << 16), &denali_phy[467]);
  1984. writel(denali_phy_params[468] + (0x10 << 8), &denali_phy[468]);
  1985. writel(denali_phy_params[469], &denali_phy[469]);
  1986. /*
  1987. * phy_gtlvl_resp_wait_cnt_x
  1988. * phy_gtlvl_dly_step_x
  1989. * phy_wrlvl_resp_wait_cnt_x
  1990. * phy_gtlvl_final_step_x
  1991. * phy_gtlvl_back_step_x
  1992. * phy_rdlvl_dly_step_x
  1993. *
  1994. * phy_master_delay_step_x
  1995. * phy_master_delay_wait_x
  1996. * phy_wrlvl_dly_step_x
  1997. * phy_rptr_update_x
  1998. * phy_wdqlvl_dly_step_x
  1999. */
  2000. writel(denali_phy_params[87], &denali_phy[87]);
  2001. writel(denali_phy_params[88], &denali_phy[88]);
  2002. writel(denali_phy_params[89], &denali_phy[89]);
  2003. writel(denali_phy_params[90], &denali_phy[90]);
  2004. writel(denali_phy_params[215], &denali_phy[215]);
  2005. writel(denali_phy_params[216], &denali_phy[216]);
  2006. writel(denali_phy_params[217], &denali_phy[217]);
  2007. writel(denali_phy_params[218], &denali_phy[218]);
  2008. writel(denali_phy_params[343], &denali_phy[343]);
  2009. writel(denali_phy_params[344], &denali_phy[344]);
  2010. writel(denali_phy_params[345], &denali_phy[345]);
  2011. writel(denali_phy_params[346], &denali_phy[346]);
  2012. writel(denali_phy_params[471], &denali_phy[471]);
  2013. writel(denali_phy_params[472], &denali_phy[472]);
  2014. writel(denali_phy_params[473], &denali_phy[473]);
  2015. writel(denali_phy_params[474], &denali_phy[474]);
  2016. /*
  2017. * phy_gtlvl_lat_adj_start_x
  2018. * phy_gtlvl_rddqs_slv_dly_start_x
  2019. * phy_rdlvl_rddqs_dq_slv_dly_start_x
  2020. * phy_wdqlvl_dqdm_slv_dly_start_x
  2021. */
  2022. writel(denali_phy_params[80], &denali_phy[80]);
  2023. writel(denali_phy_params[81], &denali_phy[81]);
  2024. writel(denali_phy_params[208], &denali_phy[208]);
  2025. writel(denali_phy_params[209], &denali_phy[209]);
  2026. writel(denali_phy_params[336], &denali_phy[336]);
  2027. writel(denali_phy_params[337], &denali_phy[337]);
  2028. writel(denali_phy_params[464], &denali_phy[464]);
  2029. writel(denali_phy_params[465], &denali_phy[465]);
  2030. /*
  2031. * phy_master_delay_start_x
  2032. * phy_sw_master_mode_x
  2033. * phy_rddata_en_tsel_dly_x
  2034. */
  2035. writel(denali_phy_params[86], &denali_phy[86]);
  2036. writel(denali_phy_params[214], &denali_phy[214]);
  2037. writel(denali_phy_params[342], &denali_phy[342]);
  2038. writel(denali_phy_params[470], &denali_phy[470]);
  2039. /*
  2040. * phy_rddqz_slave_delay_x
  2041. * phy_rddqs_dqz_fall_slave_delay_x
  2042. * phy_rddqs_dqz_rise_slave_delay_x
  2043. * phy_rddqs_dm_fall_slave_delay_x
  2044. * phy_rddqs_dm_rise_slave_delay_x
  2045. * phy_rddqs_gate_slave_delay_x
  2046. * phy_wrlvl_delay_early_threshold_x
  2047. * phy_write_path_lat_add_x
  2048. * phy_rddqs_latency_adjust_x
  2049. * phy_wrlvl_delay_period_threshold_x
  2050. * phy_wrlvl_early_force_zero_x
  2051. */
  2052. sdram_copy_to_reg((u32 *)&denali_phy[64],
  2053. (u32 *)&denali_phy_params[64], (67 - 63) * 4);
  2054. clrsetbits_le32(&denali_phy[68], 0xfffffc00,
  2055. denali_phy_params[68] & 0xfffffc00);
  2056. sdram_copy_to_reg((u32 *)&denali_phy[69],
  2057. (u32 *)&denali_phy_params[69], (79 - 68) * 4);
  2058. sdram_copy_to_reg((u32 *)&denali_phy[192],
  2059. (u32 *)&denali_phy_params[192], (195 - 191) * 4);
  2060. clrsetbits_le32(&denali_phy[196], 0xfffffc00,
  2061. denali_phy_params[196] & 0xfffffc00);
  2062. sdram_copy_to_reg((u32 *)&denali_phy[197],
  2063. (u32 *)&denali_phy_params[197], (207 - 196) * 4);
  2064. sdram_copy_to_reg((u32 *)&denali_phy[320],
  2065. (u32 *)&denali_phy_params[320], (323 - 319) * 4);
  2066. clrsetbits_le32(&denali_phy[324], 0xfffffc00,
  2067. denali_phy_params[324] & 0xfffffc00);
  2068. sdram_copy_to_reg((u32 *)&denali_phy[325],
  2069. (u32 *)&denali_phy_params[325], (335 - 324) * 4);
  2070. sdram_copy_to_reg((u32 *)&denali_phy[448],
  2071. (u32 *)&denali_phy_params[448], (451 - 447) * 4);
  2072. clrsetbits_le32(&denali_phy[452], 0xfffffc00,
  2073. denali_phy_params[452] & 0xfffffc00);
  2074. sdram_copy_to_reg((u32 *)&denali_phy[453],
  2075. (u32 *)&denali_phy_params[453], (463 - 452) * 4);
  2076. /* phy_two_cyc_preamble_x */
  2077. clrsetbits_le32(&denali_phy[7], 0x3 << 24,
  2078. denali_phy_params[7] & (0x3 << 24));
  2079. clrsetbits_le32(&denali_phy[135], 0x3 << 24,
  2080. denali_phy_params[135] & (0x3 << 24));
  2081. clrsetbits_le32(&denali_phy[263], 0x3 << 24,
  2082. denali_phy_params[263] & (0x3 << 24));
  2083. clrsetbits_le32(&denali_phy[391], 0x3 << 24,
  2084. denali_phy_params[391] & (0x3 << 24));
  2085. /* speed */
  2086. if (params_cfg->base.ddr_freq < 400)
  2087. speed = 0x0;
  2088. else if (params_cfg->base.ddr_freq < 800)
  2089. speed = 0x1;
  2090. else if (params_cfg->base.ddr_freq < 1200)
  2091. speed = 0x2;
  2092. /* phy_924 phy_pad_fdbk_drive */
  2093. clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
  2094. /* phy_926 phy_pad_data_drive */
  2095. clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
  2096. /* phy_927 phy_pad_dqs_drive */
  2097. clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
  2098. /* phy_928 phy_pad_addr_drive */
  2099. clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
  2100. /* phy_929 phy_pad_clk_drive */
  2101. clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
  2102. /* phy_935 phy_pad_cke_drive */
  2103. clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
  2104. /* phy_937 phy_pad_rst_drive */
  2105. clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
  2106. /* phy_939 phy_pad_cs_drive */
  2107. clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
  2108. if (params_cfg->base.dramtype == LPDDR4) {
  2109. read_mr(dram->chan[channel].pctl, 1, 5, &mr5);
  2110. set_ds_odt(&dram->chan[channel], params_cfg, true, mr5);
  2111. ctl_fn = lpddr4_get_ctl_fn(params_cfg, phy_fn);
  2112. set_lpddr4_dq_odt(&dram->chan[channel], params_cfg,
  2113. ctl_fn, true, true, mr5);
  2114. set_lpddr4_ca_odt(&dram->chan[channel], params_cfg,
  2115. ctl_fn, true, true, mr5);
  2116. set_lpddr4_MR3(&dram->chan[channel], params_cfg,
  2117. ctl_fn, true, mr5);
  2118. set_lpddr4_MR12(&dram->chan[channel], params_cfg,
  2119. ctl_fn, true, mr5);
  2120. set_lpddr4_MR14(&dram->chan[channel], params_cfg,
  2121. ctl_fn, true, mr5);
  2122. /*
  2123. * if phy_sw_master_mode_x not bypass mode,
  2124. * clear phy_slice_pwr_rdc_disable.
  2125. * note: need use timings, not ddr_publ_regs
  2126. */
  2127. if (!((denali_phy_params[86] >> 8) & (1 << 2))) {
  2128. clrbits_le32(&denali_phy[10], 1 << 16);
  2129. clrbits_le32(&denali_phy[138], 1 << 16);
  2130. clrbits_le32(&denali_phy[266], 1 << 16);
  2131. clrbits_le32(&denali_phy[394], 1 << 16);
  2132. }
  2133. /*
  2134. * when PHY_PER_CS_TRAINING_EN=1, W2W_DIFFCS_DLY_Fx can't
  2135. * smaller than 8
  2136. * NOTE: need use timings, not ddr_publ_regs
  2137. */
  2138. if ((denali_phy_params[84] >> 16) & 1) {
  2139. if (((readl(&denali_ctl[217 + ctl_fn]) >>
  2140. 16) & 0x1f) < 8)
  2141. clrsetbits_le32(&denali_ctl[217 + ctl_fn],
  2142. 0x1f << 16,
  2143. 8 << 16);
  2144. }
  2145. }
  2146. }
  2147. static void lpddr4_set_phy(struct dram_info *dram,
  2148. struct rk3399_sdram_params *params, u32 phy_fn,
  2149. struct rk3399_sdram_params *params_cfg)
  2150. {
  2151. u32 channel;
  2152. for (channel = 0; channel < 2; channel++)
  2153. lpddr4_copy_phy(dram, params, phy_fn, params_cfg,
  2154. channel);
  2155. }
  2156. static int lpddr4_set_ctl(struct dram_info *dram,
  2157. struct rk3399_sdram_params *params,
  2158. u32 fn, u32 hz)
  2159. {
  2160. u32 channel;
  2161. int ret_clk, ret;
  2162. /* cci idle req stall */
  2163. writel(0x70007, &dram->grf->soc_con0);
  2164. /* enable all clk */
  2165. setbits_le32(&dram->pmu->pmu_noc_auto_ena, (0x3 << 7));
  2166. /* idle */
  2167. setbits_le32(&dram->pmu->pmu_bus_idle_req, (0x3 << 18));
  2168. while ((readl(&dram->pmu->pmu_bus_idle_st) & (0x3 << 18))
  2169. != (0x3 << 18))
  2170. ;
  2171. /* change freq */
  2172. writel((((0x3 << 4) | (1 << 2) | 1) << 16) |
  2173. (fn << 4) | (1 << 2) | 1, &dram->cic->cic_ctrl0);
  2174. while (!(readl(&dram->cic->cic_status0) & (1 << 2)))
  2175. ;
  2176. ret_clk = clk_set_rate(&dram->ddr_clk, hz);
  2177. if (ret_clk < 0) {
  2178. printf("%s clk set failed %d\n", __func__, ret_clk);
  2179. return ret_clk;
  2180. }
  2181. writel(0x20002, &dram->cic->cic_ctrl0);
  2182. while (!(readl(&dram->cic->cic_status0) & (1 << 0)))
  2183. ;
  2184. /* deidle */
  2185. clrbits_le32(&dram->pmu->pmu_bus_idle_req, (0x3 << 18));
  2186. while (readl(&dram->pmu->pmu_bus_idle_st) & (0x3 << 18))
  2187. ;
  2188. /* clear enable all clk */
  2189. clrbits_le32(&dram->pmu->pmu_noc_auto_ena, (0x3 << 7));
  2190. /* lpddr4 ctl2 can not do training, all training will fail */
  2191. if (!(params->base.dramtype == LPDDR4 && fn == 2)) {
  2192. for (channel = 0; channel < 2; channel++) {
  2193. if (!(params->ch[channel].cap_info.col))
  2194. continue;
  2195. ret = data_training(dram, channel, params,
  2196. PI_FULL_TRAINING);
  2197. if (ret)
  2198. printf("%s: channel %d training failed!\n",
  2199. __func__, channel);
  2200. else
  2201. debug("%s: channel %d training pass\n",
  2202. __func__, channel);
  2203. }
  2204. }
  2205. return 0;
  2206. }
  2207. static int lpddr4_set_rate(struct dram_info *dram,
  2208. struct rk3399_sdram_params *params)
  2209. {
  2210. u32 ctl_fn;
  2211. u32 phy_fn;
  2212. for (ctl_fn = 0; ctl_fn < 2; ctl_fn++) {
  2213. phy_fn = lpddr4_get_phy_fn(params, ctl_fn);
  2214. lpddr4_set_phy(dram, params, phy_fn, &dfs_cfgs_lpddr4[ctl_fn]);
  2215. lpddr4_set_ctl(dram, params, ctl_fn,
  2216. dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq);
  2217. printf("%s: change freq to %d mhz %d, %d\n", __func__,
  2218. dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq, ctl_fn, phy_fn);
  2219. }
  2220. return 0;
  2221. }
  2222. #endif /* CONFIG_RAM_RK3399_LPDDR4 */
  2223. /* CS0,n=1
  2224. * CS1,n=2
  2225. * CS0 & CS1, n=3
  2226. * cs0_cap: MB unit
  2227. */
  2228. static void dram_set_cs(const struct chan_info *chan, u32 cs_map, u32 cs0_cap,
  2229. unsigned char dramtype)
  2230. {
  2231. u32 *denali_ctl = chan->pctl->denali_ctl;
  2232. u32 *denali_pi = chan->pi->denali_pi;
  2233. struct msch_regs *ddr_msch_regs = chan->msch;
  2234. clrsetbits_le32(&denali_ctl[196], 0x3, cs_map);
  2235. writel((cs0_cap / 32) | (((4096 - cs0_cap) / 32) << 8),
  2236. &ddr_msch_regs->ddrsize);
  2237. if (dramtype == LPDDR4) {
  2238. if (cs_map == 1)
  2239. cs_map = 0x5;
  2240. else if (cs_map == 2)
  2241. cs_map = 0xa;
  2242. else
  2243. cs_map = 0xF;
  2244. }
  2245. /*PI_41 PI_CS_MAP:RW:24:4*/
  2246. clrsetbits_le32(&denali_pi[41],
  2247. 0xf << 24, cs_map << 24);
  2248. if (cs_map == 1 && dramtype == DDR3)
  2249. writel(0x2EC7FFFF, &denali_pi[34]);
  2250. }
  2251. static void dram_set_bw(const struct chan_info *chan, u32 bw)
  2252. {
  2253. u32 *denali_ctl = chan->pctl->denali_ctl;
  2254. if (bw == 2)
  2255. clrbits_le32(&denali_ctl[196], 1 << 16);
  2256. else
  2257. setbits_le32(&denali_ctl[196], 1 << 16);
  2258. }
  2259. static void dram_set_max_col(const struct chan_info *chan, u32 bw, u32 *pcol)
  2260. {
  2261. u32 *denali_ctl = chan->pctl->denali_ctl;
  2262. struct msch_regs *ddr_msch_regs = chan->msch;
  2263. u32 *denali_pi = chan->pi->denali_pi;
  2264. u32 ddrconfig;
  2265. clrbits_le32(&denali_ctl[191], 0xf);
  2266. clrsetbits_le32(&denali_ctl[190],
  2267. (7 << 24),
  2268. ((16 - ((bw == 2) ? 14 : 15)) << 24));
  2269. /*PI_199 PI_COL_DIFF:RW:0:4*/
  2270. clrbits_le32(&denali_pi[199], 0xf);
  2271. /*PI_155 PI_ROW_DIFF:RW:24:3*/
  2272. clrsetbits_le32(&denali_pi[155],
  2273. (7 << 24),
  2274. ((16 - 12) << 24));
  2275. ddrconfig = (bw == 2) ? 3 : 2;
  2276. writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf);
  2277. /* set max cs0 size */
  2278. writel((4096 / 32) | ((0 / 32) << 8),
  2279. &ddr_msch_regs->ddrsize);
  2280. *pcol = 12;
  2281. }
  2282. static void dram_set_max_bank(const struct chan_info *chan, u32 bw, u32 *pbank,
  2283. u32 *pcol)
  2284. {
  2285. u32 *denali_ctl = chan->pctl->denali_ctl;
  2286. u32 *denali_pi = chan->pi->denali_pi;
  2287. clrbits_le32(&denali_ctl[191], 0xf);
  2288. clrbits_le32(&denali_ctl[190], (3 << 16));
  2289. /*PI_199 PI_COL_DIFF:RW:0:4*/
  2290. clrbits_le32(&denali_pi[199], 0xf);
  2291. /*PI_155 PI_BANK_DIFF:RW:16:2*/
  2292. clrbits_le32(&denali_pi[155], (3 << 16));
  2293. *pbank = 3;
  2294. *pcol = 12;
  2295. }
  2296. static void dram_set_max_row(const struct chan_info *chan, u32 bw, u32 *prow,
  2297. u32 *pbank, u32 *pcol)
  2298. {
  2299. u32 *denali_ctl = chan->pctl->denali_ctl;
  2300. u32 *denali_pi = chan->pi->denali_pi;
  2301. struct msch_regs *ddr_msch_regs = chan->msch;
  2302. clrsetbits_le32(&denali_ctl[191], 0xf, 12 - 10);
  2303. clrbits_le32(&denali_ctl[190],
  2304. (0x3 << 16) | (0x7 << 24));
  2305. /*PI_199 PI_COL_DIFF:RW:0:4*/
  2306. clrsetbits_le32(&denali_pi[199], 0xf, 12 - 10);
  2307. /*PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2*/
  2308. clrbits_le32(&denali_pi[155],
  2309. (0x3 << 16) | (0x7 << 24));
  2310. writel(1 | (1 << 8), &ddr_msch_regs->ddrconf);
  2311. /* set max cs0 size */
  2312. writel((4096 / 32) | ((0 / 32) << 8),
  2313. &ddr_msch_regs->ddrsize);
  2314. *prow = 16;
  2315. *pbank = 3;
  2316. *pcol = (bw == 2) ? 10 : 11;
  2317. }
  2318. static u64 dram_detect_cap(struct dram_info *dram,
  2319. struct rk3399_sdram_params *params,
  2320. unsigned char channel)
  2321. {
  2322. const struct chan_info *chan = &dram->chan[channel];
  2323. struct sdram_cap_info *cap_info = &params->ch[channel].cap_info;
  2324. u32 bw;
  2325. u32 col_tmp;
  2326. u32 bk_tmp;
  2327. u32 row_tmp;
  2328. u32 cs0_cap;
  2329. u32 training_flag;
  2330. u32 ddrconfig;
  2331. /* detect bw */
  2332. bw = 2;
  2333. if (params->base.dramtype != LPDDR4) {
  2334. dram_set_bw(chan, bw);
  2335. cap_info->bw = bw;
  2336. if (data_training(dram, channel, params,
  2337. PI_READ_GATE_TRAINING)) {
  2338. bw = 1;
  2339. dram_set_bw(chan, 1);
  2340. cap_info->bw = bw;
  2341. if (data_training(dram, channel, params,
  2342. PI_READ_GATE_TRAINING)) {
  2343. printf("16bit error!!!\n");
  2344. goto error;
  2345. }
  2346. }
  2347. }
  2348. /*
  2349. * LPDDR3 CA training msut be trigger before other training.
  2350. * DDR3 is not have CA training.
  2351. */
  2352. if (params->base.dramtype == LPDDR3)
  2353. training_flag = PI_WRITE_LEVELING;
  2354. else
  2355. training_flag = PI_FULL_TRAINING;
  2356. if (params->base.dramtype != LPDDR4) {
  2357. if (data_training(dram, channel, params, training_flag)) {
  2358. printf("full training error!!!\n");
  2359. goto error;
  2360. }
  2361. }
  2362. /* detect col */
  2363. dram_set_max_col(chan, bw, &col_tmp);
  2364. if (sdram_detect_col(cap_info, col_tmp) != 0)
  2365. goto error;
  2366. /* detect bank */
  2367. dram_set_max_bank(chan, bw, &bk_tmp, &col_tmp);
  2368. sdram_detect_bank(cap_info, col_tmp, bk_tmp);
  2369. /* detect row */
  2370. dram_set_max_row(chan, bw, &row_tmp, &bk_tmp, &col_tmp);
  2371. if (sdram_detect_row(cap_info, col_tmp, bk_tmp, row_tmp) != 0)
  2372. goto error;
  2373. /* detect row_3_4 */
  2374. sdram_detect_row_3_4(cap_info, col_tmp, bk_tmp);
  2375. /* set ddrconfig */
  2376. cs0_cap = (1 << (cap_info->cs0_row + cap_info->col + cap_info->bk +
  2377. cap_info->bw - 20));
  2378. if (cap_info->row_3_4)
  2379. cs0_cap = cs0_cap * 3 / 4;
  2380. cap_info->cs1_row = cap_info->cs0_row;
  2381. set_memory_map(chan, channel, params);
  2382. ddrconfig = calculate_ddrconfig(params, channel);
  2383. if (-1 == ddrconfig)
  2384. goto error;
  2385. set_ddrconfig(chan, params, channel,
  2386. cap_info->ddrconfig);
  2387. /* detect cs1 row */
  2388. sdram_detect_cs1_row(cap_info, params->base.dramtype);
  2389. /* detect die bw */
  2390. sdram_detect_dbw(cap_info, params->base.dramtype);
  2391. return 0;
  2392. error:
  2393. return (-1);
  2394. }
  2395. static unsigned char calculate_stride(struct rk3399_sdram_params *params)
  2396. {
  2397. unsigned int gstride_type;
  2398. unsigned int channel;
  2399. unsigned int chinfo = 0;
  2400. unsigned int cap = 0;
  2401. unsigned int stride = -1;
  2402. unsigned int ch_cap[2] = {0, 0};
  2403. gstride_type = STRIDE_256B;
  2404. for (channel = 0; channel < 2; channel++) {
  2405. unsigned int cs0_cap = 0;
  2406. unsigned int cs1_cap = 0;
  2407. struct sdram_cap_info *cap_info =
  2408. &params->ch[channel].cap_info;
  2409. if (cap_info->col == 0)
  2410. continue;
  2411. cs0_cap = (1 << (cap_info->cs0_row + cap_info->col +
  2412. cap_info->bk + cap_info->bw - 20));
  2413. if (cap_info->rank > 1)
  2414. cs1_cap = cs0_cap >> (cap_info->cs0_row
  2415. - cap_info->cs1_row);
  2416. if (cap_info->row_3_4) {
  2417. cs0_cap = cs0_cap * 3 / 4;
  2418. cs1_cap = cs1_cap * 3 / 4;
  2419. }
  2420. ch_cap[channel] = cs0_cap + cs1_cap;
  2421. chinfo |= 1 << channel;
  2422. }
  2423. cap = ch_cap[0] + ch_cap[1];
  2424. if (params->base.num_channels == 1) {
  2425. if (chinfo & 1) /* channel a only */
  2426. stride = 0x17;
  2427. else /* channel b only */
  2428. stride = 0x18;
  2429. } else {/* 2 channel */
  2430. if (ch_cap[0] == ch_cap[1]) {
  2431. /* interleaved */
  2432. if (gstride_type == PART_STRIDE) {
  2433. /*
  2434. * first 64MB no interleaved other 256B interleaved
  2435. * if 786M+768M.useful space from 0-1280MB and
  2436. * 1536MB-1792MB
  2437. * if 1.5G+1.5G(continuous).useful space from 0-2560MB
  2438. * and 3072MB-3584MB
  2439. */
  2440. stride = 0x1F;
  2441. } else {
  2442. switch (cap) {
  2443. /* 512MB */
  2444. case 512:
  2445. stride = 0;
  2446. break;
  2447. /* 1GB unstride or 256B stride*/
  2448. case 1024:
  2449. stride = (gstride_type == UN_STRIDE) ?
  2450. 0x1 : 0x5;
  2451. break;
  2452. /*
  2453. * 768MB + 768MB same as total 2GB memory
  2454. * useful space: 0-768MB 1GB-1792MB
  2455. */
  2456. case 1536:
  2457. /* 2GB unstride or 256B or 512B stride */
  2458. case 2048:
  2459. stride = (gstride_type == UN_STRIDE) ?
  2460. 0x2 :
  2461. ((gstride_type == STRIDE_512B) ?
  2462. 0xA : 0x9);
  2463. break;
  2464. /* 1536MB + 1536MB */
  2465. case 3072:
  2466. stride = (gstride_type == UN_STRIDE) ?
  2467. 0x3 :
  2468. ((gstride_type == STRIDE_512B) ?
  2469. 0x12 : 0x11);
  2470. break;
  2471. /* 4GB unstride or 128B,256B,512B,4KB stride */
  2472. case 4096:
  2473. stride = (gstride_type == UN_STRIDE) ?
  2474. 0x3 : (0xC + gstride_type);
  2475. break;
  2476. }
  2477. }
  2478. }
  2479. if (ch_cap[0] == 2048 && ch_cap[1] == 1024) {
  2480. /* 2GB + 1GB */
  2481. stride = (gstride_type == UN_STRIDE) ? 0x3 : 0x19;
  2482. }
  2483. /*
  2484. * remain two channel capability not equal OR capability
  2485. * power function of 2
  2486. */
  2487. if (stride == (-1)) {
  2488. switch ((ch_cap[0] > ch_cap[1]) ?
  2489. ch_cap[0] : ch_cap[1]) {
  2490. case 256: /* 256MB + 128MB */
  2491. stride = 0;
  2492. break;
  2493. case 512: /* 512MB + 256MB */
  2494. stride = 1;
  2495. break;
  2496. case 1024:/* 1GB + 128MB/256MB/384MB/512MB/768MB */
  2497. stride = 2;
  2498. break;
  2499. case 2048: /* 2GB + 128MB/256MB/384MB/512MB/768MB/1GB */
  2500. stride = 3;
  2501. break;
  2502. default:
  2503. break;
  2504. }
  2505. }
  2506. if (stride == (-1))
  2507. goto error;
  2508. }
  2509. switch (stride) {
  2510. case 0xc:
  2511. printf("128B stride\n");
  2512. break;
  2513. case 5:
  2514. case 9:
  2515. case 0xd:
  2516. case 0x11:
  2517. case 0x19:
  2518. printf("256B stride\n");
  2519. break;
  2520. case 0xa:
  2521. case 0xe:
  2522. case 0x12:
  2523. printf("512B stride\n");
  2524. break;
  2525. case 0xf:
  2526. printf("4K stride\n");
  2527. break;
  2528. case 0x1f:
  2529. printf("32MB + 256B stride\n");
  2530. break;
  2531. default:
  2532. printf("no stride\n");
  2533. }
  2534. sdram_print_stride(stride);
  2535. return stride;
  2536. error:
  2537. printf("Cap not support!\n");
  2538. return (-1);
  2539. }
  2540. static void clear_channel_params(struct rk3399_sdram_params *params, u8 channel)
  2541. {
  2542. params->ch[channel].cap_info.rank = 0;
  2543. params->ch[channel].cap_info.col = 0;
  2544. params->ch[channel].cap_info.bk = 0;
  2545. params->ch[channel].cap_info.bw = 32;
  2546. params->ch[channel].cap_info.dbw = 32;
  2547. params->ch[channel].cap_info.row_3_4 = 0;
  2548. params->ch[channel].cap_info.cs0_row = 0;
  2549. params->ch[channel].cap_info.cs1_row = 0;
  2550. params->ch[channel].cap_info.ddrconfig = 0;
  2551. }
  2552. static int sdram_init(struct dram_info *dram,
  2553. struct rk3399_sdram_params *params)
  2554. {
  2555. unsigned char dramtype = params->base.dramtype;
  2556. unsigned int ddr_freq = params->base.ddr_freq;
  2557. int channel, ch, rank;
  2558. u32 tmp, ret;
  2559. debug("Starting SDRAM initialization...\n");
  2560. if ((dramtype == DDR3 && ddr_freq > 933) ||
  2561. (dramtype == LPDDR3 && ddr_freq > 933) ||
  2562. (dramtype == LPDDR4 && ddr_freq > 800)) {
  2563. debug("SDRAM frequency is to high!");
  2564. return -E2BIG;
  2565. }
  2566. /* detect rank */
  2567. for (ch = 0; ch < 2; ch++) {
  2568. params->ch[ch].cap_info.rank = 2;
  2569. for (rank = 2; rank != 0; rank--) {
  2570. for (channel = 0; channel < 2; channel++) {
  2571. const struct chan_info *chan =
  2572. &dram->chan[channel];
  2573. struct rockchip_cru *cru = dram->cru;
  2574. struct rk3399_ddr_publ_regs *publ = chan->publ;
  2575. phy_pctrl_reset(cru, channel);
  2576. phy_dll_bypass_set(publ, ddr_freq);
  2577. pctl_cfg(dram, chan, channel, params);
  2578. }
  2579. /* start to trigger initialization */
  2580. pctl_start(dram, params, 3);
  2581. /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
  2582. if (dramtype == LPDDR3)
  2583. udelay(10);
  2584. tmp = (rank == 2) ? 3 : 1;
  2585. dram_set_cs(&dram->chan[ch], tmp, 2048,
  2586. params->base.dramtype);
  2587. params->ch[ch].cap_info.rank = rank;
  2588. ret = dram->ops->data_training_first(dram, ch,
  2589. rank, params);
  2590. if (!ret) {
  2591. debug("%s: data trained for rank %d, ch %d\n",
  2592. __func__, rank, ch);
  2593. break;
  2594. }
  2595. }
  2596. /* Computed rank with associated channel number */
  2597. params->ch[ch].cap_info.rank = rank;
  2598. }
  2599. params->base.num_channels = 0;
  2600. for (channel = 0; channel < 2; channel++) {
  2601. const struct chan_info *chan = &dram->chan[channel];
  2602. struct sdram_cap_info *cap_info =
  2603. &params->ch[channel].cap_info;
  2604. if (cap_info->rank == 0) {
  2605. clear_channel_params(params, 1);
  2606. continue;
  2607. } else {
  2608. params->base.num_channels++;
  2609. }
  2610. printf("Channel ");
  2611. printf(channel ? "1: " : "0: ");
  2612. if (channel == 0)
  2613. set_ddr_stride(dram->pmusgrf, 0x17);
  2614. else
  2615. set_ddr_stride(dram->pmusgrf, 0x18);
  2616. if (dram_detect_cap(dram, params, channel)) {
  2617. printf("Cap error!\n");
  2618. continue;
  2619. }
  2620. sdram_print_ddr_info(cap_info, &params->base);
  2621. set_memory_map(chan, channel, params);
  2622. cap_info->ddrconfig =
  2623. calculate_ddrconfig(params, channel);
  2624. if (-1 == cap_info->ddrconfig) {
  2625. printf("no ddrconfig find, Cap not support!\n");
  2626. continue;
  2627. }
  2628. set_ddrconfig(chan, params, channel, cap_info->ddrconfig);
  2629. set_cap_relate_config(chan, params, channel);
  2630. }
  2631. if (params->base.num_channels == 0) {
  2632. printf("%s: ", __func__);
  2633. sdram_print_dram_type(params->base.dramtype);
  2634. printf(" - %dMHz failed!\n", params->base.ddr_freq);
  2635. return -EINVAL;
  2636. }
  2637. params->base.stride = calculate_stride(params);
  2638. dram_all_config(dram, params);
  2639. dram->ops->set_rate_index(dram, params);
  2640. debug("Finish SDRAM initialization...\n");
  2641. return 0;
  2642. }
  2643. static int rk3399_dmc_ofdata_to_platdata(struct udevice *dev)
  2644. {
  2645. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  2646. struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
  2647. int ret;
  2648. ret = dev_read_u32_array(dev, "rockchip,sdram-params",
  2649. (u32 *)&plat->sdram_params,
  2650. sizeof(plat->sdram_params) / sizeof(u32));
  2651. if (ret) {
  2652. printf("%s: Cannot read rockchip,sdram-params %d\n",
  2653. __func__, ret);
  2654. return ret;
  2655. }
  2656. ret = regmap_init_mem(dev_ofnode(dev), &plat->map);
  2657. if (ret)
  2658. printf("%s: regmap failed %d\n", __func__, ret);
  2659. #endif
  2660. return 0;
  2661. }
  2662. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  2663. static int conv_of_platdata(struct udevice *dev)
  2664. {
  2665. struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
  2666. struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
  2667. int ret;
  2668. ret = regmap_init_mem_platdata(dev, dtplat->reg,
  2669. ARRAY_SIZE(dtplat->reg) / 2,
  2670. &plat->map);
  2671. if (ret)
  2672. return ret;
  2673. return 0;
  2674. }
  2675. #endif
  2676. static const struct sdram_rk3399_ops rk3399_ops = {
  2677. #if !defined(CONFIG_RAM_RK3399_LPDDR4)
  2678. .data_training_first = data_training_first,
  2679. .set_rate_index = switch_to_phy_index1,
  2680. .modify_param = modify_param,
  2681. .get_phy_index_params = get_phy_index_params,
  2682. #else
  2683. .data_training_first = lpddr4_mr_detect,
  2684. .set_rate_index = lpddr4_set_rate,
  2685. .modify_param = lpddr4_modify_param,
  2686. .get_phy_index_params = lpddr4_get_phy_index_params,
  2687. #endif
  2688. };
  2689. static int rk3399_dmc_init(struct udevice *dev)
  2690. {
  2691. struct dram_info *priv = dev_get_priv(dev);
  2692. struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
  2693. int ret;
  2694. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  2695. struct rk3399_sdram_params *params = &plat->sdram_params;
  2696. #else
  2697. struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
  2698. struct rk3399_sdram_params *params =
  2699. (void *)dtplat->rockchip_sdram_params;
  2700. ret = conv_of_platdata(dev);
  2701. if (ret)
  2702. return ret;
  2703. #endif
  2704. priv->ops = &rk3399_ops;
  2705. priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);
  2706. priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  2707. priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
  2708. priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
  2709. priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
  2710. priv->pmucru = rockchip_get_pmucru();
  2711. priv->cru = rockchip_get_cru();
  2712. priv->chan[0].pctl = regmap_get_range(plat->map, 0);
  2713. priv->chan[0].pi = regmap_get_range(plat->map, 1);
  2714. priv->chan[0].publ = regmap_get_range(plat->map, 2);
  2715. priv->chan[0].msch = regmap_get_range(plat->map, 3);
  2716. priv->chan[1].pctl = regmap_get_range(plat->map, 4);
  2717. priv->chan[1].pi = regmap_get_range(plat->map, 5);
  2718. priv->chan[1].publ = regmap_get_range(plat->map, 6);
  2719. priv->chan[1].msch = regmap_get_range(plat->map, 7);
  2720. debug("con reg %p %p %p %p %p %p %p %p\n",
  2721. priv->chan[0].pctl, priv->chan[0].pi,
  2722. priv->chan[0].publ, priv->chan[0].msch,
  2723. priv->chan[1].pctl, priv->chan[1].pi,
  2724. priv->chan[1].publ, priv->chan[1].msch);
  2725. debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p, pmu %p\n", priv->cru,
  2726. priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru, priv->pmu);
  2727. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  2728. ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->ddr_clk);
  2729. #else
  2730. ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
  2731. #endif
  2732. if (ret) {
  2733. printf("%s clk get failed %d\n", __func__, ret);
  2734. return ret;
  2735. }
  2736. ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz);
  2737. if (ret < 0) {
  2738. printf("%s clk set failed %d\n", __func__, ret);
  2739. return ret;
  2740. }
  2741. ret = sdram_init(priv, params);
  2742. if (ret < 0) {
  2743. printf("%s DRAM init failed %d\n", __func__, ret);
  2744. return ret;
  2745. }
  2746. return 0;
  2747. }
  2748. #endif
  2749. static int rk3399_dmc_probe(struct udevice *dev)
  2750. {
  2751. #if defined(CONFIG_TPL_BUILD) || \
  2752. (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
  2753. if (rk3399_dmc_init(dev))
  2754. return 0;
  2755. #else
  2756. struct dram_info *priv = dev_get_priv(dev);
  2757. priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
  2758. debug("%s: pmugrf = %p\n", __func__, priv->pmugrf);
  2759. priv->info.base = CONFIG_SYS_SDRAM_BASE;
  2760. priv->info.size =
  2761. rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);
  2762. #endif
  2763. return 0;
  2764. }
  2765. static int rk3399_dmc_get_info(struct udevice *dev, struct ram_info *info)
  2766. {
  2767. struct dram_info *priv = dev_get_priv(dev);
  2768. *info = priv->info;
  2769. return 0;
  2770. }
  2771. static struct ram_ops rk3399_dmc_ops = {
  2772. .get_info = rk3399_dmc_get_info,
  2773. };
  2774. static const struct udevice_id rk3399_dmc_ids[] = {
  2775. { .compatible = "rockchip,rk3399-dmc" },
  2776. { }
  2777. };
  2778. U_BOOT_DRIVER(dmc_rk3399) = {
  2779. .name = "rockchip_rk3399_dmc",
  2780. .id = UCLASS_RAM,
  2781. .of_match = rk3399_dmc_ids,
  2782. .ops = &rk3399_dmc_ops,
  2783. #if defined(CONFIG_TPL_BUILD) || \
  2784. (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
  2785. .ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata,
  2786. #endif
  2787. .probe = rk3399_dmc_probe,
  2788. .priv_auto_alloc_size = sizeof(struct dram_info),
  2789. #if defined(CONFIG_TPL_BUILD) || \
  2790. (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
  2791. .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),
  2792. #endif
  2793. };