rockchip_sdhci.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Fuzhou Rockchip Electronics Co., Ltd
  4. *
  5. * Rockchip SD Host Controller Interface
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <dt-structs.h>
  10. #include <linux/err.h>
  11. #include <linux/libfdt.h>
  12. #include <malloc.h>
  13. #include <mapmem.h>
  14. #include <sdhci.h>
  15. #include <clk.h>
  16. /* 400KHz is max freq for card ID etc. Use that as min */
  17. #define EMMC_MIN_FREQ 400000
  18. struct rockchip_sdhc_plat {
  19. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  20. struct dtd_rockchip_rk3399_sdhci_5_1 dtplat;
  21. #endif
  22. struct mmc_config cfg;
  23. struct mmc mmc;
  24. };
  25. struct rockchip_sdhc {
  26. struct sdhci_host host;
  27. void *base;
  28. };
  29. static int arasan_sdhci_probe(struct udevice *dev)
  30. {
  31. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  32. struct rockchip_sdhc_plat *plat = dev_get_platdata(dev);
  33. struct rockchip_sdhc *prv = dev_get_priv(dev);
  34. struct sdhci_host *host = &prv->host;
  35. int max_frequency, ret;
  36. struct clk clk;
  37. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  38. struct dtd_rockchip_rk3399_sdhci_5_1 *dtplat = &plat->dtplat;
  39. host->name = dev->name;
  40. host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
  41. max_frequency = dtplat->max_frequency;
  42. ret = clk_get_by_driver_info(dev, dtplat->clocks, &clk);
  43. #else
  44. max_frequency = dev_read_u32_default(dev, "max-frequency", 0);
  45. ret = clk_get_by_index(dev, 0, &clk);
  46. #endif
  47. if (!ret) {
  48. ret = clk_set_rate(&clk, max_frequency);
  49. if (IS_ERR_VALUE(ret))
  50. printf("%s clk set rate fail!\n", __func__);
  51. } else {
  52. printf("%s fail to get clk\n", __func__);
  53. }
  54. host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
  55. host->max_clk = max_frequency;
  56. /*
  57. * The sdhci-driver only supports 4bit and 8bit, as sdhci_setup_cfg
  58. * doesn't allow us to clear MMC_MODE_4BIT. Consequently, we don't
  59. * check for other bus-width values.
  60. */
  61. if (host->bus_width == 8)
  62. host->host_caps |= MMC_MODE_8BIT;
  63. host->mmc = &plat->mmc;
  64. host->mmc->priv = &prv->host;
  65. host->mmc->dev = dev;
  66. upriv->mmc = host->mmc;
  67. ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ);
  68. if (ret)
  69. return ret;
  70. return sdhci_probe(dev);
  71. }
  72. static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
  73. {
  74. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  75. struct sdhci_host *host = dev_get_priv(dev);
  76. host->name = dev->name;
  77. host->ioaddr = dev_read_addr_ptr(dev);
  78. host->bus_width = dev_read_u32_default(dev, "bus-width", 4);
  79. #endif
  80. return 0;
  81. }
  82. static int rockchip_sdhci_bind(struct udevice *dev)
  83. {
  84. struct rockchip_sdhc_plat *plat = dev_get_platdata(dev);
  85. return sdhci_bind(dev, &plat->mmc, &plat->cfg);
  86. }
  87. static const struct udevice_id arasan_sdhci_ids[] = {
  88. { .compatible = "arasan,sdhci-5.1" },
  89. { }
  90. };
  91. U_BOOT_DRIVER(arasan_sdhci_drv) = {
  92. .name = "rockchip_rk3399_sdhci_5_1",
  93. .id = UCLASS_MMC,
  94. .of_match = arasan_sdhci_ids,
  95. .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
  96. .ops = &sdhci_ops,
  97. .bind = rockchip_sdhci_bind,
  98. .probe = arasan_sdhci_probe,
  99. .priv_auto_alloc_size = sizeof(struct rockchip_sdhc),
  100. .platdata_auto_alloc_size = sizeof(struct rockchip_sdhc_plat),
  101. };