ftsdc010_mci.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Faraday MMC/SD Host Controller
  4. *
  5. * (C) Copyright 2010 Faraday Technology
  6. * Dante Su <dantesu@faraday-tech.com>
  7. *
  8. * Copyright 2018 Andes Technology, Inc.
  9. * Author: Rick Chen (rick@andestech.com)
  10. */
  11. #include <common.h>
  12. #include <clk.h>
  13. #include <log.h>
  14. #include <malloc.h>
  15. #include <part.h>
  16. #include <mmc.h>
  17. #include <linux/bitops.h>
  18. #include <linux/io.h>
  19. #include <linux/errno.h>
  20. #include <asm/byteorder.h>
  21. #include <faraday/ftsdc010.h>
  22. #include "ftsdc010_mci.h"
  23. #include <dm.h>
  24. #include <dt-structs.h>
  25. #include <errno.h>
  26. #include <mapmem.h>
  27. #include <pwrseq.h>
  28. #include <syscon.h>
  29. #include <linux/err.h>
  30. DECLARE_GLOBAL_DATA_PTR;
  31. #define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */
  32. #define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */
  33. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  34. struct ftsdc010 {
  35. fdt32_t bus_width;
  36. bool cap_mmc_highspeed;
  37. bool cap_sd_highspeed;
  38. fdt32_t clock_freq_min_max[2];
  39. struct phandle_2_cell clocks[4];
  40. fdt32_t fifo_depth;
  41. fdt32_t reg[2];
  42. };
  43. #endif
  44. struct ftsdc010_plat {
  45. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  46. struct ftsdc010 dtplat;
  47. #endif
  48. struct mmc_config cfg;
  49. struct mmc mmc;
  50. };
  51. struct ftsdc_priv {
  52. struct clk clk;
  53. struct ftsdc010_chip chip;
  54. int fifo_depth;
  55. bool fifo_mode;
  56. u32 minmax[2];
  57. };
  58. static inline int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
  59. {
  60. struct ftsdc010_chip *chip = mmc->priv;
  61. struct ftsdc010_mmc __iomem *regs = chip->regs;
  62. int ret = -ETIMEDOUT;
  63. uint32_t ts, st;
  64. uint32_t cmd = FTSDC010_CMD_IDX(mmc_cmd->cmdidx);
  65. uint32_t arg = mmc_cmd->cmdarg;
  66. uint32_t flags = mmc_cmd->resp_type;
  67. cmd |= FTSDC010_CMD_CMD_EN;
  68. if (chip->acmd) {
  69. cmd |= FTSDC010_CMD_APP_CMD;
  70. chip->acmd = 0;
  71. }
  72. if (flags & MMC_RSP_PRESENT)
  73. cmd |= FTSDC010_CMD_NEED_RSP;
  74. if (flags & MMC_RSP_136)
  75. cmd |= FTSDC010_CMD_LONG_RSP;
  76. writel(FTSDC010_STATUS_RSP_MASK | FTSDC010_STATUS_CMD_SEND,
  77. &regs->clr);
  78. writel(arg, &regs->argu);
  79. writel(cmd, &regs->cmd);
  80. if (!(flags & (MMC_RSP_PRESENT | MMC_RSP_136))) {
  81. for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
  82. if (readl(&regs->status) & FTSDC010_STATUS_CMD_SEND) {
  83. writel(FTSDC010_STATUS_CMD_SEND, &regs->clr);
  84. ret = 0;
  85. break;
  86. }
  87. }
  88. } else {
  89. st = 0;
  90. for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
  91. st = readl(&regs->status);
  92. writel(st & FTSDC010_STATUS_RSP_MASK, &regs->clr);
  93. if (st & FTSDC010_STATUS_RSP_MASK)
  94. break;
  95. }
  96. if (st & FTSDC010_STATUS_RSP_CRC_OK) {
  97. if (flags & MMC_RSP_136) {
  98. mmc_cmd->response[0] = readl(&regs->rsp3);
  99. mmc_cmd->response[1] = readl(&regs->rsp2);
  100. mmc_cmd->response[2] = readl(&regs->rsp1);
  101. mmc_cmd->response[3] = readl(&regs->rsp0);
  102. } else {
  103. mmc_cmd->response[0] = readl(&regs->rsp0);
  104. }
  105. ret = 0;
  106. } else {
  107. debug("ftsdc010: rsp err (cmd=%d, st=0x%x)\n",
  108. mmc_cmd->cmdidx, st);
  109. }
  110. }
  111. if (ret) {
  112. debug("ftsdc010: cmd timeout (op code=%d)\n",
  113. mmc_cmd->cmdidx);
  114. } else if (mmc_cmd->cmdidx == MMC_CMD_APP_CMD) {
  115. chip->acmd = 1;
  116. }
  117. return ret;
  118. }
  119. static void ftsdc010_clkset(struct mmc *mmc, uint32_t rate)
  120. {
  121. struct ftsdc010_chip *chip = mmc->priv;
  122. struct ftsdc010_mmc __iomem *regs = chip->regs;
  123. uint32_t div;
  124. for (div = 0; div < 0x7f; ++div) {
  125. if (rate >= chip->sclk / (2 * (div + 1)))
  126. break;
  127. }
  128. chip->rate = chip->sclk / (2 * (div + 1));
  129. writel(FTSDC010_CCR_CLK_DIV(div), &regs->ccr);
  130. if (IS_SD(mmc)) {
  131. setbits_le32(&regs->ccr, FTSDC010_CCR_CLK_SD);
  132. if (chip->rate > 25000000)
  133. setbits_le32(&regs->ccr, FTSDC010_CCR_CLK_HISPD);
  134. else
  135. clrbits_le32(&regs->ccr, FTSDC010_CCR_CLK_HISPD);
  136. }
  137. }
  138. static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask)
  139. {
  140. int ret = -ETIMEDOUT;
  141. uint32_t st, timeout = 10000000;
  142. while (timeout--) {
  143. st = readl(&regs->status);
  144. if (!(st & mask))
  145. continue;
  146. writel(st & mask, &regs->clr);
  147. ret = 0;
  148. break;
  149. }
  150. if (ret){
  151. debug("ftsdc010: wait st(0x%x) timeout\n", mask);
  152. }
  153. return ret;
  154. }
  155. /*
  156. * u-boot mmc api
  157. */
  158. static int ftsdc010_request(struct udevice *dev, struct mmc_cmd *cmd,
  159. struct mmc_data *data)
  160. {
  161. struct mmc *mmc = mmc_get_mmc_dev(dev);
  162. int ret = -EOPNOTSUPP;
  163. uint32_t len = 0;
  164. struct ftsdc010_chip *chip = mmc->priv;
  165. struct ftsdc010_mmc __iomem *regs = chip->regs;
  166. if (data && (data->flags & MMC_DATA_WRITE) && chip->wprot) {
  167. printf("ftsdc010: the card is write protected!\n");
  168. return ret;
  169. }
  170. if (data) {
  171. uint32_t dcr;
  172. len = data->blocksize * data->blocks;
  173. /* 1. data disable + fifo reset */
  174. dcr = 0;
  175. #ifdef CONFIG_FTSDC010_SDIO
  176. dcr |= FTSDC010_DCR_FIFO_RST;
  177. #endif
  178. writel(dcr, &regs->dcr);
  179. /* 2. clear status register */
  180. writel(FTSDC010_STATUS_DATA_MASK | FTSDC010_STATUS_FIFO_URUN
  181. | FTSDC010_STATUS_FIFO_ORUN, &regs->clr);
  182. /* 3. data timeout (1 sec) */
  183. writel(chip->rate, &regs->dtr);
  184. /* 4. data length (bytes) */
  185. writel(len, &regs->dlr);
  186. /* 5. data enable */
  187. dcr = (ffs(data->blocksize) - 1) | FTSDC010_DCR_DATA_EN;
  188. if (data->flags & MMC_DATA_WRITE)
  189. dcr |= FTSDC010_DCR_DATA_WRITE;
  190. writel(dcr, &regs->dcr);
  191. }
  192. ret = ftsdc010_send_cmd(mmc, cmd);
  193. if (ret) {
  194. printf("ftsdc010: CMD%d failed\n", cmd->cmdidx);
  195. return ret;
  196. }
  197. if (!data)
  198. return ret;
  199. if (data->flags & MMC_DATA_WRITE) {
  200. const uint8_t *buf = (const uint8_t *)data->src;
  201. while (len > 0) {
  202. int wlen;
  203. /* wait for tx ready */
  204. ret = ftsdc010_wait(regs, FTSDC010_STATUS_FIFO_URUN);
  205. if (ret)
  206. break;
  207. /* write bytes to ftsdc010 */
  208. for (wlen = 0; wlen < len && wlen < chip->fifo; ) {
  209. writel(*(uint32_t *)buf, &regs->dwr);
  210. buf += 4;
  211. wlen += 4;
  212. }
  213. len -= wlen;
  214. }
  215. } else {
  216. uint8_t *buf = (uint8_t *)data->dest;
  217. while (len > 0) {
  218. int rlen;
  219. /* wait for rx ready */
  220. ret = ftsdc010_wait(regs, FTSDC010_STATUS_FIFO_ORUN);
  221. if (ret)
  222. break;
  223. /* fetch bytes from ftsdc010 */
  224. for (rlen = 0; rlen < len && rlen < chip->fifo; ) {
  225. *(uint32_t *)buf = readl(&regs->dwr);
  226. buf += 4;
  227. rlen += 4;
  228. }
  229. len -= rlen;
  230. }
  231. }
  232. if (!ret) {
  233. ret = ftsdc010_wait(regs,
  234. FTSDC010_STATUS_DATA_END | FTSDC010_STATUS_DATA_CRC_OK);
  235. }
  236. return ret;
  237. }
  238. static int ftsdc010_set_ios(struct udevice *dev)
  239. {
  240. struct mmc *mmc = mmc_get_mmc_dev(dev);
  241. struct ftsdc010_chip *chip = mmc->priv;
  242. struct ftsdc010_mmc __iomem *regs = chip->regs;
  243. ftsdc010_clkset(mmc, mmc->clock);
  244. clrbits_le32(&regs->bwr, FTSDC010_BWR_MODE_MASK);
  245. switch (mmc->bus_width) {
  246. case 4:
  247. setbits_le32(&regs->bwr, FTSDC010_BWR_MODE_4BIT);
  248. break;
  249. case 8:
  250. setbits_le32(&regs->bwr, FTSDC010_BWR_MODE_8BIT);
  251. break;
  252. default:
  253. setbits_le32(&regs->bwr, FTSDC010_BWR_MODE_1BIT);
  254. break;
  255. }
  256. return 0;
  257. }
  258. static int ftsdc010_get_cd(struct udevice *dev)
  259. {
  260. struct mmc *mmc = mmc_get_mmc_dev(dev);
  261. struct ftsdc010_chip *chip = mmc->priv;
  262. struct ftsdc010_mmc __iomem *regs = chip->regs;
  263. return !(readl(&regs->status) & FTSDC010_STATUS_CARD_DETECT);
  264. }
  265. static int ftsdc010_get_wp(struct udevice *dev)
  266. {
  267. struct mmc *mmc = mmc_get_mmc_dev(dev);
  268. struct ftsdc010_chip *chip = mmc->priv;
  269. struct ftsdc010_mmc __iomem *regs = chip->regs;
  270. if (readl(&regs->status) & FTSDC010_STATUS_WRITE_PROT) {
  271. printf("ftsdc010: write protected\n");
  272. chip->wprot = 1;
  273. }
  274. return 0;
  275. }
  276. static int ftsdc010_init(struct mmc *mmc)
  277. {
  278. struct ftsdc010_chip *chip = mmc->priv;
  279. struct ftsdc010_mmc __iomem *regs = chip->regs;
  280. uint32_t ts;
  281. chip->fifo = (readl(&regs->feature) & 0xff) << 2;
  282. /* 1. chip reset */
  283. writel(FTSDC010_CMD_SDC_RST, &regs->cmd);
  284. for (ts = get_timer(0); get_timer(ts) < CFG_RST_TIMEOUT; ) {
  285. if (readl(&regs->cmd) & FTSDC010_CMD_SDC_RST)
  286. continue;
  287. break;
  288. }
  289. if (readl(&regs->cmd) & FTSDC010_CMD_SDC_RST) {
  290. printf("ftsdc010: reset failed\n");
  291. return -EOPNOTSUPP;
  292. }
  293. /* 2. enter low speed mode (400k card detection) */
  294. ftsdc010_clkset(mmc, 400000);
  295. /* 3. interrupt disabled */
  296. writel(0, &regs->int_mask);
  297. return 0;
  298. }
  299. static int ftsdc010_probe(struct udevice *dev)
  300. {
  301. struct mmc *mmc = mmc_get_mmc_dev(dev);
  302. return ftsdc010_init(mmc);
  303. }
  304. const struct dm_mmc_ops dm_ftsdc010_mmc_ops = {
  305. .send_cmd = ftsdc010_request,
  306. .set_ios = ftsdc010_set_ios,
  307. .get_cd = ftsdc010_get_cd,
  308. .get_wp = ftsdc010_get_wp,
  309. };
  310. static void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
  311. uint caps, u32 max_clk, u32 min_clk)
  312. {
  313. cfg->name = name;
  314. cfg->f_min = min_clk;
  315. cfg->f_max = max_clk;
  316. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
  317. cfg->host_caps = caps;
  318. if (buswidth == 8) {
  319. cfg->host_caps |= MMC_MODE_8BIT;
  320. cfg->host_caps &= ~MMC_MODE_4BIT;
  321. } else {
  322. cfg->host_caps |= MMC_MODE_4BIT;
  323. cfg->host_caps &= ~MMC_MODE_8BIT;
  324. }
  325. cfg->part_type = PART_TYPE_DOS;
  326. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  327. }
  328. static int ftsdc010_mmc_ofdata_to_platdata(struct udevice *dev)
  329. {
  330. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  331. struct ftsdc_priv *priv = dev_get_priv(dev);
  332. struct ftsdc010_chip *chip = &priv->chip;
  333. chip->name = dev->name;
  334. chip->ioaddr = (void *)devfdt_get_addr(dev);
  335. chip->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  336. "bus-width", 4);
  337. chip->priv = dev;
  338. priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  339. "fifo-depth", 0);
  340. priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
  341. "fifo-mode");
  342. if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
  343. "clock-freq-min-max", priv->minmax, 2)) {
  344. int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  345. "max-frequency", -EINVAL);
  346. if (val < 0)
  347. return val;
  348. priv->minmax[0] = 400000; /* 400 kHz */
  349. priv->minmax[1] = val;
  350. } else {
  351. debug("%s: 'clock-freq-min-max' property was deprecated.\n",
  352. __func__);
  353. }
  354. #endif
  355. chip->sclk = priv->minmax[1];
  356. chip->regs = chip->ioaddr;
  357. return 0;
  358. }
  359. static int ftsdc010_mmc_probe(struct udevice *dev)
  360. {
  361. struct ftsdc010_plat *plat = dev_get_platdata(dev);
  362. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  363. struct ftsdc_priv *priv = dev_get_priv(dev);
  364. struct ftsdc010_chip *chip = &priv->chip;
  365. struct udevice *pwr_dev __maybe_unused;
  366. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  367. int ret;
  368. struct ftsdc010 *dtplat = &plat->dtplat;
  369. chip->name = dev->name;
  370. chip->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
  371. chip->buswidth = dtplat->bus_width;
  372. chip->priv = dev;
  373. chip->dev_index = 1;
  374. memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax));
  375. ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->clk);
  376. if (ret < 0)
  377. return ret;
  378. #endif
  379. if (dev_read_bool(dev, "cap-mmc-highspeed") || \
  380. dev_read_bool(dev, "cap-sd-highspeed"))
  381. chip->caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
  382. ftsdc_setup_cfg(&plat->cfg, dev->name, chip->buswidth, chip->caps,
  383. priv->minmax[1] , priv->minmax[0]);
  384. chip->mmc = &plat->mmc;
  385. chip->mmc->priv = &priv->chip;
  386. chip->mmc->dev = dev;
  387. upriv->mmc = chip->mmc;
  388. return ftsdc010_probe(dev);
  389. }
  390. int ftsdc010_mmc_bind(struct udevice *dev)
  391. {
  392. struct ftsdc010_plat *plat = dev_get_platdata(dev);
  393. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  394. }
  395. static const struct udevice_id ftsdc010_mmc_ids[] = {
  396. { .compatible = "andestech,atfsdc010" },
  397. { }
  398. };
  399. U_BOOT_DRIVER(ftsdc010_mmc) = {
  400. .name = "ftsdc010_mmc",
  401. .id = UCLASS_MMC,
  402. .of_match = ftsdc010_mmc_ids,
  403. .ofdata_to_platdata = ftsdc010_mmc_ofdata_to_platdata,
  404. .ops = &dm_ftsdc010_mmc_ops,
  405. .bind = ftsdc010_mmc_bind,
  406. .probe = ftsdc010_mmc_probe,
  407. .priv_auto_alloc_size = sizeof(struct ftsdc_priv),
  408. .platdata_auto_alloc_size = sizeof(struct ftsdc010_plat),
  409. };