mtk-power-domain.c 9.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 MediaTek Inc.
  4. * Author: Ryder Lee <ryder.lee@mediatek.com>
  5. */
  6. #include <clk.h>
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <power-domain-uclass.h>
  10. #include <regmap.h>
  11. #include <syscon.h>
  12. #include <asm/io.h>
  13. #include <asm/processor.h>
  14. #include <linux/iopoll.h>
  15. #include <dt-bindings/power/mt7623-power.h>
  16. #include <dt-bindings/power/mt7629-power.h>
  17. #define SPM_EN (0xb16 << 16 | 0x1)
  18. #define SPM_VDE_PWR_CON 0x0210
  19. #define SPM_MFG_PWR_CON 0x0214
  20. #define SPM_ISP_PWR_CON 0x0238
  21. #define SPM_DIS_PWR_CON 0x023c
  22. #define SPM_CONN_PWR_CON 0x0280
  23. #define SPM_BDP_PWR_CON 0x029c
  24. #define SPM_ETH_PWR_CON 0x02a0
  25. #define SPM_HIF_PWR_CON 0x02a4
  26. #define SPM_IFR_MSC_PWR_CON 0x02a8
  27. #define SPM_ETHSYS_PWR_CON 0x2e0
  28. #define SPM_HIF0_PWR_CON 0x2e4
  29. #define SPM_HIF1_PWR_CON 0x2e8
  30. #define SPM_PWR_STATUS 0x60c
  31. #define SPM_PWR_STATUS_2ND 0x610
  32. #define PWR_RST_B_BIT BIT(0)
  33. #define PWR_ISO_BIT BIT(1)
  34. #define PWR_ON_BIT BIT(2)
  35. #define PWR_ON_2ND_BIT BIT(3)
  36. #define PWR_CLK_DIS_BIT BIT(4)
  37. #define PWR_STATUS_CONN BIT(1)
  38. #define PWR_STATUS_DISP BIT(3)
  39. #define PWR_STATUS_MFG BIT(4)
  40. #define PWR_STATUS_ISP BIT(5)
  41. #define PWR_STATUS_VDEC BIT(7)
  42. #define PWR_STATUS_BDP BIT(14)
  43. #define PWR_STATUS_ETH BIT(15)
  44. #define PWR_STATUS_HIF BIT(16)
  45. #define PWR_STATUS_IFR_MSC BIT(17)
  46. #define PWR_STATUS_ETHSYS BIT(24)
  47. #define PWR_STATUS_HIF0 BIT(25)
  48. #define PWR_STATUS_HIF1 BIT(26)
  49. /* Infrasys configuration */
  50. #define INFRA_TOPDCM_CTRL 0x10
  51. #define INFRA_TOPAXI_PROT_EN 0x220
  52. #define INFRA_TOPAXI_PROT_STA1 0x228
  53. #define DCM_TOP_EN BIT(0)
  54. enum scp_domain_type {
  55. SCPSYS_MT7622,
  56. SCPSYS_MT7623,
  57. SCPSYS_MT7629,
  58. };
  59. struct scp_domain;
  60. struct scp_domain_data {
  61. struct scp_domain *scpd;
  62. u32 sta_mask;
  63. int ctl_offs;
  64. u32 sram_pdn_bits;
  65. u32 sram_pdn_ack_bits;
  66. u32 bus_prot_mask;
  67. };
  68. struct scp_domain {
  69. void __iomem *base;
  70. void __iomem *infracfg;
  71. enum scp_domain_type type;
  72. struct scp_domain_data *data;
  73. };
  74. static struct scp_domain_data scp_domain_mt7623[] = {
  75. [MT7623_POWER_DOMAIN_CONN] = {
  76. .sta_mask = PWR_STATUS_CONN,
  77. .ctl_offs = SPM_CONN_PWR_CON,
  78. .bus_prot_mask = BIT(8) | BIT(2),
  79. },
  80. [MT7623_POWER_DOMAIN_DISP] = {
  81. .sta_mask = PWR_STATUS_DISP,
  82. .ctl_offs = SPM_DIS_PWR_CON,
  83. .sram_pdn_bits = GENMASK(11, 8),
  84. .bus_prot_mask = BIT(2),
  85. },
  86. [MT7623_POWER_DOMAIN_MFG] = {
  87. .sta_mask = PWR_STATUS_MFG,
  88. .ctl_offs = SPM_MFG_PWR_CON,
  89. .sram_pdn_bits = GENMASK(11, 8),
  90. .sram_pdn_ack_bits = GENMASK(12, 12),
  91. },
  92. [MT7623_POWER_DOMAIN_VDEC] = {
  93. .sta_mask = PWR_STATUS_VDEC,
  94. .ctl_offs = SPM_VDE_PWR_CON,
  95. .sram_pdn_bits = GENMASK(11, 8),
  96. .sram_pdn_ack_bits = GENMASK(12, 12),
  97. },
  98. [MT7623_POWER_DOMAIN_ISP] = {
  99. .sta_mask = PWR_STATUS_ISP,
  100. .ctl_offs = SPM_ISP_PWR_CON,
  101. .sram_pdn_bits = GENMASK(11, 8),
  102. .sram_pdn_ack_bits = GENMASK(13, 12),
  103. },
  104. [MT7623_POWER_DOMAIN_BDP] = {
  105. .sta_mask = PWR_STATUS_BDP,
  106. .ctl_offs = SPM_BDP_PWR_CON,
  107. .sram_pdn_bits = GENMASK(11, 8),
  108. },
  109. [MT7623_POWER_DOMAIN_ETH] = {
  110. .sta_mask = PWR_STATUS_ETH,
  111. .ctl_offs = SPM_ETH_PWR_CON,
  112. .sram_pdn_bits = GENMASK(11, 8),
  113. .sram_pdn_ack_bits = GENMASK(15, 12),
  114. },
  115. [MT7623_POWER_DOMAIN_HIF] = {
  116. .sta_mask = PWR_STATUS_HIF,
  117. .ctl_offs = SPM_HIF_PWR_CON,
  118. .sram_pdn_bits = GENMASK(11, 8),
  119. .sram_pdn_ack_bits = GENMASK(15, 12),
  120. },
  121. [MT7623_POWER_DOMAIN_IFR_MSC] = {
  122. .sta_mask = PWR_STATUS_IFR_MSC,
  123. .ctl_offs = SPM_IFR_MSC_PWR_CON,
  124. },
  125. };
  126. static struct scp_domain_data scp_domain_mt7629[] = {
  127. [MT7629_POWER_DOMAIN_ETHSYS] = {
  128. .sta_mask = PWR_STATUS_ETHSYS,
  129. .ctl_offs = SPM_ETHSYS_PWR_CON,
  130. .sram_pdn_bits = GENMASK(11, 8),
  131. .sram_pdn_ack_bits = GENMASK(15, 12),
  132. .bus_prot_mask = (BIT(3) | BIT(17)),
  133. },
  134. [MT7629_POWER_DOMAIN_HIF0] = {
  135. .sta_mask = PWR_STATUS_HIF0,
  136. .ctl_offs = SPM_HIF0_PWR_CON,
  137. .sram_pdn_bits = GENMASK(11, 8),
  138. .sram_pdn_ack_bits = GENMASK(15, 12),
  139. .bus_prot_mask = GENMASK(25, 24),
  140. },
  141. [MT7629_POWER_DOMAIN_HIF1] = {
  142. .sta_mask = PWR_STATUS_HIF1,
  143. .ctl_offs = SPM_HIF1_PWR_CON,
  144. .sram_pdn_bits = GENMASK(11, 8),
  145. .sram_pdn_ack_bits = GENMASK(15, 12),
  146. .bus_prot_mask = GENMASK(28, 26),
  147. },
  148. };
  149. /**
  150. * This function enables the bus protection bits for disabled power
  151. * domains so that the system does not hang when some unit accesses the
  152. * bus while in power down.
  153. */
  154. static int mtk_infracfg_set_bus_protection(void __iomem *infracfg,
  155. u32 mask)
  156. {
  157. u32 val;
  158. clrsetbits_le32(infracfg + INFRA_TOPAXI_PROT_EN, mask, mask);
  159. return readl_poll_timeout(infracfg + INFRA_TOPAXI_PROT_STA1, val,
  160. (val & mask) == mask, 100);
  161. }
  162. static int mtk_infracfg_clear_bus_protection(void __iomem *infracfg,
  163. u32 mask)
  164. {
  165. u32 val;
  166. clrbits_le32(infracfg + INFRA_TOPAXI_PROT_EN, mask);
  167. return readl_poll_timeout(infracfg + INFRA_TOPAXI_PROT_STA1, val,
  168. !(val & mask), 100);
  169. }
  170. static int scpsys_domain_is_on(struct scp_domain_data *data)
  171. {
  172. struct scp_domain *scpd = data->scpd;
  173. u32 sta = readl(scpd->base + SPM_PWR_STATUS) &
  174. data->sta_mask;
  175. u32 sta2 = readl(scpd->base + SPM_PWR_STATUS_2ND) &
  176. data->sta_mask;
  177. /*
  178. * A domain is on when both status bits are set. If only one is set
  179. * return an error. This happens while powering up a domain
  180. */
  181. if (sta && sta2)
  182. return true;
  183. if (!sta && !sta2)
  184. return false;
  185. return -EINVAL;
  186. }
  187. static int scpsys_power_on(struct power_domain *power_domain)
  188. {
  189. struct scp_domain *scpd = dev_get_priv(power_domain->dev);
  190. struct scp_domain_data *data = &scpd->data[power_domain->id];
  191. void __iomem *ctl_addr = scpd->base + data->ctl_offs;
  192. u32 pdn_ack = data->sram_pdn_ack_bits;
  193. u32 val;
  194. int ret, tmp;
  195. writel(SPM_EN, scpd->base);
  196. val = readl(ctl_addr);
  197. val |= PWR_ON_BIT;
  198. writel(val, ctl_addr);
  199. val |= PWR_ON_2ND_BIT;
  200. writel(val, ctl_addr);
  201. ret = readx_poll_timeout(scpsys_domain_is_on, data, tmp, tmp > 0,
  202. 100);
  203. if (ret < 0)
  204. return ret;
  205. val &= ~PWR_CLK_DIS_BIT;
  206. writel(val, ctl_addr);
  207. val &= ~PWR_ISO_BIT;
  208. writel(val, ctl_addr);
  209. val |= PWR_RST_B_BIT;
  210. writel(val, ctl_addr);
  211. val &= ~data->sram_pdn_bits;
  212. writel(val, ctl_addr);
  213. ret = readl_poll_timeout(ctl_addr, tmp, !(tmp & pdn_ack), 100);
  214. if (ret < 0)
  215. return ret;
  216. if (data->bus_prot_mask) {
  217. ret = mtk_infracfg_clear_bus_protection(scpd->infracfg,
  218. data->bus_prot_mask);
  219. if (ret)
  220. return ret;
  221. }
  222. return 0;
  223. }
  224. static int scpsys_power_off(struct power_domain *power_domain)
  225. {
  226. struct scp_domain *scpd = dev_get_priv(power_domain->dev);
  227. struct scp_domain_data *data = &scpd->data[power_domain->id];
  228. void __iomem *ctl_addr = scpd->base + data->ctl_offs;
  229. u32 pdn_ack = data->sram_pdn_ack_bits;
  230. u32 val;
  231. int ret, tmp;
  232. if (data->bus_prot_mask) {
  233. ret = mtk_infracfg_set_bus_protection(scpd->infracfg,
  234. data->bus_prot_mask);
  235. if (ret)
  236. return ret;
  237. }
  238. val = readl(ctl_addr);
  239. val |= data->sram_pdn_bits;
  240. writel(val, ctl_addr);
  241. ret = readl_poll_timeout(ctl_addr, tmp, (tmp & pdn_ack) == pdn_ack,
  242. 100);
  243. if (ret < 0)
  244. return ret;
  245. val |= PWR_ISO_BIT;
  246. writel(val, ctl_addr);
  247. val &= ~PWR_RST_B_BIT;
  248. writel(val, ctl_addr);
  249. val |= PWR_CLK_DIS_BIT;
  250. writel(val, ctl_addr);
  251. val &= ~PWR_ON_BIT;
  252. writel(val, ctl_addr);
  253. val &= ~PWR_ON_2ND_BIT;
  254. writel(val, ctl_addr);
  255. ret = readx_poll_timeout(scpsys_domain_is_on, data, tmp, !tmp, 100);
  256. if (ret < 0)
  257. return ret;
  258. return 0;
  259. }
  260. static int scpsys_power_request(struct power_domain *power_domain)
  261. {
  262. struct scp_domain *scpd = dev_get_priv(power_domain->dev);
  263. struct scp_domain_data *data;
  264. data = &scpd->data[power_domain->id];
  265. data->scpd = scpd;
  266. return 0;
  267. }
  268. static int scpsys_power_free(struct power_domain *power_domain)
  269. {
  270. return 0;
  271. }
  272. static int mtk_power_domain_hook(struct udevice *dev)
  273. {
  274. struct scp_domain *scpd = dev_get_priv(dev);
  275. scpd->type = (enum scp_domain_type)dev_get_driver_data(dev);
  276. switch (scpd->type) {
  277. case SCPSYS_MT7623:
  278. scpd->data = scp_domain_mt7623;
  279. break;
  280. case SCPSYS_MT7622:
  281. case SCPSYS_MT7629:
  282. scpd->data = scp_domain_mt7629;
  283. break;
  284. default:
  285. return -EINVAL;
  286. }
  287. return 0;
  288. }
  289. static int mtk_power_domain_probe(struct udevice *dev)
  290. {
  291. struct ofnode_phandle_args args;
  292. struct scp_domain *scpd = dev_get_priv(dev);
  293. struct regmap *regmap;
  294. struct clk_bulk bulk;
  295. int err;
  296. scpd->base = dev_read_addr_ptr(dev);
  297. if (!scpd->base)
  298. return -ENOENT;
  299. err = mtk_power_domain_hook(dev);
  300. if (err)
  301. return err;
  302. /* get corresponding syscon phandle */
  303. err = dev_read_phandle_with_args(dev, "infracfg", NULL, 0, 0, &args);
  304. if (err)
  305. return err;
  306. regmap = syscon_node_to_regmap(args.node);
  307. if (IS_ERR(regmap))
  308. return PTR_ERR(regmap);
  309. scpd->infracfg = regmap_get_range(regmap, 0);
  310. if (!scpd->infracfg)
  311. return -ENOENT;
  312. /* enable Infra DCM */
  313. setbits_le32(scpd->infracfg + INFRA_TOPDCM_CTRL, DCM_TOP_EN);
  314. err = clk_get_bulk(dev, &bulk);
  315. if (err)
  316. return err;
  317. return clk_enable_bulk(&bulk);
  318. }
  319. static const struct udevice_id mtk_power_domain_ids[] = {
  320. {
  321. .compatible = "mediatek,mt7622-scpsys",
  322. .data = SCPSYS_MT7622,
  323. },
  324. {
  325. .compatible = "mediatek,mt7623-scpsys",
  326. .data = SCPSYS_MT7623,
  327. },
  328. {
  329. .compatible = "mediatek,mt7629-scpsys",
  330. .data = SCPSYS_MT7629,
  331. },
  332. { /* sentinel */ }
  333. };
  334. struct power_domain_ops mtk_power_domain_ops = {
  335. .rfree = scpsys_power_free,
  336. .off = scpsys_power_off,
  337. .on = scpsys_power_on,
  338. .request = scpsys_power_request,
  339. };
  340. U_BOOT_DRIVER(mtk_power_domain) = {
  341. .name = "mtk_power_domain",
  342. .id = UCLASS_POWER_DOMAIN,
  343. .ops = &mtk_power_domain_ops,
  344. .probe = mtk_power_domain_probe,
  345. .of_match = mtk_power_domain_ids,
  346. .priv_auto_alloc_size = sizeof(struct scp_domain),
  347. };