meson-gx-pwrc-vpu.c 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Amlogic Meson VPU Power Domain Controller driver
  4. *
  5. * Copyright (c) 2018 BayLibre, SAS.
  6. * Author: Neil Armstrong <narmstrong@baylibre.com>
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <power-domain-uclass.h>
  11. #include <regmap.h>
  12. #include <syscon.h>
  13. #include <reset.h>
  14. #include <clk.h>
  15. enum {
  16. VPU_PWRC_COMPATIBLE_GX = 0,
  17. VPU_PWRC_COMPATIBLE_G12A = 1,
  18. };
  19. /* AO Offsets */
  20. #define AO_RTI_GEN_PWR_SLEEP0 (0x3a << 2)
  21. #define GEN_PWR_VPU_HDMI BIT(8)
  22. #define GEN_PWR_VPU_HDMI_ISO BIT(9)
  23. /* HHI Offsets */
  24. #define HHI_MEM_PD_REG0 (0x40 << 2)
  25. #define HHI_VPU_MEM_PD_REG0 (0x41 << 2)
  26. #define HHI_VPU_MEM_PD_REG1 (0x42 << 2)
  27. #define HHI_VPU_MEM_PD_REG2 (0x4d << 2)
  28. struct meson_gx_pwrc_vpu_priv {
  29. struct regmap *regmap_ao;
  30. struct regmap *regmap_hhi;
  31. struct reset_ctl_bulk resets;
  32. struct clk_bulk clks;
  33. };
  34. static int meson_pwrc_vpu_request(struct power_domain *power_domain)
  35. {
  36. return 0;
  37. }
  38. static int meson_pwrc_vpu_free(struct power_domain *power_domain)
  39. {
  40. return 0;
  41. }
  42. static int meson_gx_pwrc_vpu_on(struct power_domain *power_domain)
  43. {
  44. struct meson_gx_pwrc_vpu_priv *priv = dev_get_priv(power_domain->dev);
  45. int i, ret;
  46. regmap_update_bits(priv->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
  47. GEN_PWR_VPU_HDMI, 0);
  48. udelay(20);
  49. /* Power Up Memories */
  50. for (i = 0; i < 32; i += 2) {
  51. regmap_update_bits(priv->regmap_hhi, HHI_VPU_MEM_PD_REG0,
  52. 0x3 << i, 0);
  53. udelay(5);
  54. }
  55. for (i = 0; i < 32; i += 2) {
  56. regmap_update_bits(priv->regmap_hhi, HHI_VPU_MEM_PD_REG1,
  57. 0x3 << i, 0);
  58. udelay(5);
  59. }
  60. for (i = 8; i < 16; i++) {
  61. regmap_update_bits(priv->regmap_hhi, HHI_MEM_PD_REG0,
  62. BIT(i), 0);
  63. udelay(5);
  64. }
  65. udelay(20);
  66. ret = reset_assert_bulk(&priv->resets);
  67. if (ret)
  68. return ret;
  69. regmap_update_bits(priv->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
  70. GEN_PWR_VPU_HDMI_ISO, 0);
  71. ret = reset_deassert_bulk(&priv->resets);
  72. if (ret)
  73. return ret;
  74. ret = clk_enable_bulk(&priv->clks);
  75. if (ret)
  76. return ret;
  77. return 0;
  78. }
  79. static int meson_g12a_pwrc_vpu_on(struct power_domain *power_domain)
  80. {
  81. struct meson_gx_pwrc_vpu_priv *priv = dev_get_priv(power_domain->dev);
  82. int i, ret;
  83. regmap_update_bits(priv->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
  84. GEN_PWR_VPU_HDMI, 0);
  85. udelay(20);
  86. /* Power Up Memories */
  87. for (i = 0; i < 32; i += 2) {
  88. regmap_update_bits(priv->regmap_hhi, HHI_VPU_MEM_PD_REG0,
  89. 0x3 << i, 0);
  90. udelay(5);
  91. }
  92. for (i = 0; i < 32; i += 2) {
  93. regmap_update_bits(priv->regmap_hhi, HHI_VPU_MEM_PD_REG1,
  94. 0x3 << i, 0);
  95. udelay(5);
  96. }
  97. for (i = 0; i < 32; i += 2) {
  98. regmap_update_bits(priv->regmap_hhi, HHI_VPU_MEM_PD_REG2,
  99. 0x3 << i, 0);
  100. udelay(5);
  101. }
  102. for (i = 8; i < 16; i++) {
  103. regmap_update_bits(priv->regmap_hhi, HHI_MEM_PD_REG0,
  104. BIT(i), 0);
  105. udelay(5);
  106. }
  107. udelay(20);
  108. ret = reset_assert_bulk(&priv->resets);
  109. if (ret)
  110. return ret;
  111. regmap_update_bits(priv->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
  112. GEN_PWR_VPU_HDMI_ISO, 0);
  113. ret = reset_deassert_bulk(&priv->resets);
  114. if (ret)
  115. return ret;
  116. ret = clk_enable_bulk(&priv->clks);
  117. if (ret)
  118. return ret;
  119. return 0;
  120. }
  121. static int meson_pwrc_vpu_on(struct power_domain *power_domain)
  122. {
  123. unsigned int compat = dev_get_driver_data(power_domain->dev);
  124. switch (compat) {
  125. case VPU_PWRC_COMPATIBLE_GX:
  126. return meson_gx_pwrc_vpu_on(power_domain);
  127. case VPU_PWRC_COMPATIBLE_G12A:
  128. return meson_g12a_pwrc_vpu_on(power_domain);
  129. }
  130. return -EINVAL;
  131. }
  132. static int meson_gx_pwrc_vpu_off(struct power_domain *power_domain)
  133. {
  134. struct meson_gx_pwrc_vpu_priv *priv = dev_get_priv(power_domain->dev);
  135. int i;
  136. regmap_update_bits(priv->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
  137. GEN_PWR_VPU_HDMI_ISO, GEN_PWR_VPU_HDMI_ISO);
  138. udelay(20);
  139. /* Power Down Memories */
  140. for (i = 0; i < 32; i += 2) {
  141. regmap_update_bits(priv->regmap_hhi, HHI_VPU_MEM_PD_REG0,
  142. 0x3 << i, 0x3 << i);
  143. udelay(5);
  144. }
  145. for (i = 0; i < 32; i += 2) {
  146. regmap_update_bits(priv->regmap_hhi, HHI_VPU_MEM_PD_REG1,
  147. 0x3 << i, 0x3 << i);
  148. udelay(5);
  149. }
  150. for (i = 8; i < 16; i++) {
  151. regmap_update_bits(priv->regmap_hhi, HHI_MEM_PD_REG0,
  152. BIT(i), BIT(i));
  153. udelay(5);
  154. }
  155. udelay(20);
  156. regmap_update_bits(priv->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
  157. GEN_PWR_VPU_HDMI, GEN_PWR_VPU_HDMI);
  158. mdelay(20);
  159. clk_disable_bulk(&priv->clks);
  160. return 0;
  161. }
  162. static int meson_g12a_pwrc_vpu_off(struct power_domain *power_domain)
  163. {
  164. struct meson_gx_pwrc_vpu_priv *priv = dev_get_priv(power_domain->dev);
  165. int i;
  166. regmap_update_bits(priv->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
  167. GEN_PWR_VPU_HDMI_ISO, GEN_PWR_VPU_HDMI_ISO);
  168. udelay(20);
  169. /* Power Down Memories */
  170. for (i = 0; i < 32; i += 2) {
  171. regmap_update_bits(priv->regmap_hhi, HHI_VPU_MEM_PD_REG0,
  172. 0x3 << i, 0x3 << i);
  173. udelay(5);
  174. }
  175. for (i = 0; i < 32; i += 2) {
  176. regmap_update_bits(priv->regmap_hhi, HHI_VPU_MEM_PD_REG1,
  177. 0x3 << i, 0x3 << i);
  178. udelay(5);
  179. }
  180. for (i = 0; i < 32; i += 2) {
  181. regmap_update_bits(priv->regmap_hhi, HHI_VPU_MEM_PD_REG2,
  182. 0x3 << i, 0x3 << i);
  183. udelay(5);
  184. }
  185. for (i = 8; i < 16; i++) {
  186. regmap_update_bits(priv->regmap_hhi, HHI_MEM_PD_REG0,
  187. BIT(i), BIT(i));
  188. udelay(5);
  189. }
  190. udelay(20);
  191. regmap_update_bits(priv->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
  192. GEN_PWR_VPU_HDMI, GEN_PWR_VPU_HDMI);
  193. mdelay(20);
  194. clk_disable_bulk(&priv->clks);
  195. return 0;
  196. }
  197. static int meson_pwrc_vpu_off(struct power_domain *power_domain)
  198. {
  199. unsigned int compat = dev_get_driver_data(power_domain->dev);
  200. switch (compat) {
  201. case VPU_PWRC_COMPATIBLE_GX:
  202. return meson_gx_pwrc_vpu_off(power_domain);
  203. case VPU_PWRC_COMPATIBLE_G12A:
  204. return meson_g12a_pwrc_vpu_off(power_domain);
  205. }
  206. return -EINVAL;
  207. }
  208. static int meson_pwrc_vpu_of_xlate(struct power_domain *power_domain,
  209. struct ofnode_phandle_args *args)
  210. {
  211. /* #power-domain-cells is 0 */
  212. if (args->args_count != 0) {
  213. debug("Invalid args_count: %d\n", args->args_count);
  214. return -EINVAL;
  215. }
  216. return 0;
  217. }
  218. struct power_domain_ops meson_gx_pwrc_vpu_ops = {
  219. .rfree = meson_pwrc_vpu_free,
  220. .off = meson_pwrc_vpu_off,
  221. .on = meson_pwrc_vpu_on,
  222. .request = meson_pwrc_vpu_request,
  223. .of_xlate = meson_pwrc_vpu_of_xlate,
  224. };
  225. static const struct udevice_id meson_gx_pwrc_vpu_ids[] = {
  226. {
  227. .compatible = "amlogic,meson-gx-pwrc-vpu",
  228. .data = VPU_PWRC_COMPATIBLE_GX,
  229. },
  230. {
  231. .compatible = "amlogic,meson-g12a-pwrc-vpu",
  232. .data = VPU_PWRC_COMPATIBLE_G12A,
  233. },
  234. { }
  235. };
  236. static int meson_gx_pwrc_vpu_probe(struct udevice *dev)
  237. {
  238. struct meson_gx_pwrc_vpu_priv *priv = dev_get_priv(dev);
  239. u32 hhi_phandle;
  240. ofnode hhi_node;
  241. int ret;
  242. priv->regmap_ao = syscon_node_to_regmap(dev_get_parent(dev)->node);
  243. if (IS_ERR(priv->regmap_ao))
  244. return PTR_ERR(priv->regmap_ao);
  245. ret = ofnode_read_u32(dev->node, "amlogic,hhi-sysctrl",
  246. &hhi_phandle);
  247. if (ret)
  248. return ret;
  249. hhi_node = ofnode_get_by_phandle(hhi_phandle);
  250. if (!ofnode_valid(hhi_node))
  251. return -EINVAL;
  252. priv->regmap_hhi = syscon_node_to_regmap(hhi_node);
  253. if (IS_ERR(priv->regmap_hhi))
  254. return PTR_ERR(priv->regmap_hhi);
  255. ret = reset_get_bulk(dev, &priv->resets);
  256. if (ret)
  257. return ret;
  258. ret = clk_get_bulk(dev, &priv->clks);
  259. if (ret)
  260. return ret;
  261. return 0;
  262. }
  263. U_BOOT_DRIVER(meson_gx_pwrc_vpu) = {
  264. .name = "meson_gx_pwrc_vpu",
  265. .id = UCLASS_POWER_DOMAIN,
  266. .of_match = meson_gx_pwrc_vpu_ids,
  267. .probe = meson_gx_pwrc_vpu_probe,
  268. .ops = &meson_gx_pwrc_vpu_ops,
  269. .priv_auto_alloc_size = sizeof(struct meson_gx_pwrc_vpu_priv),
  270. };