meson-ee-pwrc.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2019 BayLibre, SAS
  4. * Author: Neil Armstrong <narmstrong@baylibre.com>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <power-domain-uclass.h>
  9. #include <regmap.h>
  10. #include <syscon.h>
  11. #include <reset.h>
  12. #include <clk.h>
  13. #include <dt-bindings/power/meson-g12a-power.h>
  14. #include <dt-bindings/power/meson-sm1-power.h>
  15. /* AO Offsets */
  16. #define AO_RTI_GEN_PWR_SLEEP0 (0x3a << 2)
  17. #define AO_RTI_GEN_PWR_ISO0 (0x3b << 2)
  18. /* HHI Offsets */
  19. #define HHI_MEM_PD_REG0 (0x40 << 2)
  20. #define HHI_VPU_MEM_PD_REG0 (0x41 << 2)
  21. #define HHI_VPU_MEM_PD_REG1 (0x42 << 2)
  22. #define HHI_VPU_MEM_PD_REG3 (0x43 << 2)
  23. #define HHI_VPU_MEM_PD_REG4 (0x44 << 2)
  24. #define HHI_AUDIO_MEM_PD_REG0 (0x45 << 2)
  25. #define HHI_NANOQ_MEM_PD_REG0 (0x46 << 2)
  26. #define HHI_NANOQ_MEM_PD_REG1 (0x47 << 2)
  27. #define HHI_VPU_MEM_PD_REG2 (0x4d << 2)
  28. struct meson_ee_pwrc;
  29. struct meson_ee_pwrc_domain;
  30. struct meson_ee_pwrc_mem_domain {
  31. unsigned int reg;
  32. unsigned int mask;
  33. };
  34. struct meson_ee_pwrc_top_domain {
  35. unsigned int sleep_reg;
  36. unsigned int sleep_mask;
  37. unsigned int iso_reg;
  38. unsigned int iso_mask;
  39. };
  40. struct meson_ee_pwrc_domain_desc {
  41. char *name;
  42. unsigned int reset_names_count;
  43. unsigned int clk_names_count;
  44. struct meson_ee_pwrc_top_domain *top_pd;
  45. unsigned int mem_pd_count;
  46. struct meson_ee_pwrc_mem_domain *mem_pd;
  47. bool (*get_power)(struct power_domain *power_domain);
  48. };
  49. struct meson_ee_pwrc_domain_data {
  50. unsigned int count;
  51. struct meson_ee_pwrc_domain_desc *domains;
  52. };
  53. /* TOP Power Domains */
  54. static struct meson_ee_pwrc_top_domain g12a_pwrc_vpu = {
  55. .sleep_reg = AO_RTI_GEN_PWR_SLEEP0,
  56. .sleep_mask = BIT(8),
  57. .iso_reg = AO_RTI_GEN_PWR_SLEEP0,
  58. .iso_mask = BIT(9),
  59. };
  60. #define SM1_EE_PD(__bit) \
  61. { \
  62. .sleep_reg = AO_RTI_GEN_PWR_SLEEP0, \
  63. .sleep_mask = BIT(__bit), \
  64. .iso_reg = AO_RTI_GEN_PWR_ISO0, \
  65. .iso_mask = BIT(__bit), \
  66. }
  67. static struct meson_ee_pwrc_top_domain sm1_pwrc_vpu = SM1_EE_PD(8);
  68. static struct meson_ee_pwrc_top_domain sm1_pwrc_nna = SM1_EE_PD(16);
  69. static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17);
  70. static struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18);
  71. static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19);
  72. /* Memory PD Domains */
  73. #define VPU_MEMPD(__reg) \
  74. { __reg, GENMASK(1, 0) }, \
  75. { __reg, GENMASK(3, 2) }, \
  76. { __reg, GENMASK(5, 4) }, \
  77. { __reg, GENMASK(7, 6) }, \
  78. { __reg, GENMASK(9, 8) }, \
  79. { __reg, GENMASK(11, 10) }, \
  80. { __reg, GENMASK(13, 12) }, \
  81. { __reg, GENMASK(15, 14) }, \
  82. { __reg, GENMASK(17, 16) }, \
  83. { __reg, GENMASK(19, 18) }, \
  84. { __reg, GENMASK(21, 20) }, \
  85. { __reg, GENMASK(23, 22) }, \
  86. { __reg, GENMASK(25, 24) }, \
  87. { __reg, GENMASK(27, 26) }, \
  88. { __reg, GENMASK(29, 28) }, \
  89. { __reg, GENMASK(31, 30) }
  90. #define VPU_HHI_MEMPD(__reg) \
  91. { __reg, BIT(8) }, \
  92. { __reg, BIT(9) }, \
  93. { __reg, BIT(10) }, \
  94. { __reg, BIT(11) }, \
  95. { __reg, BIT(12) }, \
  96. { __reg, BIT(13) }, \
  97. { __reg, BIT(14) }, \
  98. { __reg, BIT(15) }
  99. static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_vpu[] = {
  100. VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
  101. VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
  102. VPU_MEMPD(HHI_VPU_MEM_PD_REG2),
  103. VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
  104. };
  105. static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_eth[] = {
  106. { HHI_MEM_PD_REG0, GENMASK(3, 2) },
  107. };
  108. static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_vpu[] = {
  109. VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
  110. VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
  111. VPU_MEMPD(HHI_VPU_MEM_PD_REG2),
  112. VPU_MEMPD(HHI_VPU_MEM_PD_REG3),
  113. { HHI_VPU_MEM_PD_REG4, GENMASK(1, 0) },
  114. { HHI_VPU_MEM_PD_REG4, GENMASK(3, 2) },
  115. { HHI_VPU_MEM_PD_REG4, GENMASK(5, 4) },
  116. { HHI_VPU_MEM_PD_REG4, GENMASK(7, 6) },
  117. VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
  118. };
  119. static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_nna[] = {
  120. { HHI_NANOQ_MEM_PD_REG0, 0xff },
  121. { HHI_NANOQ_MEM_PD_REG1, 0xff },
  122. };
  123. static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_usb[] = {
  124. { HHI_MEM_PD_REG0, GENMASK(31, 30) },
  125. };
  126. static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_pcie[] = {
  127. { HHI_MEM_PD_REG0, GENMASK(29, 26) },
  128. };
  129. static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_ge2d[] = {
  130. { HHI_MEM_PD_REG0, GENMASK(25, 18) },
  131. };
  132. static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = {
  133. { HHI_MEM_PD_REG0, GENMASK(5, 4) },
  134. { HHI_AUDIO_MEM_PD_REG0, GENMASK(1, 0) },
  135. { HHI_AUDIO_MEM_PD_REG0, GENMASK(3, 2) },
  136. { HHI_AUDIO_MEM_PD_REG0, GENMASK(5, 4) },
  137. { HHI_AUDIO_MEM_PD_REG0, GENMASK(7, 6) },
  138. { HHI_AUDIO_MEM_PD_REG0, GENMASK(13, 12) },
  139. { HHI_AUDIO_MEM_PD_REG0, GENMASK(15, 14) },
  140. { HHI_AUDIO_MEM_PD_REG0, GENMASK(17, 16) },
  141. { HHI_AUDIO_MEM_PD_REG0, GENMASK(19, 18) },
  142. { HHI_AUDIO_MEM_PD_REG0, GENMASK(21, 20) },
  143. { HHI_AUDIO_MEM_PD_REG0, GENMASK(23, 22) },
  144. { HHI_AUDIO_MEM_PD_REG0, GENMASK(25, 24) },
  145. { HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) },
  146. };
  147. #define VPU_PD(__name, __top_pd, __mem, __get_power, __resets, __clks) \
  148. { \
  149. .name = __name, \
  150. .reset_names_count = __resets, \
  151. .clk_names_count = __clks, \
  152. .top_pd = __top_pd, \
  153. .mem_pd_count = ARRAY_SIZE(__mem), \
  154. .mem_pd = __mem, \
  155. .get_power = __get_power, \
  156. }
  157. #define TOP_PD(__name, __top_pd, __mem, __get_power) \
  158. { \
  159. .name = __name, \
  160. .top_pd = __top_pd, \
  161. .mem_pd_count = ARRAY_SIZE(__mem), \
  162. .mem_pd = __mem, \
  163. .get_power = __get_power, \
  164. }
  165. #define MEM_PD(__name, __mem) \
  166. TOP_PD(__name, NULL, __mem, NULL)
  167. static bool pwrc_ee_get_power(struct power_domain *power_domain);
  168. static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = {
  169. [PWRC_G12A_VPU_ID] = VPU_PD("VPU", &g12a_pwrc_vpu, g12a_pwrc_mem_vpu,
  170. pwrc_ee_get_power, 11, 2),
  171. [PWRC_G12A_ETH_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth),
  172. };
  173. static struct meson_ee_pwrc_domain_desc sm1_pwrc_domains[] = {
  174. [PWRC_SM1_VPU_ID] = VPU_PD("VPU", &sm1_pwrc_vpu, sm1_pwrc_mem_vpu,
  175. pwrc_ee_get_power, 11, 2),
  176. [PWRC_SM1_NNA_ID] = TOP_PD("NNA", &sm1_pwrc_nna, sm1_pwrc_mem_nna,
  177. pwrc_ee_get_power),
  178. [PWRC_SM1_USB_ID] = TOP_PD("USB", &sm1_pwrc_usb, sm1_pwrc_mem_usb,
  179. pwrc_ee_get_power),
  180. [PWRC_SM1_PCIE_ID] = TOP_PD("PCI", &sm1_pwrc_pci, sm1_pwrc_mem_pcie,
  181. pwrc_ee_get_power),
  182. [PWRC_SM1_GE2D_ID] = TOP_PD("GE2D", &sm1_pwrc_ge2d, sm1_pwrc_mem_ge2d,
  183. pwrc_ee_get_power),
  184. [PWRC_SM1_AUDIO_ID] = MEM_PD("AUDIO", sm1_pwrc_mem_audio),
  185. [PWRC_SM1_ETH_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth),
  186. };
  187. struct meson_ee_pwrc_priv {
  188. struct regmap *regmap_ao;
  189. struct regmap *regmap_hhi;
  190. struct reset_ctl_bulk resets;
  191. struct clk_bulk clks;
  192. const struct meson_ee_pwrc_domain_data *data;
  193. };
  194. static bool pwrc_ee_get_power(struct power_domain *power_domain)
  195. {
  196. struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
  197. struct meson_ee_pwrc_domain_desc *pwrc_domain;
  198. u32 reg;
  199. pwrc_domain = &priv->data->domains[power_domain->id];
  200. regmap_read(priv->regmap_ao,
  201. pwrc_domain->top_pd->sleep_reg, &reg);
  202. return (reg & pwrc_domain->top_pd->sleep_mask);
  203. }
  204. static int meson_ee_pwrc_request(struct power_domain *power_domain)
  205. {
  206. return 0;
  207. }
  208. static int meson_ee_pwrc_free(struct power_domain *power_domain)
  209. {
  210. return 0;
  211. }
  212. static int meson_ee_pwrc_off(struct power_domain *power_domain)
  213. {
  214. struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
  215. struct meson_ee_pwrc_domain_desc *pwrc_domain;
  216. int i;
  217. pwrc_domain = &priv->data->domains[power_domain->id];
  218. if (pwrc_domain->top_pd)
  219. regmap_update_bits(priv->regmap_ao,
  220. pwrc_domain->top_pd->sleep_reg,
  221. pwrc_domain->top_pd->sleep_mask,
  222. pwrc_domain->top_pd->sleep_mask);
  223. udelay(20);
  224. for (i = 0 ; i < pwrc_domain->mem_pd_count ; ++i)
  225. regmap_update_bits(priv->regmap_hhi,
  226. pwrc_domain->mem_pd[i].reg,
  227. pwrc_domain->mem_pd[i].mask,
  228. pwrc_domain->mem_pd[i].mask);
  229. udelay(20);
  230. if (pwrc_domain->top_pd)
  231. regmap_update_bits(priv->regmap_ao,
  232. pwrc_domain->top_pd->iso_reg,
  233. pwrc_domain->top_pd->iso_mask,
  234. pwrc_domain->top_pd->iso_mask);
  235. if (pwrc_domain->clk_names_count) {
  236. mdelay(20);
  237. clk_disable_bulk(&priv->clks);
  238. }
  239. return 0;
  240. }
  241. static int meson_ee_pwrc_on(struct power_domain *power_domain)
  242. {
  243. struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
  244. struct meson_ee_pwrc_domain_desc *pwrc_domain;
  245. int i, ret;
  246. pwrc_domain = &priv->data->domains[power_domain->id];
  247. if (pwrc_domain->top_pd)
  248. regmap_update_bits(priv->regmap_ao,
  249. pwrc_domain->top_pd->sleep_reg,
  250. pwrc_domain->top_pd->sleep_mask, 0);
  251. udelay(20);
  252. for (i = 0 ; i < pwrc_domain->mem_pd_count ; ++i)
  253. regmap_update_bits(priv->regmap_hhi,
  254. pwrc_domain->mem_pd[i].reg,
  255. pwrc_domain->mem_pd[i].mask, 0);
  256. udelay(20);
  257. if (pwrc_domain->reset_names_count) {
  258. ret = reset_assert_bulk(&priv->resets);
  259. if (ret)
  260. return ret;
  261. }
  262. if (pwrc_domain->top_pd)
  263. regmap_update_bits(priv->regmap_ao,
  264. pwrc_domain->top_pd->iso_reg,
  265. pwrc_domain->top_pd->iso_mask, 0);
  266. if (pwrc_domain->reset_names_count) {
  267. ret = reset_deassert_bulk(&priv->resets);
  268. if (ret)
  269. return ret;
  270. }
  271. if (pwrc_domain->clk_names_count)
  272. return clk_enable_bulk(&priv->clks);
  273. return 0;
  274. }
  275. static int meson_ee_pwrc_of_xlate(struct power_domain *power_domain,
  276. struct ofnode_phandle_args *args)
  277. {
  278. struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
  279. /* #power-domain-cells is 1 */
  280. if (args->args_count < 1) {
  281. debug("Invalid args_count: %d\n", args->args_count);
  282. return -EINVAL;
  283. }
  284. power_domain->id = args->args[0];
  285. if (power_domain->id >= priv->data->count) {
  286. debug("Invalid domain ID: %lu\n", power_domain->id);
  287. return -EINVAL;
  288. }
  289. return 0;
  290. }
  291. struct power_domain_ops meson_ee_pwrc_ops = {
  292. .rfree = meson_ee_pwrc_free,
  293. .off = meson_ee_pwrc_off,
  294. .on = meson_ee_pwrc_on,
  295. .request = meson_ee_pwrc_request,
  296. .of_xlate = meson_ee_pwrc_of_xlate,
  297. };
  298. static struct meson_ee_pwrc_domain_data meson_ee_g12a_pwrc_data = {
  299. .count = ARRAY_SIZE(g12a_pwrc_domains),
  300. .domains = g12a_pwrc_domains,
  301. };
  302. static struct meson_ee_pwrc_domain_data meson_ee_sm1_pwrc_data = {
  303. .count = ARRAY_SIZE(sm1_pwrc_domains),
  304. .domains = sm1_pwrc_domains,
  305. };
  306. static const struct udevice_id meson_ee_pwrc_ids[] = {
  307. {
  308. .compatible = "amlogic,meson-g12a-pwrc",
  309. .data = (unsigned long)&meson_ee_g12a_pwrc_data,
  310. },
  311. {
  312. .compatible = "amlogic,meson-sm1-pwrc",
  313. .data = (unsigned long)&meson_ee_sm1_pwrc_data,
  314. },
  315. { }
  316. };
  317. static int meson_ee_pwrc_probe(struct udevice *dev)
  318. {
  319. struct meson_ee_pwrc_priv *priv = dev_get_priv(dev);
  320. u32 ao_phandle;
  321. ofnode ao_node;
  322. int ret;
  323. priv->data = (void *)dev_get_driver_data(dev);
  324. if (!priv->data)
  325. return -EINVAL;
  326. priv->regmap_hhi = syscon_node_to_regmap(dev_get_parent(dev)->node);
  327. if (IS_ERR(priv->regmap_hhi))
  328. return PTR_ERR(priv->regmap_hhi);
  329. ret = ofnode_read_u32(dev->node, "amlogic,ao-sysctrl",
  330. &ao_phandle);
  331. if (ret)
  332. return ret;
  333. ao_node = ofnode_get_by_phandle(ao_phandle);
  334. if (!ofnode_valid(ao_node))
  335. return -EINVAL;
  336. priv->regmap_ao = syscon_node_to_regmap(ao_node);
  337. if (IS_ERR(priv->regmap_ao))
  338. return PTR_ERR(priv->regmap_ao);
  339. ret = reset_get_bulk(dev, &priv->resets);
  340. if (ret)
  341. return ret;
  342. ret = clk_get_bulk(dev, &priv->clks);
  343. if (ret)
  344. return ret;
  345. return 0;
  346. }
  347. U_BOOT_DRIVER(meson_ee_pwrc) = {
  348. .name = "meson_ee_pwrc",
  349. .id = UCLASS_POWER_DOMAIN,
  350. .of_match = meson_ee_pwrc_ids,
  351. .probe = meson_ee_pwrc_probe,
  352. .ops = &meson_ee_pwrc_ops,
  353. .priv_auto_alloc_size = sizeof(struct meson_ee_pwrc_priv),
  354. };