mxc_gpio.c 8.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2009
  4. * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
  5. *
  6. * Copyright (C) 2011
  7. * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
  8. */
  9. #include <common.h>
  10. #include <errno.h>
  11. #include <dm.h>
  12. #include <malloc.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <asm/gpio.h>
  15. #include <asm/io.h>
  16. enum mxc_gpio_direction {
  17. MXC_GPIO_DIRECTION_IN,
  18. MXC_GPIO_DIRECTION_OUT,
  19. };
  20. #define GPIO_PER_BANK 32
  21. struct mxc_gpio_plat {
  22. int bank_index;
  23. struct gpio_regs *regs;
  24. };
  25. struct mxc_bank_info {
  26. struct gpio_regs *regs;
  27. };
  28. #if !CONFIG_IS_ENABLED(DM_GPIO)
  29. #define GPIO_TO_PORT(n) ((n) / 32)
  30. /* GPIO port description */
  31. static unsigned long gpio_ports[] = {
  32. [0] = GPIO1_BASE_ADDR,
  33. [1] = GPIO2_BASE_ADDR,
  34. [2] = GPIO3_BASE_ADDR,
  35. #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
  36. defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
  37. defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
  38. defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050)
  39. [3] = GPIO4_BASE_ADDR,
  40. #endif
  41. #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
  42. defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
  43. defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050)
  44. [4] = GPIO5_BASE_ADDR,
  45. #if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
  46. defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT1050))
  47. [5] = GPIO6_BASE_ADDR,
  48. #endif
  49. #endif
  50. #if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
  51. defined(CONFIG_ARCH_IMX8)
  52. #if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
  53. [6] = GPIO7_BASE_ADDR,
  54. #endif
  55. #endif
  56. #if defined(CONFIG_ARCH_IMX8)
  57. [7] = GPIO8_BASE_ADDR,
  58. #endif
  59. };
  60. static int mxc_gpio_direction(unsigned int gpio,
  61. enum mxc_gpio_direction direction)
  62. {
  63. unsigned int port = GPIO_TO_PORT(gpio);
  64. struct gpio_regs *regs;
  65. u32 l;
  66. if (port >= ARRAY_SIZE(gpio_ports))
  67. return -1;
  68. gpio &= 0x1f;
  69. regs = (struct gpio_regs *)gpio_ports[port];
  70. l = readl(&regs->gpio_dir);
  71. switch (direction) {
  72. case MXC_GPIO_DIRECTION_OUT:
  73. l |= 1 << gpio;
  74. break;
  75. case MXC_GPIO_DIRECTION_IN:
  76. l &= ~(1 << gpio);
  77. }
  78. writel(l, &regs->gpio_dir);
  79. return 0;
  80. }
  81. int gpio_set_value(unsigned gpio, int value)
  82. {
  83. unsigned int port = GPIO_TO_PORT(gpio);
  84. struct gpio_regs *regs;
  85. u32 l;
  86. if (port >= ARRAY_SIZE(gpio_ports))
  87. return -1;
  88. gpio &= 0x1f;
  89. regs = (struct gpio_regs *)gpio_ports[port];
  90. l = readl(&regs->gpio_dr);
  91. if (value)
  92. l |= 1 << gpio;
  93. else
  94. l &= ~(1 << gpio);
  95. writel(l, &regs->gpio_dr);
  96. return 0;
  97. }
  98. int gpio_get_value(unsigned gpio)
  99. {
  100. unsigned int port = GPIO_TO_PORT(gpio);
  101. struct gpio_regs *regs;
  102. u32 val;
  103. if (port >= ARRAY_SIZE(gpio_ports))
  104. return -1;
  105. gpio &= 0x1f;
  106. regs = (struct gpio_regs *)gpio_ports[port];
  107. val = (readl(&regs->gpio_psr) >> gpio) & 0x01;
  108. return val;
  109. }
  110. int gpio_request(unsigned gpio, const char *label)
  111. {
  112. unsigned int port = GPIO_TO_PORT(gpio);
  113. if (port >= ARRAY_SIZE(gpio_ports))
  114. return -1;
  115. return 0;
  116. }
  117. int gpio_free(unsigned gpio)
  118. {
  119. return 0;
  120. }
  121. int gpio_direction_input(unsigned gpio)
  122. {
  123. return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_IN);
  124. }
  125. int gpio_direction_output(unsigned gpio, int value)
  126. {
  127. int ret = gpio_set_value(gpio, value);
  128. if (ret < 0)
  129. return ret;
  130. return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT);
  131. }
  132. #endif
  133. #if CONFIG_IS_ENABLED(DM_GPIO)
  134. #include <fdtdec.h>
  135. static int mxc_gpio_is_output(struct gpio_regs *regs, int offset)
  136. {
  137. u32 val;
  138. val = readl(&regs->gpio_dir);
  139. return val & (1 << offset) ? 1 : 0;
  140. }
  141. static void mxc_gpio_bank_direction(struct gpio_regs *regs, int offset,
  142. enum mxc_gpio_direction direction)
  143. {
  144. u32 l;
  145. l = readl(&regs->gpio_dir);
  146. switch (direction) {
  147. case MXC_GPIO_DIRECTION_OUT:
  148. l |= 1 << offset;
  149. break;
  150. case MXC_GPIO_DIRECTION_IN:
  151. l &= ~(1 << offset);
  152. }
  153. writel(l, &regs->gpio_dir);
  154. }
  155. static void mxc_gpio_bank_set_value(struct gpio_regs *regs, int offset,
  156. int value)
  157. {
  158. u32 l;
  159. l = readl(&regs->gpio_dr);
  160. if (value)
  161. l |= 1 << offset;
  162. else
  163. l &= ~(1 << offset);
  164. writel(l, &regs->gpio_dr);
  165. }
  166. static int mxc_gpio_bank_get_value(struct gpio_regs *regs, int offset)
  167. {
  168. return (readl(&regs->gpio_psr) >> offset) & 0x01;
  169. }
  170. /* set GPIO pin 'gpio' as an input */
  171. static int mxc_gpio_direction_input(struct udevice *dev, unsigned offset)
  172. {
  173. struct mxc_bank_info *bank = dev_get_priv(dev);
  174. /* Configure GPIO direction as input. */
  175. mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_IN);
  176. return 0;
  177. }
  178. /* set GPIO pin 'gpio' as an output, with polarity 'value' */
  179. static int mxc_gpio_direction_output(struct udevice *dev, unsigned offset,
  180. int value)
  181. {
  182. struct mxc_bank_info *bank = dev_get_priv(dev);
  183. /* Configure GPIO output value. */
  184. mxc_gpio_bank_set_value(bank->regs, offset, value);
  185. /* Configure GPIO direction as output. */
  186. mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_OUT);
  187. return 0;
  188. }
  189. /* read GPIO IN value of pin 'gpio' */
  190. static int mxc_gpio_get_value(struct udevice *dev, unsigned offset)
  191. {
  192. struct mxc_bank_info *bank = dev_get_priv(dev);
  193. return mxc_gpio_bank_get_value(bank->regs, offset);
  194. }
  195. /* write GPIO OUT value to pin 'gpio' */
  196. static int mxc_gpio_set_value(struct udevice *dev, unsigned offset,
  197. int value)
  198. {
  199. struct mxc_bank_info *bank = dev_get_priv(dev);
  200. mxc_gpio_bank_set_value(bank->regs, offset, value);
  201. return 0;
  202. }
  203. static int mxc_gpio_get_function(struct udevice *dev, unsigned offset)
  204. {
  205. struct mxc_bank_info *bank = dev_get_priv(dev);
  206. /* GPIOF_FUNC is not implemented yet */
  207. if (mxc_gpio_is_output(bank->regs, offset))
  208. return GPIOF_OUTPUT;
  209. else
  210. return GPIOF_INPUT;
  211. }
  212. static const struct dm_gpio_ops gpio_mxc_ops = {
  213. .direction_input = mxc_gpio_direction_input,
  214. .direction_output = mxc_gpio_direction_output,
  215. .get_value = mxc_gpio_get_value,
  216. .set_value = mxc_gpio_set_value,
  217. .get_function = mxc_gpio_get_function,
  218. };
  219. static int mxc_gpio_probe(struct udevice *dev)
  220. {
  221. struct mxc_bank_info *bank = dev_get_priv(dev);
  222. struct mxc_gpio_plat *plat = dev_get_platdata(dev);
  223. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  224. int banknum;
  225. char name[18], *str;
  226. banknum = plat->bank_index;
  227. if (IS_ENABLED(CONFIG_ARCH_IMX8))
  228. sprintf(name, "GPIO%d_", banknum);
  229. else
  230. sprintf(name, "GPIO%d_", banknum + 1);
  231. str = strdup(name);
  232. if (!str)
  233. return -ENOMEM;
  234. uc_priv->bank_name = str;
  235. uc_priv->gpio_count = GPIO_PER_BANK;
  236. bank->regs = plat->regs;
  237. return 0;
  238. }
  239. static int mxc_gpio_ofdata_to_platdata(struct udevice *dev)
  240. {
  241. fdt_addr_t addr;
  242. struct mxc_gpio_plat *plat = dev_get_platdata(dev);
  243. addr = dev_read_addr(dev);
  244. if (addr == FDT_ADDR_T_NONE)
  245. return -EINVAL;
  246. plat->regs = (struct gpio_regs *)addr;
  247. plat->bank_index = dev->req_seq;
  248. return 0;
  249. }
  250. static int mxc_gpio_bind(struct udevice *dev)
  251. {
  252. return 0;
  253. }
  254. static const struct udevice_id mxc_gpio_ids[] = {
  255. { .compatible = "fsl,imx35-gpio" },
  256. { }
  257. };
  258. U_BOOT_DRIVER(gpio_mxc) = {
  259. .name = "gpio_mxc",
  260. .id = UCLASS_GPIO,
  261. .ops = &gpio_mxc_ops,
  262. .probe = mxc_gpio_probe,
  263. .ofdata_to_platdata = mxc_gpio_ofdata_to_platdata,
  264. .platdata_auto_alloc_size = sizeof(struct mxc_gpio_plat),
  265. .priv_auto_alloc_size = sizeof(struct mxc_bank_info),
  266. .of_match = mxc_gpio_ids,
  267. .bind = mxc_gpio_bind,
  268. };
  269. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  270. static const struct mxc_gpio_plat mxc_plat[] = {
  271. { 0, (struct gpio_regs *)GPIO1_BASE_ADDR },
  272. { 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
  273. { 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
  274. #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
  275. defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
  276. defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
  277. { 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
  278. #endif
  279. #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
  280. defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
  281. { 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
  282. #ifndef CONFIG_IMX8M
  283. { 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
  284. #endif
  285. #endif
  286. #if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_ARCH_IMX8)
  287. { 6, (struct gpio_regs *)GPIO7_BASE_ADDR },
  288. #endif
  289. #if defined(CONFIG_ARCH_IMX8)
  290. { 7, (struct gpio_regs *)GPIO8_BASE_ADDR },
  291. #endif
  292. };
  293. U_BOOT_DEVICES(mxc_gpios) = {
  294. { "gpio_mxc", &mxc_plat[0] },
  295. { "gpio_mxc", &mxc_plat[1] },
  296. { "gpio_mxc", &mxc_plat[2] },
  297. #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
  298. defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
  299. defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
  300. { "gpio_mxc", &mxc_plat[3] },
  301. #endif
  302. #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
  303. defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
  304. { "gpio_mxc", &mxc_plat[4] },
  305. #ifndef CONFIG_IMX8M
  306. { "gpio_mxc", &mxc_plat[5] },
  307. #endif
  308. #endif
  309. #if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_ARCH_IMX8)
  310. { "gpio_mxc", &mxc_plat[6] },
  311. #endif
  312. #if defined(CONFIG_ARCH_IMX8)
  313. { "gpio_mxc", &mxc_plat[7] },
  314. #endif
  315. };
  316. #endif
  317. #endif