cpu.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Google, Inc
  4. *
  5. * Based on code from coreboot
  6. */
  7. #include <common.h>
  8. #include <cpu.h>
  9. #include <dm.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <pci.h>
  13. #include <asm/cpu.h>
  14. #include <asm/cpu_x86.h>
  15. #include <asm/io.h>
  16. #include <asm/lapic.h>
  17. #include <asm/msr.h>
  18. #include <asm/turbo.h>
  19. #define BYT_PRV_CLK 0x800
  20. #define BYT_PRV_CLK_EN (1 << 0)
  21. #define BYT_PRV_CLK_M_VAL_SHIFT 1
  22. #define BYT_PRV_CLK_N_VAL_SHIFT 16
  23. #define BYT_PRV_CLK_UPDATE (1 << 31)
  24. static void hsuart_clock_set(void *base)
  25. {
  26. u32 m, n, reg;
  27. /*
  28. * Configure the BayTrail UART clock for the internal HS UARTs
  29. * (PCI devices) to 58982400 Hz
  30. */
  31. m = 0x2400;
  32. n = 0x3d09;
  33. reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
  34. writel(reg, base + BYT_PRV_CLK);
  35. reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
  36. writel(reg, base + BYT_PRV_CLK);
  37. }
  38. /*
  39. * Configure the internal clock of both SIO HS-UARTs, if they are enabled
  40. * via FSP
  41. */
  42. int arch_cpu_init_dm(void)
  43. {
  44. struct udevice *dev;
  45. void *base;
  46. int ret;
  47. int i;
  48. /* Loop over the 2 HS-UARTs */
  49. for (i = 0; i < 2; i++) {
  50. ret = dm_pci_bus_find_bdf(PCI_BDF(0, 0x1e, 3 + i), &dev);
  51. if (!ret) {
  52. base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0,
  53. PCI_REGION_MEM);
  54. hsuart_clock_set(base);
  55. }
  56. }
  57. return 0;
  58. }
  59. static void set_max_freq(void)
  60. {
  61. msr_t perf_ctl;
  62. msr_t msr;
  63. /* Enable speed step */
  64. msr = msr_read(MSR_IA32_MISC_ENABLE);
  65. msr.lo |= MISC_ENABLE_ENHANCED_SPEEDSTEP;
  66. msr_write(MSR_IA32_MISC_ENABLE, msr);
  67. /*
  68. * Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of
  69. * the PERF_CTL
  70. */
  71. msr = msr_read(MSR_IACORE_RATIOS);
  72. perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;
  73. /*
  74. * Set guaranteed vid [22:16] from IACORE_VIDS to bits [7:0] of
  75. * the PERF_CTL
  76. */
  77. msr = msr_read(MSR_IACORE_VIDS);
  78. perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;
  79. perf_ctl.hi = 0;
  80. msr_write(MSR_IA32_PERF_CTL, perf_ctl);
  81. }
  82. static int cpu_x86_baytrail_probe(struct udevice *dev)
  83. {
  84. if (!ll_boot_init())
  85. return 0;
  86. debug("Init BayTrail core\n");
  87. /*
  88. * On BayTrail the turbo disable bit is actually scoped at the
  89. * building-block level, not package. For non-BSP cores that are
  90. * within a building block, enable turbo. The cores within the BSP's
  91. * building block will just see it already enabled and move on.
  92. */
  93. if (lapicid())
  94. turbo_enable();
  95. /* Dynamic L2 shrink enable and threshold */
  96. msr_clrsetbits_64(MSR_PMG_CST_CONFIG_CONTROL, 0x3f000f, 0xe0008),
  97. /* Disable C1E */
  98. msr_clrsetbits_64(MSR_POWER_CTL, 2, 0);
  99. msr_setbits_64(MSR_POWER_MISC, 0x44);
  100. /* Set this core to max frequency ratio */
  101. set_max_freq();
  102. return 0;
  103. }
  104. static unsigned bus_freq(void)
  105. {
  106. msr_t clk_info = msr_read(MSR_BSEL_CR_OVERCLOCK_CONTROL);
  107. switch (clk_info.lo & 0x3) {
  108. case 0:
  109. return 83333333;
  110. case 1:
  111. return 100000000;
  112. case 2:
  113. return 133333333;
  114. case 3:
  115. return 116666666;
  116. default:
  117. return 0;
  118. }
  119. }
  120. static unsigned long tsc_freq(void)
  121. {
  122. msr_t platform_info;
  123. ulong bclk = bus_freq();
  124. if (!bclk)
  125. return 0;
  126. platform_info = msr_read(MSR_PLATFORM_INFO);
  127. return bclk * ((platform_info.lo >> 8) & 0xff);
  128. }
  129. static int baytrail_get_info(const struct udevice *dev, struct cpu_info *info)
  130. {
  131. info->cpu_freq = tsc_freq();
  132. info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU;
  133. return 0;
  134. }
  135. static int baytrail_get_count(const struct udevice *dev)
  136. {
  137. int ecx = 0;
  138. /*
  139. * Use the algorithm described in Intel 64 and IA-32 Architectures
  140. * Software Developer's Manual Volume 3 (3A, 3B & 3C): System
  141. * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping
  142. * of CPUID Extended Topology Leaf.
  143. */
  144. while (1) {
  145. struct cpuid_result leaf_b;
  146. leaf_b = cpuid_ext(0xb, ecx);
  147. /*
  148. * Bay Trail doesn't have hyperthreading so just determine the
  149. * number of cores by from level type (ecx[15:8] == * 2)
  150. */
  151. if ((leaf_b.ecx & 0xff00) == 0x0200)
  152. return leaf_b.ebx & 0xffff;
  153. ecx++;
  154. }
  155. return 0;
  156. }
  157. static const struct cpu_ops cpu_x86_baytrail_ops = {
  158. .get_desc = cpu_x86_get_desc,
  159. .get_info = baytrail_get_info,
  160. .get_count = baytrail_get_count,
  161. .get_vendor = cpu_x86_get_vendor,
  162. };
  163. static const struct udevice_id cpu_x86_baytrail_ids[] = {
  164. { .compatible = "intel,baytrail-cpu" },
  165. { }
  166. };
  167. U_BOOT_DRIVER(cpu_x86_baytrail_drv) = {
  168. .name = "cpu_x86_baytrail",
  169. .id = UCLASS_CPU,
  170. .of_match = cpu_x86_baytrail_ids,
  171. .bind = cpu_x86_bind,
  172. .probe = cpu_x86_baytrail_probe,
  173. .ops = &cpu_x86_baytrail_ops,
  174. .flags = DM_FLAG_PRE_RELOC,
  175. };