bx50v3.c 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 Timesys Corporation
  4. * Copyright 2015 General Electric Company
  5. * Copyright 2012 Freescale Semiconductor, Inc.
  6. */
  7. #include <image.h>
  8. #include <init.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/iomux.h>
  12. #include <asm/arch/mx6-pins.h>
  13. #include <env.h>
  14. #include <linux/errno.h>
  15. #include <linux/libfdt.h>
  16. #include <asm/gpio.h>
  17. #include <asm/mach-imx/iomux-v3.h>
  18. #include <asm/mach-imx/boot_mode.h>
  19. #include <asm/mach-imx/video.h>
  20. #include <mmc.h>
  21. #include <fsl_esdhc_imx.h>
  22. #include <miiphy.h>
  23. #include <net.h>
  24. #include <netdev.h>
  25. #include <asm/arch/mxc_hdmi.h>
  26. #include <asm/arch/crm_regs.h>
  27. #include <asm/io.h>
  28. #include <asm/arch/sys_proto.h>
  29. #include <power/regulator.h>
  30. #include <power/da9063_pmic.h>
  31. #include <input.h>
  32. #include <pwm.h>
  33. #include <version.h>
  34. #include <stdlib.h>
  35. #include <dm/root.h>
  36. #include "../common/ge_common.h"
  37. #include "../common/vpd_reader.h"
  38. #include "../../../drivers/net/e1000.h"
  39. #include <pci.h>
  40. #include <panel.h>
  41. DECLARE_GLOBAL_DATA_PTR;
  42. static int confidx; /* Default to generic. */
  43. static struct vpd_cache vpd;
  44. #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  45. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  46. PAD_CTL_HYS)
  47. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  48. PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  49. #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  50. PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  51. #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  52. PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
  53. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  54. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  55. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  56. #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  57. int dram_init(void)
  58. {
  59. gd->ram_size = imx_ddr_size();
  60. return 0;
  61. }
  62. static int mx6_rgmii_rework(struct phy_device *phydev)
  63. {
  64. /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
  65. /* set device address 0x7 */
  66. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  67. /* offset 0x8016: CLK_25M Clock Select */
  68. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  69. /* enable register write, no post increment, address 0x7 */
  70. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  71. /* set to 125 MHz from local PLL source */
  72. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
  73. /* rgmii tx clock delay enable */
  74. /* set debug port address: SerDes Test and System Mode Control */
  75. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  76. /* enable rgmii tx clock delay */
  77. /* set the reserved bits to avoid board specific voltage peak issue*/
  78. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
  79. return 0;
  80. }
  81. int board_phy_config(struct phy_device *phydev)
  82. {
  83. mx6_rgmii_rework(phydev);
  84. if (phydev->drv->config)
  85. phydev->drv->config(phydev);
  86. return 0;
  87. }
  88. #if defined(CONFIG_VIDEO_IPUV3)
  89. static void do_enable_backlight(struct display_info_t const *dev)
  90. {
  91. struct udevice *panel;
  92. int ret;
  93. ret = uclass_get_device(UCLASS_PANEL, 0, &panel);
  94. if (ret) {
  95. printf("Could not find panel: %d\n", ret);
  96. return;
  97. }
  98. panel_set_backlight(panel, 100);
  99. panel_enable_backlight(panel);
  100. }
  101. static void do_enable_hdmi(struct display_info_t const *dev)
  102. {
  103. imx_enable_hdmi_phy();
  104. }
  105. static int is_b850v3(void)
  106. {
  107. return confidx == 3;
  108. }
  109. static int detect_lcd(struct display_info_t const *dev)
  110. {
  111. return !is_b850v3();
  112. }
  113. struct display_info_t const displays[] = {{
  114. .bus = -1,
  115. .addr = -1,
  116. .pixfmt = IPU_PIX_FMT_RGB24,
  117. .detect = detect_lcd,
  118. .enable = do_enable_backlight,
  119. .mode = {
  120. .name = "G121X1-L03",
  121. .refresh = 60,
  122. .xres = 1024,
  123. .yres = 768,
  124. .pixclock = 15385,
  125. .left_margin = 20,
  126. .right_margin = 300,
  127. .upper_margin = 30,
  128. .lower_margin = 8,
  129. .hsync_len = 1,
  130. .vsync_len = 1,
  131. .sync = FB_SYNC_EXT,
  132. .vmode = FB_VMODE_NONINTERLACED
  133. } }, {
  134. .bus = -1,
  135. .addr = 3,
  136. .pixfmt = IPU_PIX_FMT_RGB24,
  137. .detect = detect_hdmi,
  138. .enable = do_enable_hdmi,
  139. .mode = {
  140. .name = "HDMI",
  141. .refresh = 60,
  142. .xres = 1024,
  143. .yres = 768,
  144. .pixclock = 15385,
  145. .left_margin = 220,
  146. .right_margin = 40,
  147. .upper_margin = 21,
  148. .lower_margin = 7,
  149. .hsync_len = 60,
  150. .vsync_len = 10,
  151. .sync = FB_SYNC_EXT,
  152. .vmode = FB_VMODE_NONINTERLACED
  153. } } };
  154. size_t display_count = ARRAY_SIZE(displays);
  155. static void enable_videopll(void)
  156. {
  157. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  158. s32 timeout = 100000;
  159. setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
  160. /* PLL_VIDEO 455MHz (24MHz * (37+11/12) / 2)
  161. * |
  162. * PLL5
  163. * |
  164. * CS2CDR[LDB_DI0_CLK_SEL]
  165. * |
  166. * +----> LDB_DI0_SERIAL_CLK_ROOT
  167. * |
  168. * +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU 455 / 7 = 65 MHz
  169. */
  170. clrsetbits_le32(&ccm->analog_pll_video,
  171. BM_ANADIG_PLL_VIDEO_DIV_SELECT |
  172. BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
  173. BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
  174. BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
  175. writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
  176. writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
  177. clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
  178. while (timeout--)
  179. if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
  180. break;
  181. if (timeout < 0)
  182. printf("Warning: video pll lock timeout!\n");
  183. clrsetbits_le32(&ccm->analog_pll_video,
  184. BM_ANADIG_PLL_VIDEO_BYPASS,
  185. BM_ANADIG_PLL_VIDEO_ENABLE);
  186. }
  187. static void setup_display_b850v3(void)
  188. {
  189. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  190. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  191. enable_videopll();
  192. /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
  193. setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
  194. imx_setup_hdmi();
  195. /* Set LDB_DI0 as clock source for IPU_DI0 */
  196. clrsetbits_le32(&mxc_ccm->chsccdr,
  197. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
  198. (CHSCCDR_CLK_SEL_LDB_DI0 <<
  199. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
  200. /* Turn on IPU LDB DI0 clocks */
  201. setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
  202. enable_ipu_clock();
  203. writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
  204. IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
  205. IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
  206. IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
  207. IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
  208. IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
  209. IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
  210. IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
  211. IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
  212. IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
  213. &iomux->gpr[2]);
  214. clrbits_le32(&iomux->gpr[3],
  215. IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
  216. IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
  217. IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
  218. }
  219. static void setup_display_bx50v3(void)
  220. {
  221. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  222. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  223. enable_videopll();
  224. /* When a reset/reboot is performed the display power needs to be turned
  225. * off for atleast 500ms. The boot time is ~300ms, we need to wait for
  226. * an additional 200ms here. Unfortunately we use external PMIC for
  227. * doing the reset, so can not differentiate between POR vs soft reset
  228. */
  229. mdelay(200);
  230. /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
  231. setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
  232. /* Set LDB_DI0 as clock source for IPU_DI0 */
  233. clrsetbits_le32(&mxc_ccm->chsccdr,
  234. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
  235. (CHSCCDR_CLK_SEL_LDB_DI0 <<
  236. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
  237. /* Turn on IPU LDB DI0 clocks */
  238. setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
  239. enable_ipu_clock();
  240. writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
  241. IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
  242. IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
  243. IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
  244. IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
  245. &iomux->gpr[2]);
  246. clrsetbits_le32(&iomux->gpr[3],
  247. IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
  248. (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
  249. IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
  250. }
  251. #endif /* CONFIG_VIDEO_IPUV3 */
  252. /*
  253. * Do not overwrite the console
  254. * Use always serial for U-Boot console
  255. */
  256. int overwrite_console(void)
  257. {
  258. return 1;
  259. }
  260. #define VPD_TYPE_INVALID 0x00
  261. #define VPD_BLOCK_NETWORK 0x20
  262. #define VPD_BLOCK_HWID 0x44
  263. #define VPD_PRODUCT_B850 1
  264. #define VPD_PRODUCT_B650 2
  265. #define VPD_PRODUCT_B450 3
  266. #define VPD_HAS_MAC1 0x1
  267. #define VPD_HAS_MAC2 0x2
  268. #define VPD_MAC_ADDRESS_LENGTH 6
  269. struct vpd_cache {
  270. bool is_read;
  271. u8 product_id;
  272. u8 has;
  273. unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
  274. unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
  275. };
  276. /*
  277. * Extracts MAC and product information from the VPD.
  278. */
  279. static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
  280. size_t size, u8 const *data)
  281. {
  282. if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
  283. size >= 1) {
  284. vpd->product_id = data[0];
  285. } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
  286. type != VPD_TYPE_INVALID) {
  287. if (size >= 6) {
  288. vpd->has |= VPD_HAS_MAC1;
  289. memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
  290. }
  291. if (size >= 12) {
  292. vpd->has |= VPD_HAS_MAC2;
  293. memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
  294. }
  295. }
  296. return 0;
  297. }
  298. static void process_vpd(struct vpd_cache *vpd)
  299. {
  300. int fec_index = 0;
  301. int i210_index = -1;
  302. if (!vpd->is_read) {
  303. printf("VPD wasn't read");
  304. return;
  305. }
  306. if (vpd->has & VPD_HAS_MAC1)
  307. eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
  308. env_set("ethact", "eth0");
  309. switch (vpd->product_id) {
  310. case VPD_PRODUCT_B450:
  311. env_set("confidx", "1");
  312. i210_index = 1;
  313. break;
  314. case VPD_PRODUCT_B650:
  315. env_set("confidx", "2");
  316. i210_index = 1;
  317. break;
  318. case VPD_PRODUCT_B850:
  319. env_set("confidx", "3");
  320. i210_index = 2;
  321. break;
  322. }
  323. if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
  324. eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
  325. }
  326. static iomux_v3_cfg_t const misc_pads[] = {
  327. MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  328. MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL),
  329. MX6_PAD_EIM_CS0__GPIO2_IO23 | MUX_PAD_CTRL(NC_PAD_CTRL),
  330. MX6_PAD_EIM_CS1__GPIO2_IO24 | MUX_PAD_CTRL(NC_PAD_CTRL),
  331. MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL),
  332. MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL),
  333. MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL),
  334. MX6_PAD_GPIO_9__WDOG1_B | MUX_PAD_CTRL(NC_PAD_CTRL),
  335. };
  336. #define SUS_S3_OUT IMX_GPIO_NR(4, 11)
  337. #define WIFI_EN IMX_GPIO_NR(6, 14)
  338. int board_early_init_f(void)
  339. {
  340. imx_iomux_v3_setup_multiple_pads(misc_pads,
  341. ARRAY_SIZE(misc_pads));
  342. #if defined(CONFIG_VIDEO_IPUV3)
  343. /* Set LDB clock to Video PLL */
  344. select_ldb_di_clock_source(MXC_PLL5_CLK);
  345. #endif
  346. return 0;
  347. }
  348. static void set_confidx(const struct vpd_cache* vpd)
  349. {
  350. switch (vpd->product_id) {
  351. case VPD_PRODUCT_B450:
  352. confidx = 1;
  353. break;
  354. case VPD_PRODUCT_B650:
  355. confidx = 2;
  356. break;
  357. case VPD_PRODUCT_B850:
  358. confidx = 3;
  359. break;
  360. }
  361. }
  362. int board_init(void)
  363. {
  364. if (!read_vpd(&vpd, vpd_callback)) {
  365. int ret, rescan;
  366. vpd.is_read = true;
  367. set_confidx(&vpd);
  368. ret = fdtdec_resetup(&rescan);
  369. if (!ret && rescan) {
  370. dm_uninit();
  371. dm_init_and_scan(false);
  372. }
  373. }
  374. gpio_request(SUS_S3_OUT, "sus_s3_out");
  375. gpio_direction_output(SUS_S3_OUT, 1);
  376. gpio_request(WIFI_EN, "wifi_en");
  377. gpio_direction_output(WIFI_EN, 1);
  378. #if defined(CONFIG_VIDEO_IPUV3)
  379. if (is_b850v3())
  380. setup_display_b850v3();
  381. else
  382. setup_display_bx50v3();
  383. #endif
  384. /* address of boot parameters */
  385. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  386. return 0;
  387. }
  388. #ifdef CONFIG_CMD_BMODE
  389. static const struct boot_mode board_boot_modes[] = {
  390. /* 4 bit bus width */
  391. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  392. {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  393. {NULL, 0},
  394. };
  395. #endif
  396. void pmic_init(void)
  397. {
  398. struct udevice *reg;
  399. int ret, i;
  400. static const char * const bucks[] = {
  401. "bcore1",
  402. "bcore2",
  403. "bpro",
  404. "bmem",
  405. "bio",
  406. "bperi",
  407. };
  408. for (i = 0; i < ARRAY_SIZE(bucks); i++) {
  409. ret = regulator_get_by_devname(bucks[i], &reg);
  410. if (reg < 0) {
  411. printf("%s(): Unable to get regulator %s: %d\n",
  412. __func__, bucks[i], ret);
  413. continue;
  414. }
  415. regulator_set_mode(reg, DA9063_BUCKMODE_SYNC);
  416. }
  417. }
  418. int board_late_init(void)
  419. {
  420. process_vpd(&vpd);
  421. #ifdef CONFIG_CMD_BMODE
  422. add_board_boot_modes(board_boot_modes);
  423. #endif
  424. if (is_b850v3())
  425. env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
  426. else
  427. env_set("videoargs", "video=LVDS-1:1024x768@65");
  428. /* board specific pmic init */
  429. pmic_init();
  430. check_time();
  431. pci_init();
  432. return 0;
  433. }
  434. /*
  435. * Removes the 'eth[0-9]*addr' environment variable with the given index
  436. *
  437. * @param index [in] the index of the eth_device whose variable is to be removed
  438. */
  439. static void remove_ethaddr_env_var(int index)
  440. {
  441. char env_var_name[9];
  442. sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
  443. env_set(env_var_name, NULL);
  444. }
  445. int last_stage_init(void)
  446. {
  447. int i;
  448. /*
  449. * Remove first three ethaddr which may have been created by
  450. * function process_vpd().
  451. */
  452. for (i = 0; i < 3; ++i)
  453. remove_ethaddr_env_var(i);
  454. return 0;
  455. }
  456. int checkboard(void)
  457. {
  458. printf("BOARD: %s\n", CONFIG_BOARD_NAME);
  459. return 0;
  460. }
  461. #ifdef CONFIG_OF_BOARD_SETUP
  462. int ft_board_setup(void *blob, bd_t *bd)
  463. {
  464. char *rtc_status = env_get("rtc_status");
  465. fdt_setprop(blob, 0, "ge,boot-ver", version_string,
  466. strlen(version_string) + 1);
  467. fdt_setprop(blob, 0, "ge,rtc-status", rtc_status,
  468. strlen(rtc_status) + 1);
  469. return 0;
  470. }
  471. #endif
  472. int board_fit_config_name_match(const char *name)
  473. {
  474. if (!vpd.is_read)
  475. return strcmp(name, "imx6q-bx50v3");
  476. switch (vpd.product_id) {
  477. case VPD_PRODUCT_B450:
  478. return strcmp(name, "imx6q-b450v3");
  479. case VPD_PRODUCT_B650:
  480. return strcmp(name, "imx6q-b650v3");
  481. case VPD_PRODUCT_B850:
  482. return strcmp(name, "imx6q-b850v3");
  483. default:
  484. return -1;
  485. }
  486. }
  487. int embedded_dtb_select(void)
  488. {
  489. vpd.is_read = false;
  490. return fdtdec_setup();
  491. }