gw_ventana.c 36 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Gateworks Corporation
  4. *
  5. * Author: Tim Harvey <tharvey@gateworks.com>
  6. */
  7. #include <common.h>
  8. #include <net.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/crm_regs.h>
  11. #include <asm/arch/iomux.h>
  12. #include <asm/arch/mx6-pins.h>
  13. #include <asm/arch/mxc_hdmi.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <asm/gpio.h>
  16. #include <asm/mach-imx/boot_mode.h>
  17. #include <asm/mach-imx/sata.h>
  18. #include <asm/mach-imx/spi.h>
  19. #include <asm/mach-imx/video.h>
  20. #include <asm/io.h>
  21. #include <asm/setup.h>
  22. #include <dm.h>
  23. #include <dm/platform_data/serial_mxc.h>
  24. #include <env.h>
  25. #include <hwconfig.h>
  26. #include <i2c.h>
  27. #include <fdt_support.h>
  28. #include <fsl_esdhc_imx.h>
  29. #include <jffs2/load_kernel.h>
  30. #include <linux/ctype.h>
  31. #include <miiphy.h>
  32. #include <mtd_node.h>
  33. #include <netdev.h>
  34. #include <pci.h>
  35. #include <linux/libfdt.h>
  36. #include <power/pmic.h>
  37. #include <power/ltc3676_pmic.h>
  38. #include <power/pfuze100_pmic.h>
  39. #include <fdt_support.h>
  40. #include <jffs2/load_kernel.h>
  41. #include <spi_flash.h>
  42. #include "gsc.h"
  43. #include "common.h"
  44. DECLARE_GLOBAL_DATA_PTR;
  45. /*
  46. * EEPROM board info struct populated by read_eeprom so that we only have to
  47. * read it once.
  48. */
  49. struct ventana_board_info ventana_info;
  50. static int board_type;
  51. /* ENET */
  52. static iomux_v3_cfg_t const enet_pads[] = {
  53. IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  54. IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  55. IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  56. IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  57. IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  58. IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  59. IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  60. IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  61. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  62. IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
  63. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  64. IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  65. IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  66. IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  67. IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  68. IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  69. IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  70. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  71. /* PHY nRST */
  72. IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
  73. };
  74. #ifdef CONFIG_CMD_NAND
  75. static iomux_v3_cfg_t const nfc_pads[] = {
  76. IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
  77. IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
  78. IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  79. IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  80. IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  81. IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  82. IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  83. IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  84. IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  85. IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  86. IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  87. IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  88. IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  89. IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  90. IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  91. };
  92. static void setup_gpmi_nand(void)
  93. {
  94. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  95. /* config gpmi nand iomux */
  96. SETUP_IOMUX_PADS(nfc_pads);
  97. /* config gpmi and bch clock to 100 MHz */
  98. clrsetbits_le32(&mxc_ccm->cs2cdr,
  99. MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  100. MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  101. MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  102. MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
  103. MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
  104. MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
  105. /* enable gpmi and bch clock gating */
  106. setbits_le32(&mxc_ccm->CCGR4,
  107. MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  108. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  109. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  110. MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  111. MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
  112. /* enable apbh clock gating */
  113. setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  114. }
  115. #endif
  116. static void setup_iomux_enet(int gpio)
  117. {
  118. SETUP_IOMUX_PADS(enet_pads);
  119. /* toggle PHY_RST# */
  120. gpio_request(gpio, "phy_rst#");
  121. gpio_direction_output(gpio, 0);
  122. mdelay(10);
  123. gpio_set_value(gpio, 1);
  124. mdelay(100);
  125. }
  126. #ifdef CONFIG_USB_EHCI_MX6
  127. static iomux_v3_cfg_t const usb_pads[] = {
  128. IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG),
  129. IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
  130. /* OTG PWR */
  131. IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG),
  132. };
  133. int board_ehci_hcd_init(int port)
  134. {
  135. int gpio;
  136. SETUP_IOMUX_PADS(usb_pads);
  137. /* Reset USB HUB */
  138. switch (board_type) {
  139. case GW53xx:
  140. case GW552x:
  141. case GW5906:
  142. gpio = (IMX_GPIO_NR(1, 9));
  143. break;
  144. case GW54proto:
  145. case GW54xx:
  146. gpio = (IMX_GPIO_NR(1, 16));
  147. break;
  148. default:
  149. return 0;
  150. }
  151. /* request and toggle hub rst */
  152. gpio_request(gpio, "usb_hub_rst#");
  153. gpio_direction_output(gpio, 0);
  154. mdelay(2);
  155. gpio_set_value(gpio, 1);
  156. return 0;
  157. }
  158. int board_ehci_power(int port, int on)
  159. {
  160. /* enable OTG VBUS */
  161. if (!port && board_type < GW_UNKNOWN) {
  162. if (gpio_cfg[board_type].otgpwr_en)
  163. gpio_set_value(gpio_cfg[board_type].otgpwr_en, on);
  164. }
  165. return 0;
  166. }
  167. #endif /* CONFIG_USB_EHCI_MX6 */
  168. #ifdef CONFIG_MXC_SPI
  169. iomux_v3_cfg_t const ecspi1_pads[] = {
  170. /* SS1 */
  171. IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  172. IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  173. IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  174. IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  175. };
  176. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  177. {
  178. return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
  179. }
  180. static void setup_spi(void)
  181. {
  182. gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
  183. gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
  184. SETUP_IOMUX_PADS(ecspi1_pads);
  185. }
  186. #endif
  187. /* configure eth0 PHY board-specific LED behavior */
  188. int board_phy_config(struct phy_device *phydev)
  189. {
  190. unsigned short val;
  191. /* Marvel 88E1510 */
  192. if (phydev->phy_id == 0x1410dd1) {
  193. /*
  194. * Page 3, Register 16: LED[2:0] Function Control Register
  195. * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
  196. * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
  197. */
  198. phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
  199. val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
  200. val &= 0xff00;
  201. val |= 0x0017;
  202. phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
  203. phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
  204. }
  205. /* TI DP83867 */
  206. else if (phydev->phy_id == 0x2000a231) {
  207. /* configure register 0x170 for ref CLKOUT */
  208. phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
  209. phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
  210. phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f);
  211. val = phy_read(phydev, MDIO_DEVAD_NONE, 14);
  212. val &= ~0x1f00;
  213. val |= 0x0b00; /* chD tx clock*/
  214. phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
  215. }
  216. if (phydev->drv->config)
  217. phydev->drv->config(phydev);
  218. return 0;
  219. }
  220. #ifdef CONFIG_MV88E61XX_SWITCH
  221. int mv88e61xx_hw_reset(struct phy_device *phydev)
  222. {
  223. struct mii_dev *bus = phydev->bus;
  224. /* GPIO[0] output, CLK125 */
  225. debug("enabling RGMII_REFCLK\n");
  226. bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
  227. 0x1a /*MV_SCRATCH_MISC*/,
  228. (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
  229. bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
  230. 0x1a /*MV_SCRATCH_MISC*/,
  231. (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
  232. /* RGMII delay - Physical Control register bit[15:14] */
  233. debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
  234. /* forced 1000mbps full-duplex link */
  235. bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
  236. phydev->autoneg = AUTONEG_DISABLE;
  237. phydev->speed = SPEED_1000;
  238. phydev->duplex = DUPLEX_FULL;
  239. /* LED configuration: 7:4-green (8=Activity) 3:0 amber (8=Link) */
  240. bus->write(bus, 0x10, 0, 0x16, 0x8088);
  241. bus->write(bus, 0x11, 0, 0x16, 0x8088);
  242. bus->write(bus, 0x12, 0, 0x16, 0x8088);
  243. bus->write(bus, 0x13, 0, 0x16, 0x8088);
  244. return 0;
  245. }
  246. #endif // CONFIG_MV88E61XX_SWITCH
  247. int board_eth_init(bd_t *bis)
  248. {
  249. #ifdef CONFIG_FEC_MXC
  250. struct ventana_board_info *info = &ventana_info;
  251. if (test_bit(EECONFIG_ETH0, info->config)) {
  252. setup_iomux_enet(GP_PHY_RST);
  253. cpu_eth_init(bis);
  254. }
  255. #endif
  256. #ifdef CONFIG_E1000
  257. e1000_initialize(bis);
  258. #endif
  259. #ifdef CONFIG_CI_UDC
  260. /* For otg ethernet*/
  261. usb_eth_initialize(bis);
  262. #endif
  263. /* default to the first detected enet dev */
  264. if (!env_get("ethprime")) {
  265. struct eth_device *dev = eth_get_dev_by_index(0);
  266. if (dev) {
  267. env_set("ethprime", dev->name);
  268. printf("set ethprime to %s\n", env_get("ethprime"));
  269. }
  270. }
  271. return 0;
  272. }
  273. #if defined(CONFIG_VIDEO_IPUV3)
  274. static void enable_hdmi(struct display_info_t const *dev)
  275. {
  276. imx_enable_hdmi_phy();
  277. }
  278. static int detect_i2c(struct display_info_t const *dev)
  279. {
  280. return i2c_set_bus_num(dev->bus) == 0 &&
  281. i2c_probe(dev->addr) == 0;
  282. }
  283. static void enable_lvds(struct display_info_t const *dev)
  284. {
  285. struct iomuxc *iomux = (struct iomuxc *)
  286. IOMUXC_BASE_ADDR;
  287. /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
  288. u32 reg = readl(&iomux->gpr[2]);
  289. reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
  290. writel(reg, &iomux->gpr[2]);
  291. /* Enable Backlight */
  292. gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
  293. gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
  294. gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
  295. SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
  296. gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
  297. }
  298. struct display_info_t const displays[] = {{
  299. /* HDMI Output */
  300. .bus = -1,
  301. .addr = 0,
  302. .pixfmt = IPU_PIX_FMT_RGB24,
  303. .detect = detect_hdmi,
  304. .enable = enable_hdmi,
  305. .mode = {
  306. .name = "HDMI",
  307. .refresh = 60,
  308. .xres = 1024,
  309. .yres = 768,
  310. .pixclock = 15385,
  311. .left_margin = 220,
  312. .right_margin = 40,
  313. .upper_margin = 21,
  314. .lower_margin = 7,
  315. .hsync_len = 60,
  316. .vsync_len = 10,
  317. .sync = FB_SYNC_EXT,
  318. .vmode = FB_VMODE_NONINTERLACED
  319. } }, {
  320. /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
  321. .bus = 2,
  322. .addr = 0x4,
  323. .pixfmt = IPU_PIX_FMT_LVDS666,
  324. .detect = detect_i2c,
  325. .enable = enable_lvds,
  326. .mode = {
  327. .name = "Hannstar-XGA",
  328. .refresh = 60,
  329. .xres = 1024,
  330. .yres = 768,
  331. .pixclock = 15385,
  332. .left_margin = 220,
  333. .right_margin = 40,
  334. .upper_margin = 21,
  335. .lower_margin = 7,
  336. .hsync_len = 60,
  337. .vsync_len = 10,
  338. .sync = FB_SYNC_EXT,
  339. .vmode = FB_VMODE_NONINTERLACED
  340. } }, {
  341. /* DLC700JMG-T-4 */
  342. .bus = 2,
  343. .addr = 0x38,
  344. .detect = NULL,
  345. .enable = enable_lvds,
  346. .pixfmt = IPU_PIX_FMT_LVDS666,
  347. .mode = {
  348. .name = "DLC700JMGT4",
  349. .refresh = 60,
  350. .xres = 1024, /* 1024x600active pixels */
  351. .yres = 600,
  352. .pixclock = 15385, /* 64MHz */
  353. .left_margin = 220,
  354. .right_margin = 40,
  355. .upper_margin = 21,
  356. .lower_margin = 7,
  357. .hsync_len = 60,
  358. .vsync_len = 10,
  359. .sync = FB_SYNC_EXT,
  360. .vmode = FB_VMODE_NONINTERLACED
  361. } }, {
  362. /* DLC800FIG-T-3 */
  363. .bus = 2,
  364. .addr = 0x14,
  365. .detect = NULL,
  366. .enable = enable_lvds,
  367. .pixfmt = IPU_PIX_FMT_LVDS666,
  368. .mode = {
  369. .name = "DLC800FIGT3",
  370. .refresh = 60,
  371. .xres = 1024, /* 1024x768 active pixels */
  372. .yres = 768,
  373. .pixclock = 15385, /* 64MHz */
  374. .left_margin = 220,
  375. .right_margin = 40,
  376. .upper_margin = 21,
  377. .lower_margin = 7,
  378. .hsync_len = 60,
  379. .vsync_len = 10,
  380. .sync = FB_SYNC_EXT,
  381. .vmode = FB_VMODE_NONINTERLACED
  382. } }, {
  383. .bus = 2,
  384. .addr = 0x5d,
  385. .detect = detect_i2c,
  386. .enable = enable_lvds,
  387. .pixfmt = IPU_PIX_FMT_LVDS666,
  388. .mode = {
  389. .name = "Z101WX01",
  390. .refresh = 60,
  391. .xres = 1280,
  392. .yres = 800,
  393. .pixclock = 15385, /* 64MHz */
  394. .left_margin = 220,
  395. .right_margin = 40,
  396. .upper_margin = 21,
  397. .lower_margin = 7,
  398. .hsync_len = 60,
  399. .vsync_len = 10,
  400. .sync = FB_SYNC_EXT,
  401. .vmode = FB_VMODE_NONINTERLACED
  402. }
  403. },
  404. };
  405. size_t display_count = ARRAY_SIZE(displays);
  406. static void setup_display(void)
  407. {
  408. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  409. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  410. int reg;
  411. enable_ipu_clock();
  412. imx_setup_hdmi();
  413. /* Turn on LDB0,IPU,IPU DI0 clocks */
  414. reg = __raw_readl(&mxc_ccm->CCGR3);
  415. reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
  416. writel(reg, &mxc_ccm->CCGR3);
  417. /* set LDB0, LDB1 clk select to 011/011 */
  418. reg = readl(&mxc_ccm->cs2cdr);
  419. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
  420. |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  421. reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
  422. |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  423. writel(reg, &mxc_ccm->cs2cdr);
  424. reg = readl(&mxc_ccm->cscmr2);
  425. reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
  426. writel(reg, &mxc_ccm->cscmr2);
  427. reg = readl(&mxc_ccm->chsccdr);
  428. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  429. <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  430. writel(reg, &mxc_ccm->chsccdr);
  431. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  432. |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
  433. |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  434. |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  435. |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  436. |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  437. |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  438. |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
  439. |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  440. writel(reg, &iomux->gpr[2]);
  441. reg = readl(&iomux->gpr[3]);
  442. reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
  443. | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  444. <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  445. writel(reg, &iomux->gpr[3]);
  446. /* LVDS Backlight GPIO on LVDS connector - output low */
  447. SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
  448. gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
  449. }
  450. #endif /* CONFIG_VIDEO_IPUV3 */
  451. /* setup board specific PMIC */
  452. int power_init_board(void)
  453. {
  454. setup_pmic();
  455. return 0;
  456. }
  457. #if defined(CONFIG_CMD_PCI)
  458. int imx6_pcie_toggle_reset(void)
  459. {
  460. if (board_type < GW_UNKNOWN) {
  461. uint pin = gpio_cfg[board_type].pcie_rst;
  462. gpio_request(pin, "pci_rst#");
  463. gpio_direction_output(pin, 0);
  464. mdelay(50);
  465. gpio_direction_output(pin, 1);
  466. }
  467. return 0;
  468. }
  469. /*
  470. * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
  471. * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
  472. * properly and assert reset for 100ms.
  473. */
  474. #define MAX_PCI_DEVS 32
  475. struct pci_dev {
  476. pci_dev_t devfn;
  477. unsigned short vendor;
  478. unsigned short device;
  479. unsigned short class;
  480. unsigned short busno; /* subbordinate busno */
  481. struct pci_dev *ppar;
  482. };
  483. struct pci_dev pci_devs[MAX_PCI_DEVS];
  484. int pci_devno;
  485. int pci_bridgeno;
  486. void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
  487. unsigned short vendor, unsigned short device,
  488. unsigned short class)
  489. {
  490. int i;
  491. u32 dw;
  492. struct pci_dev *pdev = &pci_devs[pci_devno++];
  493. debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
  494. PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
  495. /* store array of devs for later use in device-tree fixup */
  496. pdev->devfn = dev;
  497. pdev->vendor = vendor;
  498. pdev->device = device;
  499. pdev->class = class;
  500. pdev->ppar = NULL;
  501. if (class == PCI_CLASS_BRIDGE_PCI)
  502. pdev->busno = ++pci_bridgeno;
  503. else
  504. pdev->busno = 0;
  505. /* fixup RC - it should be 00:00.0 not 00:01.0 */
  506. if (PCI_BUS(dev) == 0)
  507. pdev->devfn = 0;
  508. /* find dev's parent */
  509. for (i = 0; i < pci_devno; i++) {
  510. if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
  511. pdev->ppar = &pci_devs[i];
  512. break;
  513. }
  514. }
  515. /* assert downstream PERST# */
  516. if (vendor == PCI_VENDOR_ID_PLX &&
  517. (device & 0xfff0) == 0x8600 &&
  518. PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
  519. debug("configuring PLX 860X downstream PERST#\n");
  520. pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
  521. dw |= 0xaaa8; /* GPIO1-7 outputs */
  522. pci_hose_write_config_dword(hose, dev, 0x62c, dw);
  523. pci_hose_read_config_dword(hose, dev, 0x644, &dw);
  524. dw |= 0xfe; /* GPIO1-7 output high */
  525. pci_hose_write_config_dword(hose, dev, 0x644, dw);
  526. mdelay(100);
  527. }
  528. }
  529. #endif /* CONFIG_CMD_PCI */
  530. #ifdef CONFIG_SERIAL_TAG
  531. /*
  532. * called when setting up ATAGS before booting kernel
  533. * populate serialnum from the following (in order of priority):
  534. * serial# env var
  535. * eeprom
  536. */
  537. void get_board_serial(struct tag_serialnr *serialnr)
  538. {
  539. char *serial = env_get("serial#");
  540. if (serial) {
  541. serialnr->high = 0;
  542. serialnr->low = simple_strtoul(serial, NULL, 10);
  543. } else if (ventana_info.model[0]) {
  544. serialnr->high = 0;
  545. serialnr->low = ventana_info.serial;
  546. } else {
  547. serialnr->high = 0;
  548. serialnr->low = 0;
  549. }
  550. }
  551. #endif
  552. /*
  553. * Board Support
  554. */
  555. int board_early_init_f(void)
  556. {
  557. setup_iomux_uart();
  558. #if defined(CONFIG_VIDEO_IPUV3)
  559. setup_display();
  560. #endif
  561. return 0;
  562. }
  563. int dram_init(void)
  564. {
  565. gd->ram_size = imx_ddr_size();
  566. return 0;
  567. }
  568. int board_init(void)
  569. {
  570. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  571. clrsetbits_le32(&iomuxc_regs->gpr[1],
  572. IOMUXC_GPR1_OTG_ID_MASK,
  573. IOMUXC_GPR1_OTG_ID_GPIO1);
  574. /* address of linux boot parameters */
  575. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  576. /* read Gateworks EEPROM into global struct (used later) */
  577. setup_ventana_i2c(0);
  578. board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
  579. #ifdef CONFIG_CMD_NAND
  580. if (gpio_cfg[board_type].nand)
  581. setup_gpmi_nand();
  582. #endif
  583. #ifdef CONFIG_MXC_SPI
  584. setup_spi();
  585. #endif
  586. setup_ventana_i2c(1);
  587. setup_ventana_i2c(2);
  588. #ifdef CONFIG_SATA
  589. setup_sata();
  590. #endif
  591. setup_iomux_gpio(board_type, &ventana_info);
  592. return 0;
  593. }
  594. #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
  595. /*
  596. * called during late init (after relocation and after board_init())
  597. * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
  598. * EEPROM read.
  599. */
  600. int checkboard(void)
  601. {
  602. struct ventana_board_info *info = &ventana_info;
  603. unsigned char buf[4];
  604. const char *p;
  605. int quiet; /* Quiet or minimal output mode */
  606. quiet = 0;
  607. p = env_get("quiet");
  608. if (p)
  609. quiet = simple_strtol(p, NULL, 10);
  610. else
  611. env_set("quiet", "0");
  612. puts("\nGateworks Corporation Copyright 2014\n");
  613. if (info->model[0]) {
  614. printf("Model: %s\n", info->model);
  615. printf("MFGDate: %02x-%02x-%02x%02x\n",
  616. info->mfgdate[0], info->mfgdate[1],
  617. info->mfgdate[2], info->mfgdate[3]);
  618. printf("Serial:%d\n", info->serial);
  619. } else {
  620. puts("Invalid EEPROM - board will not function fully\n");
  621. }
  622. if (quiet)
  623. return 0;
  624. /* Display GSC firmware revision/CRC/status */
  625. gsc_info(0);
  626. /* Display RTC */
  627. if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
  628. printf("RTC: %d\n",
  629. buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
  630. }
  631. return 0;
  632. }
  633. #endif
  634. #ifdef CONFIG_CMD_BMODE
  635. /*
  636. * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
  637. * see Table 8-11 and Table 5-9
  638. * BOOT_CFG1[7] = 1 (boot from NAND)
  639. * BOOT_CFG1[5] = 0 - raw NAND
  640. * BOOT_CFG1[4] = 0 - default pad settings
  641. * BOOT_CFG1[3:2] = 00 - devices = 1
  642. * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
  643. * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
  644. * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
  645. * BOOT_CFG2[0] = 0 - Reset time 12ms
  646. */
  647. static const struct boot_mode board_boot_modes[] = {
  648. /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
  649. { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
  650. { "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
  651. { "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/4/5 */
  652. { NULL, 0 },
  653. };
  654. #endif
  655. /* late init */
  656. int misc_init_r(void)
  657. {
  658. struct ventana_board_info *info = &ventana_info;
  659. char buf[256];
  660. int i;
  661. /* set env vars based on EEPROM data */
  662. if (ventana_info.model[0]) {
  663. char str[16], fdt[36];
  664. char *p;
  665. const char *cputype = "";
  666. /*
  667. * FDT name will be prefixed with CPU type. Three versions
  668. * will be created each increasingly generic and bootloader
  669. * env scripts will try loading each from most specific to
  670. * least.
  671. */
  672. if (is_cpu_type(MXC_CPU_MX6Q) ||
  673. is_cpu_type(MXC_CPU_MX6D))
  674. cputype = "imx6q";
  675. else if (is_cpu_type(MXC_CPU_MX6DL) ||
  676. is_cpu_type(MXC_CPU_MX6SOLO))
  677. cputype = "imx6dl";
  678. env_set("soctype", cputype);
  679. if (8 << (ventana_info.nand_flash_size-1) >= 2048)
  680. env_set("flash_layout", "large");
  681. else
  682. env_set("flash_layout", "normal");
  683. memset(str, 0, sizeof(str));
  684. for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
  685. str[i] = tolower(info->model[i]);
  686. env_set("model", str);
  687. if (!env_get("fdt_file")) {
  688. sprintf(fdt, "%s-%s.dtb", cputype, str);
  689. env_set("fdt_file", fdt);
  690. }
  691. p = strchr(str, '-');
  692. if (p) {
  693. *p++ = 0;
  694. env_set("model_base", str);
  695. sprintf(fdt, "%s-%s.dtb", cputype, str);
  696. env_set("fdt_file1", fdt);
  697. if (board_type != GW551x &&
  698. board_type != GW552x &&
  699. board_type != GW553x &&
  700. board_type != GW560x)
  701. str[4] = 'x';
  702. str[5] = 'x';
  703. str[6] = 0;
  704. sprintf(fdt, "%s-%s.dtb", cputype, str);
  705. env_set("fdt_file2", fdt);
  706. }
  707. /* initialize env from EEPROM */
  708. if (test_bit(EECONFIG_ETH0, info->config) &&
  709. !env_get("ethaddr")) {
  710. eth_env_set_enetaddr("ethaddr", info->mac0);
  711. }
  712. if (test_bit(EECONFIG_ETH1, info->config) &&
  713. !env_get("eth1addr")) {
  714. eth_env_set_enetaddr("eth1addr", info->mac1);
  715. }
  716. /* board serial-number */
  717. sprintf(str, "%6d", info->serial);
  718. env_set("serial#", str);
  719. /* memory MB */
  720. sprintf(str, "%d", (int) (gd->ram_size >> 20));
  721. env_set("mem_mb", str);
  722. }
  723. /* Set a non-initialized hwconfig based on board configuration */
  724. if (!strcmp(env_get("hwconfig"), "_UNKNOWN_")) {
  725. buf[0] = 0;
  726. if (gpio_cfg[board_type].rs232_en)
  727. strcat(buf, "rs232;");
  728. for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
  729. char buf1[32];
  730. sprintf(buf1, "dio%d:mode=gpio;", i);
  731. if (strlen(buf) + strlen(buf1) < sizeof(buf))
  732. strcat(buf, buf1);
  733. }
  734. env_set("hwconfig", buf);
  735. }
  736. /* setup baseboard specific GPIO based on board and env */
  737. setup_board_gpio(board_type, info);
  738. #ifdef CONFIG_CMD_BMODE
  739. add_board_boot_modes(board_boot_modes);
  740. #endif
  741. /* disable boot watchdog */
  742. gsc_boot_wd_disable();
  743. return 0;
  744. }
  745. #ifdef CONFIG_OF_BOARD_SETUP
  746. static int ft_sethdmiinfmt(void *blob, char *mode)
  747. {
  748. int off;
  749. if (!mode)
  750. return -EINVAL;
  751. off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
  752. if (off < 0)
  753. return off;
  754. if (0 == strcasecmp(mode, "yuv422bt656")) {
  755. u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
  756. 0x00, 0x00, 0x00 };
  757. mode = "422_ccir";
  758. fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
  759. fdt_setprop_u32(blob, off, "vidout_trc", 1);
  760. fdt_setprop_u32(blob, off, "vidout_blc", 1);
  761. fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
  762. printf(" set HDMI input mode to %s\n", mode);
  763. } else if (0 == strcasecmp(mode, "yuv422smp")) {
  764. u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
  765. 0x82, 0x81, 0x00 };
  766. mode = "422_smp";
  767. fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
  768. fdt_setprop_u32(blob, off, "vidout_trc", 0);
  769. fdt_setprop_u32(blob, off, "vidout_blc", 0);
  770. fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
  771. printf(" set HDMI input mode to %s\n", mode);
  772. } else {
  773. return -EINVAL;
  774. }
  775. return 0;
  776. }
  777. #if defined(CONFIG_CMD_PCI)
  778. #define PCI_ID(x) ( \
  779. (PCI_BUS(x->devfn)<<16)| \
  780. (PCI_DEV(x->devfn)<<11)| \
  781. (PCI_FUNC(x->devfn)<<8) \
  782. )
  783. int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
  784. {
  785. uint32_t reg[5];
  786. char node[32];
  787. int np;
  788. sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
  789. PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
  790. np = fdt_subnode_offset(blob, par, node);
  791. if (np >= 0)
  792. return np;
  793. np = fdt_add_subnode(blob, par, node);
  794. if (np < 0) {
  795. printf(" %s failed: no space\n", __func__);
  796. return np;
  797. }
  798. memset(reg, 0, sizeof(reg));
  799. reg[0] = cpu_to_fdt32(PCI_ID(dev));
  800. fdt_setprop(blob, np, "reg", reg, sizeof(reg));
  801. return np;
  802. }
  803. /* build a path of nested PCI devs for all bridges passed through */
  804. int fdt_add_pci_path(void *blob, struct pci_dev *dev)
  805. {
  806. struct pci_dev *bridges[MAX_PCI_DEVS];
  807. int k, np;
  808. /* build list of parents */
  809. np = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
  810. if (np < 0)
  811. return np;
  812. k = 0;
  813. while (dev) {
  814. bridges[k++] = dev;
  815. dev = dev->ppar;
  816. };
  817. /* now add them the to DT in reverse order */
  818. while (k--) {
  819. np = fdt_add_pci_node(blob, np, bridges[k]);
  820. if (np < 0)
  821. break;
  822. }
  823. return np;
  824. }
  825. /*
  826. * The GW16082 has a hardware errata errata such that it's
  827. * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
  828. * of this normal PCI interrupt swizzling will not work so we will
  829. * provide an irq-map via device-tree.
  830. */
  831. int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
  832. {
  833. int len;
  834. int host;
  835. uint32_t imap_new[8*4*4];
  836. const uint32_t *imap;
  837. uint32_t irq[4];
  838. uint32_t reg[4];
  839. int i;
  840. /* build irq-map based on host controllers map */
  841. host = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
  842. if (host < 0) {
  843. printf(" %s failed: missing host\n", __func__);
  844. return host;
  845. }
  846. /* use interrupt data from root complex's node */
  847. imap = fdt_getprop(blob, host, "interrupt-map", &len);
  848. if (!imap || len != 128) {
  849. printf(" %s failed: invalid interrupt-map\n",
  850. __func__);
  851. return -FDT_ERR_NOTFOUND;
  852. }
  853. /* obtain irq's of host controller in pin order */
  854. for (i = 0; i < 4; i++)
  855. irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
  856. /*
  857. * determine number of swizzles necessary:
  858. * For each bridge we pass through we need to swizzle
  859. * the number of the slot we are on.
  860. */
  861. struct pci_dev *d;
  862. int b;
  863. b = 0;
  864. d = dev->ppar;
  865. while(d && d->ppar) {
  866. b += PCI_DEV(d->devfn);
  867. d = d->ppar;
  868. }
  869. /* create new irq mappings for slots12-15
  870. * <skt> <idsel> <slot> <skt-inta> <skt-intb>
  871. * J3 AD28 12 INTD INTA
  872. * J4 AD29 13 INTC INTD
  873. * J5 AD30 14 INTB INTC
  874. * J2 AD31 15 INTA INTB
  875. */
  876. for (i = 0; i < 4; i++) {
  877. /* addr matches bus:dev:func */
  878. u32 addr = dev->busno << 16 | (12+i) << 11;
  879. /* default cells from root complex */
  880. memcpy(&imap_new[i*32], imap, 128);
  881. /* first cell is PCI device address (BDF) */
  882. imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
  883. imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
  884. imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
  885. imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
  886. /* third cell is pin */
  887. imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
  888. imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
  889. imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
  890. imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
  891. /* sixth cell is relative interrupt */
  892. imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
  893. imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
  894. imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
  895. imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
  896. }
  897. fdt_setprop(blob, np, "interrupt-map", imap_new,
  898. sizeof(imap_new));
  899. reg[0] = cpu_to_fdt32(0xfff00);
  900. reg[1] = 0;
  901. reg[2] = 0;
  902. reg[3] = cpu_to_fdt32(0x7);
  903. fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
  904. fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
  905. fdt_setprop_string(blob, np, "device_type", "pci");
  906. fdt_setprop_cell(blob, np, "#address-cells", 3);
  907. fdt_setprop_cell(blob, np, "#size-cells", 2);
  908. printf(" Added custom interrupt-map for GW16082\n");
  909. return 0;
  910. }
  911. /* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
  912. int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
  913. {
  914. char *tmp, *end;
  915. char mac[16];
  916. unsigned char mac_addr[6];
  917. int j;
  918. sprintf(mac, "eth1addr");
  919. tmp = env_get(mac);
  920. if (tmp) {
  921. for (j = 0; j < 6; j++) {
  922. mac_addr[j] = tmp ?
  923. simple_strtoul(tmp, &end,16) : 0;
  924. if (tmp)
  925. tmp = (*end) ? end+1 : end;
  926. }
  927. fdt_setprop(blob, np, "local-mac-address", mac_addr,
  928. sizeof(mac_addr));
  929. printf(" Added mac addr for eth1\n");
  930. return 0;
  931. }
  932. return -1;
  933. }
  934. /*
  935. * PCI DT nodes must be nested therefore if we need to apply a DT fixup
  936. * we will walk the PCI bus and add bridge nodes up to the device receiving
  937. * the fixup.
  938. */
  939. void ft_board_pci_fixup(void *blob, bd_t *bd)
  940. {
  941. int i, np;
  942. struct pci_dev *dev;
  943. for (i = 0; i < pci_devno; i++) {
  944. dev = &pci_devs[i];
  945. /*
  946. * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
  947. * an EEPROM at i2c1-0x50.
  948. */
  949. if ((dev->vendor == PCI_VENDOR_ID_TI) &&
  950. (dev->device == 0x8240) &&
  951. (i2c_set_bus_num(1) == 0) &&
  952. (i2c_probe(0x50) == 0))
  953. {
  954. np = fdt_add_pci_path(blob, dev);
  955. if (np > 0)
  956. fdt_fixup_gw16082(blob, np, dev);
  957. }
  958. /* ethernet1 mac address */
  959. else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
  960. (dev->device == 0x4380))
  961. {
  962. np = fdt_add_pci_path(blob, dev);
  963. if (np > 0)
  964. fdt_fixup_sky2(blob, np, dev);
  965. }
  966. }
  967. }
  968. #endif /* if defined(CONFIG_CMD_PCI) */
  969. void ft_board_wdog_fixup(void *blob, phys_addr_t addr)
  970. {
  971. int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr);
  972. if (off) {
  973. fdt_delprop(blob, off, "ext-reset-output");
  974. fdt_delprop(blob, off, "fsl,ext-reset-output");
  975. }
  976. }
  977. /*
  978. * called prior to booting kernel or by 'fdt boardsetup' command
  979. *
  980. * unless 'fdt_noauto' env var is set we will update the following in the DTB:
  981. * - mtd partitions based on mtdparts/mtdids env
  982. * - system-serial (board serial num from EEPROM)
  983. * - board (full model from EEPROM)
  984. * - peripherals removed from DTB if not loaded on board (per EEPROM config)
  985. */
  986. #define WDOG1_ADDR 0x20bc000
  987. #define WDOG2_ADDR 0x20c0000
  988. #define GPIO3_ADDR 0x20a4000
  989. #define USDHC3_ADDR 0x2198000
  990. #define PWM0_ADDR 0x2080000
  991. int ft_board_setup(void *blob, bd_t *bd)
  992. {
  993. struct ventana_board_info *info = &ventana_info;
  994. struct ventana_eeprom_config *cfg;
  995. static const struct node_info nodes[] = {
  996. { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
  997. { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
  998. };
  999. const char *model = env_get("model");
  1000. const char *display = env_get("display");
  1001. int i;
  1002. char rev = 0;
  1003. /* determine board revision */
  1004. for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
  1005. if (ventana_info.model[i] >= 'A') {
  1006. rev = ventana_info.model[i];
  1007. break;
  1008. }
  1009. }
  1010. if (env_get("fdt_noauto")) {
  1011. puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
  1012. return 0;
  1013. }
  1014. if (test_bit(EECONFIG_NAND, info->config)) {
  1015. /* Update partition nodes using info from mtdparts env var */
  1016. puts(" Updating MTD partitions...\n");
  1017. fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
  1018. }
  1019. /* Update display timings from display env var */
  1020. if (display) {
  1021. if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
  1022. display) >= 0)
  1023. printf(" Set display timings for %s...\n", display);
  1024. }
  1025. printf(" Adjusting FDT per EEPROM for %s...\n", model);
  1026. /* board serial number */
  1027. fdt_setprop(blob, 0, "system-serial", env_get("serial#"),
  1028. strlen(env_get("serial#")) + 1);
  1029. /* board (model contains model from device-tree) */
  1030. fdt_setprop(blob, 0, "board", info->model,
  1031. strlen((const char *)info->model) + 1);
  1032. /* set desired digital video capture format */
  1033. ft_sethdmiinfmt(blob, env_get("hdmiinfmt"));
  1034. /*
  1035. * Board model specific fixups
  1036. */
  1037. switch (board_type) {
  1038. case GW51xx:
  1039. /*
  1040. * disable wdog node for GW51xx-A/B to work around
  1041. * errata causing wdog timer to be unreliable.
  1042. */
  1043. if (rev >= 'A' && rev < 'C') {
  1044. i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt",
  1045. WDOG1_ADDR);
  1046. if (i)
  1047. fdt_status_disabled(blob, i);
  1048. }
  1049. /* GW51xx-E adds WDOG1_B external reset */
  1050. if (rev < 'E')
  1051. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1052. break;
  1053. case GW52xx:
  1054. /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
  1055. if (info->model[4] == '2') {
  1056. u32 handle = 0;
  1057. u32 *range = NULL;
  1058. i = fdt_node_offset_by_compatible(blob, -1,
  1059. "fsl,imx6q-pcie");
  1060. if (i)
  1061. range = (u32 *)fdt_getprop(blob, i,
  1062. "reset-gpio", NULL);
  1063. if (range) {
  1064. i = fdt_node_offset_by_compat_reg(blob,
  1065. "fsl,imx6q-gpio", GPIO3_ADDR);
  1066. if (i)
  1067. handle = fdt_get_phandle(blob, i);
  1068. if (handle) {
  1069. range[0] = cpu_to_fdt32(handle);
  1070. range[1] = cpu_to_fdt32(23);
  1071. }
  1072. }
  1073. /* these have broken usd_vsel */
  1074. if (strstr((const char *)info->model, "SP318-B") ||
  1075. strstr((const char *)info->model, "SP331-B"))
  1076. gpio_cfg[board_type].usd_vsel = 0;
  1077. /* GW522x-B adds WDOG1_B external reset */
  1078. if (rev < 'B')
  1079. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1080. }
  1081. /* GW520x-E adds WDOG1_B external reset */
  1082. else if (info->model[4] == '0' && rev < 'E')
  1083. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1084. break;
  1085. case GW53xx:
  1086. /* GW53xx-E adds WDOG1_B external reset */
  1087. if (rev < 'E')
  1088. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1089. break;
  1090. case GW54xx:
  1091. /*
  1092. * disable serial2 node for GW54xx for compatibility with older
  1093. * 3.10.x kernel that improperly had this node enabled in the DT
  1094. */
  1095. fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED,
  1096. 0);
  1097. /* GW54xx-E adds WDOG2_B external reset */
  1098. if (rev < 'E')
  1099. ft_board_wdog_fixup(blob, WDOG2_ADDR);
  1100. break;
  1101. case GW551x:
  1102. /*
  1103. * isolate CSI0_DATA_EN for GW551x-A to work around errata
  1104. * causing non functional digital video in (it is not hooked up)
  1105. */
  1106. if (rev == 'A') {
  1107. u32 *range = NULL;
  1108. int len;
  1109. const u32 *handle = NULL;
  1110. i = fdt_node_offset_by_compatible(blob, -1,
  1111. "fsl,imx-tda1997x-video");
  1112. if (i)
  1113. handle = fdt_getprop(blob, i, "pinctrl-0",
  1114. NULL);
  1115. if (handle)
  1116. i = fdt_node_offset_by_phandle(blob,
  1117. fdt32_to_cpu(*handle));
  1118. if (i)
  1119. range = (u32 *)fdt_getprop(blob, i, "fsl,pins",
  1120. &len);
  1121. if (range) {
  1122. len /= sizeof(u32);
  1123. for (i = 0; i < len; i += 6) {
  1124. u32 mux_reg = fdt32_to_cpu(range[i+0]);
  1125. u32 conf_reg = fdt32_to_cpu(range[i+1]);
  1126. /* mux PAD_CSI0_DATA_EN to GPIO */
  1127. if (is_cpu_type(MXC_CPU_MX6Q) &&
  1128. mux_reg == 0x260 &&
  1129. conf_reg == 0x630)
  1130. range[i+3] = cpu_to_fdt32(0x5);
  1131. else if (!is_cpu_type(MXC_CPU_MX6Q) &&
  1132. mux_reg == 0x08c &&
  1133. conf_reg == 0x3a0)
  1134. range[i+3] = cpu_to_fdt32(0x5);
  1135. }
  1136. fdt_setprop_inplace(blob, i, "fsl,pins", range,
  1137. len);
  1138. }
  1139. /* set BT656 video format */
  1140. ft_sethdmiinfmt(blob, "yuv422bt656");
  1141. }
  1142. /* GW551x-C adds WDOG1_B external reset */
  1143. if (rev < 'C')
  1144. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1145. break;
  1146. case GW5901:
  1147. case GW5902:
  1148. /* GW5901/GW5901 revB adds WDOG1_B as an external reset */
  1149. if (rev < 'B')
  1150. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1151. break;
  1152. }
  1153. /* Configure DIO */
  1154. for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
  1155. struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
  1156. char arg[10];
  1157. sprintf(arg, "dio%d", i);
  1158. if (!hwconfig(arg))
  1159. continue;
  1160. if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
  1161. {
  1162. phys_addr_t addr;
  1163. int off;
  1164. printf(" Enabling pwm%d for DIO%d\n",
  1165. cfg->pwm_param, i);
  1166. addr = PWM0_ADDR + (0x4000 * (cfg->pwm_param - 1));
  1167. off = fdt_node_offset_by_compat_reg(blob,
  1168. "fsl,imx6q-pwm",
  1169. addr);
  1170. if (off)
  1171. fdt_status_okay(blob, off);
  1172. }
  1173. }
  1174. /* remove no-1-8-v if UHS-I support is present */
  1175. if (gpio_cfg[board_type].usd_vsel) {
  1176. debug("Enabling UHS-I support\n");
  1177. i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc",
  1178. USDHC3_ADDR);
  1179. if (i)
  1180. fdt_delprop(blob, i, "no-1-8-v");
  1181. }
  1182. #if defined(CONFIG_CMD_PCI)
  1183. if (!env_get("nopcifixup"))
  1184. ft_board_pci_fixup(blob, bd);
  1185. #endif
  1186. /*
  1187. * Peripheral Config:
  1188. * remove nodes by alias path if EEPROM config tells us the
  1189. * peripheral is not loaded on the board.
  1190. */
  1191. if (env_get("fdt_noconfig")) {
  1192. puts(" Skiping periperhal config (fdt_noconfig defined)\n");
  1193. return 0;
  1194. }
  1195. cfg = econfig;
  1196. while (cfg->name) {
  1197. if (!test_bit(cfg->bit, info->config)) {
  1198. fdt_del_node_and_alias(blob, cfg->dtalias ?
  1199. cfg->dtalias : cfg->name);
  1200. }
  1201. cfg++;
  1202. }
  1203. return 0;
  1204. }
  1205. #endif /* CONFIG_OF_BOARD_SETUP */
  1206. static struct mxc_serial_platdata ventana_mxc_serial_plat = {
  1207. .reg = (struct mxc_uart *)UART2_BASE,
  1208. };
  1209. U_BOOT_DEVICE(ventana_serial) = {
  1210. .name = "serial_mxc",
  1211. .platdata = &ventana_mxc_serial_plat,
  1212. };