eth.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2012 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <fdt_support.h>
  8. #include <net.h>
  9. #include <netdev.h>
  10. #include <asm/mmu.h>
  11. #include <asm/processor.h>
  12. #include <asm/cache.h>
  13. #include <asm/immap_85xx.h>
  14. #include <asm/fsl_law.h>
  15. #include <fsl_ddr_sdram.h>
  16. #include <asm/fsl_serdes.h>
  17. #include <asm/fsl_portals.h>
  18. #include <asm/fsl_liodn.h>
  19. #include <malloc.h>
  20. #include <fm_eth.h>
  21. #include <fsl_mdio.h>
  22. #include <miiphy.h>
  23. #include <phy.h>
  24. #include <fsl_dtsec.h>
  25. #include <asm/fsl_serdes.h>
  26. #include <hwconfig.h>
  27. #include "../common/qixis.h"
  28. #include "../common/fman.h"
  29. #include <linux/libfdt.h>
  30. #include "t4240qds_qixis.h"
  31. #define EMI_NONE 0xFFFFFFFF
  32. #define EMI1_RGMII 0
  33. #define EMI1_SLOT1 1
  34. #define EMI1_SLOT2 2
  35. #define EMI1_SLOT3 3
  36. #define EMI1_SLOT4 4
  37. #define EMI1_SLOT5 5
  38. #define EMI1_SLOT7 7
  39. #define EMI2 8
  40. /* Slot6 and Slot8 do not have EMI connections */
  41. static int mdio_mux[NUM_FM_PORTS];
  42. static const char *mdio_names[] = {
  43. "T4240QDS_MDIO0",
  44. "T4240QDS_MDIO1",
  45. "T4240QDS_MDIO2",
  46. "T4240QDS_MDIO3",
  47. "T4240QDS_MDIO4",
  48. "T4240QDS_MDIO5",
  49. "NULL",
  50. "T4240QDS_MDIO7",
  51. "T4240QDS_10GC",
  52. };
  53. static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
  54. static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
  55. static u8 slot_qsgmii_phyaddr[5][4] = {
  56. {0, 0, 0, 0},/* not used, to make index match slot No. */
  57. {0, 1, 2, 3},
  58. {4, 5, 6, 7},
  59. {8, 9, 0xa, 0xb},
  60. {0xc, 0xd, 0xe, 0xf},
  61. };
  62. static u8 qsgmiiphy_fix[NUM_FM_PORTS] = {0};
  63. static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
  64. {
  65. return mdio_names[muxval];
  66. }
  67. struct mii_dev *mii_dev_for_muxval(u8 muxval)
  68. {
  69. struct mii_dev *bus;
  70. const char *name = t4240qds_mdio_name_for_muxval(muxval);
  71. if (!name) {
  72. printf("No bus for muxval %x\n", muxval);
  73. return NULL;
  74. }
  75. bus = miiphy_get_dev_by_name(name);
  76. if (!bus) {
  77. printf("No bus by name %s\n", name);
  78. return NULL;
  79. }
  80. return bus;
  81. }
  82. struct t4240qds_mdio {
  83. u8 muxval;
  84. struct mii_dev *realbus;
  85. };
  86. static void t4240qds_mux_mdio(u8 muxval)
  87. {
  88. u8 brdcfg4;
  89. if ((muxval < 6) || (muxval == 7)) {
  90. brdcfg4 = QIXIS_READ(brdcfg[4]);
  91. brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
  92. brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
  93. QIXIS_WRITE(brdcfg[4], brdcfg4);
  94. }
  95. }
  96. static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad,
  97. int regnum)
  98. {
  99. struct t4240qds_mdio *priv = bus->priv;
  100. t4240qds_mux_mdio(priv->muxval);
  101. return priv->realbus->read(priv->realbus, addr, devad, regnum);
  102. }
  103. static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad,
  104. int regnum, u16 value)
  105. {
  106. struct t4240qds_mdio *priv = bus->priv;
  107. t4240qds_mux_mdio(priv->muxval);
  108. return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
  109. }
  110. static int t4240qds_mdio_reset(struct mii_dev *bus)
  111. {
  112. struct t4240qds_mdio *priv = bus->priv;
  113. return priv->realbus->reset(priv->realbus);
  114. }
  115. static int t4240qds_mdio_init(char *realbusname, u8 muxval)
  116. {
  117. struct t4240qds_mdio *pmdio;
  118. struct mii_dev *bus = mdio_alloc();
  119. if (!bus) {
  120. printf("Failed to allocate T4240QDS MDIO bus\n");
  121. return -1;
  122. }
  123. pmdio = malloc(sizeof(*pmdio));
  124. if (!pmdio) {
  125. printf("Failed to allocate T4240QDS private data\n");
  126. free(bus);
  127. return -1;
  128. }
  129. bus->read = t4240qds_mdio_read;
  130. bus->write = t4240qds_mdio_write;
  131. bus->reset = t4240qds_mdio_reset;
  132. strcpy(bus->name, t4240qds_mdio_name_for_muxval(muxval));
  133. pmdio->realbus = miiphy_get_dev_by_name(realbusname);
  134. if (!pmdio->realbus) {
  135. printf("No bus with name %s\n", realbusname);
  136. free(bus);
  137. free(pmdio);
  138. return -1;
  139. }
  140. pmdio->muxval = muxval;
  141. bus->priv = pmdio;
  142. return mdio_register(bus);
  143. }
  144. void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
  145. enum fm_port port, int offset)
  146. {
  147. int interface = fm_info_get_enet_if(port);
  148. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  149. u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  150. prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  151. if (interface == PHY_INTERFACE_MODE_SGMII ||
  152. interface == PHY_INTERFACE_MODE_QSGMII) {
  153. switch (port) {
  154. case FM1_DTSEC1:
  155. if (qsgmiiphy_fix[port])
  156. fdt_set_phy_handle(blob, prop, pa,
  157. "sgmii_phy21");
  158. break;
  159. case FM1_DTSEC2:
  160. if (qsgmiiphy_fix[port])
  161. fdt_set_phy_handle(blob, prop, pa,
  162. "sgmii_phy22");
  163. break;
  164. case FM1_DTSEC3:
  165. if (qsgmiiphy_fix[port])
  166. fdt_set_phy_handle(blob, prop, pa,
  167. "sgmii_phy23");
  168. break;
  169. case FM1_DTSEC4:
  170. if (qsgmiiphy_fix[port])
  171. fdt_set_phy_handle(blob, prop, pa,
  172. "sgmii_phy24");
  173. break;
  174. case FM1_DTSEC6:
  175. if (qsgmiiphy_fix[port])
  176. fdt_set_phy_handle(blob, prop, pa,
  177. "sgmii_phy12");
  178. break;
  179. case FM1_DTSEC9:
  180. if (qsgmiiphy_fix[port])
  181. fdt_set_phy_handle(blob, prop, pa,
  182. "sgmii_phy14");
  183. else
  184. fdt_set_phy_handle(blob, prop, pa,
  185. "phy_sgmii4");
  186. break;
  187. case FM1_DTSEC10:
  188. if (qsgmiiphy_fix[port])
  189. fdt_set_phy_handle(blob, prop, pa,
  190. "sgmii_phy13");
  191. else
  192. fdt_set_phy_handle(blob, prop, pa,
  193. "phy_sgmii3");
  194. break;
  195. case FM2_DTSEC1:
  196. if (qsgmiiphy_fix[port])
  197. fdt_set_phy_handle(blob, prop, pa,
  198. "sgmii_phy41");
  199. break;
  200. case FM2_DTSEC2:
  201. if (qsgmiiphy_fix[port])
  202. fdt_set_phy_handle(blob, prop, pa,
  203. "sgmii_phy42");
  204. break;
  205. case FM2_DTSEC3:
  206. if (qsgmiiphy_fix[port])
  207. fdt_set_phy_handle(blob, prop, pa,
  208. "sgmii_phy43");
  209. break;
  210. case FM2_DTSEC4:
  211. if (qsgmiiphy_fix[port])
  212. fdt_set_phy_handle(blob, prop, pa,
  213. "sgmii_phy44");
  214. break;
  215. case FM2_DTSEC6:
  216. if (qsgmiiphy_fix[port])
  217. fdt_set_phy_handle(blob, prop, pa,
  218. "sgmii_phy32");
  219. break;
  220. case FM2_DTSEC9:
  221. if (qsgmiiphy_fix[port])
  222. fdt_set_phy_handle(blob, prop, pa,
  223. "sgmii_phy34");
  224. else
  225. fdt_set_phy_handle(blob, prop, pa,
  226. "phy_sgmii12");
  227. break;
  228. case FM2_DTSEC10:
  229. if (qsgmiiphy_fix[port])
  230. fdt_set_phy_handle(blob, prop, pa,
  231. "sgmii_phy33");
  232. else
  233. fdt_set_phy_handle(blob, prop, pa,
  234. "phy_sgmii11");
  235. break;
  236. default:
  237. break;
  238. }
  239. } else if (interface == PHY_INTERFACE_MODE_XGMII &&
  240. ((prtcl2 == 55) || (prtcl2 == 57))) {
  241. /*
  242. * if the 10G is XFI, check hwconfig to see what is the
  243. * media type, there are two types, fiber or copper,
  244. * fix the dtb accordingly.
  245. */
  246. int media_type = 0;
  247. struct fixed_link f_link;
  248. char lane_mode[20] = {"10GBASE-KR"};
  249. char buf[32] = "serdes-2,";
  250. int off;
  251. switch (port) {
  252. case FM1_10GEC1:
  253. if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
  254. media_type = 1;
  255. fdt_set_phy_handle(blob, prop, pa,
  256. "phy_xfi1");
  257. sprintf(buf, "%s%s%s", buf, "lane-a,",
  258. (char *)lane_mode);
  259. }
  260. break;
  261. case FM1_10GEC2:
  262. if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
  263. media_type = 1;
  264. fdt_set_phy_handle(blob, prop, pa,
  265. "phy_xfi2");
  266. sprintf(buf, "%s%s%s", buf, "lane-b,",
  267. (char *)lane_mode);
  268. }
  269. break;
  270. case FM2_10GEC1:
  271. if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g1")) {
  272. media_type = 1;
  273. fdt_set_phy_handle(blob, prop, pa,
  274. "phy_xfi3");
  275. sprintf(buf, "%s%s%s", buf, "lane-d,",
  276. (char *)lane_mode);
  277. }
  278. break;
  279. case FM2_10GEC2:
  280. if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g2")) {
  281. media_type = 1;
  282. fdt_set_phy_handle(blob, prop, pa,
  283. "phy_xfi4");
  284. sprintf(buf, "%s%s%s", buf, "lane-c,",
  285. (char *)lane_mode);
  286. }
  287. break;
  288. default:
  289. return;
  290. }
  291. if (!media_type) {
  292. /* fixed-link is used for XFI fiber cable */
  293. fdt_delprop(blob, offset, "phy-handle");
  294. f_link.phy_id = port;
  295. f_link.duplex = 1;
  296. f_link.link_speed = 10000;
  297. f_link.pause = 0;
  298. f_link.asym_pause = 0;
  299. fdt_setprop(blob, offset, "fixed-link", &f_link,
  300. sizeof(f_link));
  301. } else {
  302. /* set property for copper cable */
  303. off = fdt_node_offset_by_compat_reg(blob,
  304. "fsl,fman-memac-mdio", pa + 0x1000);
  305. fdt_setprop_string(blob, off, "lane-instance", buf);
  306. }
  307. }
  308. }
  309. void fdt_fixup_board_enet(void *fdt)
  310. {
  311. int i;
  312. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  313. u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  314. prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  315. for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
  316. switch (fm_info_get_enet_if(i)) {
  317. case PHY_INTERFACE_MODE_SGMII:
  318. case PHY_INTERFACE_MODE_QSGMII:
  319. switch (mdio_mux[i]) {
  320. case EMI1_SLOT1:
  321. fdt_status_okay_by_alias(fdt, "emi1_slot1");
  322. break;
  323. case EMI1_SLOT2:
  324. fdt_status_okay_by_alias(fdt, "emi1_slot2");
  325. break;
  326. case EMI1_SLOT3:
  327. fdt_status_okay_by_alias(fdt, "emi1_slot3");
  328. break;
  329. case EMI1_SLOT4:
  330. fdt_status_okay_by_alias(fdt, "emi1_slot4");
  331. break;
  332. default:
  333. break;
  334. }
  335. break;
  336. case PHY_INTERFACE_MODE_XGMII:
  337. /* check if it's XFI interface for 10g */
  338. if ((prtcl2 == 55) || (prtcl2 == 57)) {
  339. if (i == FM1_10GEC1 && hwconfig_sub(
  340. "fsl_10gkr_copper", "fm1_10g1"))
  341. fdt_status_okay_by_alias(
  342. fdt, "xfi_pcs_mdio1");
  343. if (i == FM1_10GEC2 && hwconfig_sub(
  344. "fsl_10gkr_copper", "fm1_10g2"))
  345. fdt_status_okay_by_alias(
  346. fdt, "xfi_pcs_mdio2");
  347. if (i == FM2_10GEC1 && hwconfig_sub(
  348. "fsl_10gkr_copper", "fm2_10g1"))
  349. fdt_status_okay_by_alias(
  350. fdt, "xfi_pcs_mdio3");
  351. if (i == FM2_10GEC2 && hwconfig_sub(
  352. "fsl_10gkr_copper", "fm2_10g2"))
  353. fdt_status_okay_by_alias(
  354. fdt, "xfi_pcs_mdio4");
  355. break;
  356. }
  357. switch (i) {
  358. case FM1_10GEC1:
  359. fdt_status_okay_by_alias(fdt, "emi2_xauislot1");
  360. break;
  361. case FM1_10GEC2:
  362. fdt_status_okay_by_alias(fdt, "emi2_xauislot2");
  363. break;
  364. case FM2_10GEC1:
  365. fdt_status_okay_by_alias(fdt, "emi2_xauislot3");
  366. break;
  367. case FM2_10GEC2:
  368. fdt_status_okay_by_alias(fdt, "emi2_xauislot4");
  369. break;
  370. default:
  371. break;
  372. }
  373. break;
  374. default:
  375. break;
  376. }
  377. }
  378. }
  379. static void initialize_qsgmiiphy_fix(void)
  380. {
  381. int i;
  382. unsigned short reg;
  383. for (i = 1; i <= 4; i++) {
  384. /*
  385. * Try to read if a SGMII card is used, we do it slot by slot.
  386. * if a SGMII PHY address is valid on a slot, then we mark
  387. * all ports on the slot, then fix the PHY address for the
  388. * marked port when doing dtb fixup.
  389. */
  390. if (miiphy_read(mdio_names[i],
  391. SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, &reg) != 0) {
  392. debug("Slot%d PHY ID register 2 read failed\n", i);
  393. continue;
  394. }
  395. debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg);
  396. if (reg == 0xFFFF) {
  397. /* No physical device present at this address */
  398. continue;
  399. }
  400. switch (i) {
  401. case 1:
  402. qsgmiiphy_fix[FM1_DTSEC5] = 1;
  403. qsgmiiphy_fix[FM1_DTSEC6] = 1;
  404. qsgmiiphy_fix[FM1_DTSEC9] = 1;
  405. qsgmiiphy_fix[FM1_DTSEC10] = 1;
  406. slot_qsgmii_phyaddr[1][0] = SGMII_CARD_PORT1_PHY_ADDR;
  407. slot_qsgmii_phyaddr[1][1] = SGMII_CARD_PORT2_PHY_ADDR;
  408. slot_qsgmii_phyaddr[1][2] = SGMII_CARD_PORT3_PHY_ADDR;
  409. slot_qsgmii_phyaddr[1][3] = SGMII_CARD_PORT4_PHY_ADDR;
  410. break;
  411. case 2:
  412. qsgmiiphy_fix[FM1_DTSEC1] = 1;
  413. qsgmiiphy_fix[FM1_DTSEC2] = 1;
  414. qsgmiiphy_fix[FM1_DTSEC3] = 1;
  415. qsgmiiphy_fix[FM1_DTSEC4] = 1;
  416. slot_qsgmii_phyaddr[2][0] = SGMII_CARD_PORT1_PHY_ADDR;
  417. slot_qsgmii_phyaddr[2][1] = SGMII_CARD_PORT2_PHY_ADDR;
  418. slot_qsgmii_phyaddr[2][2] = SGMII_CARD_PORT3_PHY_ADDR;
  419. slot_qsgmii_phyaddr[2][3] = SGMII_CARD_PORT4_PHY_ADDR;
  420. break;
  421. case 3:
  422. qsgmiiphy_fix[FM2_DTSEC5] = 1;
  423. qsgmiiphy_fix[FM2_DTSEC6] = 1;
  424. qsgmiiphy_fix[FM2_DTSEC9] = 1;
  425. qsgmiiphy_fix[FM2_DTSEC10] = 1;
  426. slot_qsgmii_phyaddr[3][0] = SGMII_CARD_PORT1_PHY_ADDR;
  427. slot_qsgmii_phyaddr[3][1] = SGMII_CARD_PORT2_PHY_ADDR;
  428. slot_qsgmii_phyaddr[3][2] = SGMII_CARD_PORT3_PHY_ADDR;
  429. slot_qsgmii_phyaddr[3][3] = SGMII_CARD_PORT4_PHY_ADDR;
  430. break;
  431. case 4:
  432. qsgmiiphy_fix[FM2_DTSEC1] = 1;
  433. qsgmiiphy_fix[FM2_DTSEC2] = 1;
  434. qsgmiiphy_fix[FM2_DTSEC3] = 1;
  435. qsgmiiphy_fix[FM2_DTSEC4] = 1;
  436. slot_qsgmii_phyaddr[4][0] = SGMII_CARD_PORT1_PHY_ADDR;
  437. slot_qsgmii_phyaddr[4][1] = SGMII_CARD_PORT2_PHY_ADDR;
  438. slot_qsgmii_phyaddr[4][2] = SGMII_CARD_PORT3_PHY_ADDR;
  439. slot_qsgmii_phyaddr[4][3] = SGMII_CARD_PORT4_PHY_ADDR;
  440. break;
  441. default:
  442. break;
  443. }
  444. }
  445. }
  446. int board_eth_init(bd_t *bis)
  447. {
  448. #if defined(CONFIG_FMAN_ENET)
  449. int i, idx, lane, slot, interface;
  450. struct memac_mdio_info dtsec_mdio_info;
  451. struct memac_mdio_info tgec_mdio_info;
  452. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  453. u32 srds_prtcl_s1, srds_prtcl_s2;
  454. srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
  455. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  456. srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  457. srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
  458. FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  459. srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  460. /* Initialize the mdio_mux array so we can recognize empty elements */
  461. for (i = 0; i < NUM_FM_PORTS; i++)
  462. mdio_mux[i] = EMI_NONE;
  463. dtsec_mdio_info.regs =
  464. (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
  465. dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  466. /* Register the 1G MDIO bus */
  467. fm_memac_mdio_init(bis, &dtsec_mdio_info);
  468. tgec_mdio_info.regs =
  469. (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
  470. tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  471. /* Register the 10G MDIO bus */
  472. fm_memac_mdio_init(bis, &tgec_mdio_info);
  473. /* Register the muxing front-ends to the MDIO buses */
  474. t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
  475. t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
  476. t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
  477. t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
  478. t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
  479. t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
  480. t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
  481. t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
  482. initialize_qsgmiiphy_fix();
  483. switch (srds_prtcl_s1) {
  484. case 1:
  485. case 2:
  486. case 4:
  487. /* XAUI/HiGig in Slot1 and Slot2 */
  488. fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
  489. fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
  490. break;
  491. case 27:
  492. case 28:
  493. case 35:
  494. case 36:
  495. /* SGMII in Slot1 and Slot2 */
  496. fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
  497. fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
  498. fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
  499. fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
  500. fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
  501. fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
  502. if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
  503. fm_info_set_phy_address(FM1_DTSEC9,
  504. slot_qsgmii_phyaddr[1][3]);
  505. fm_info_set_phy_address(FM1_DTSEC10,
  506. slot_qsgmii_phyaddr[1][2]);
  507. }
  508. break;
  509. case 37:
  510. case 38:
  511. fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
  512. fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
  513. fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
  514. fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
  515. fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
  516. fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
  517. if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
  518. fm_info_set_phy_address(FM1_DTSEC9,
  519. slot_qsgmii_phyaddr[1][2]);
  520. fm_info_set_phy_address(FM1_DTSEC10,
  521. slot_qsgmii_phyaddr[1][3]);
  522. }
  523. break;
  524. case 39:
  525. case 40:
  526. case 45:
  527. case 46:
  528. case 47:
  529. case 48:
  530. fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
  531. fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
  532. if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
  533. fm_info_set_phy_address(FM1_DTSEC10,
  534. slot_qsgmii_phyaddr[1][2]);
  535. fm_info_set_phy_address(FM1_DTSEC9,
  536. slot_qsgmii_phyaddr[1][3]);
  537. }
  538. fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
  539. fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
  540. fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
  541. fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
  542. break;
  543. default:
  544. puts("Invalid SerDes1 protocol for T4240QDS\n");
  545. break;
  546. }
  547. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  548. idx = i - FM1_DTSEC1;
  549. interface = fm_info_get_enet_if(i);
  550. switch (interface) {
  551. case PHY_INTERFACE_MODE_SGMII:
  552. case PHY_INTERFACE_MODE_QSGMII:
  553. if (interface == PHY_INTERFACE_MODE_QSGMII) {
  554. if (idx <= 3)
  555. lane = serdes_get_first_lane(FSL_SRDS_1,
  556. QSGMII_FM1_A);
  557. else
  558. lane = serdes_get_first_lane(FSL_SRDS_1,
  559. QSGMII_FM1_B);
  560. if (lane < 0)
  561. break;
  562. slot = lane_to_slot_fsm1[lane];
  563. debug("FM1@DTSEC%u expects QSGMII in slot %u\n",
  564. idx + 1, slot);
  565. } else {
  566. lane = serdes_get_first_lane(FSL_SRDS_1,
  567. SGMII_FM1_DTSEC1 + idx);
  568. if (lane < 0)
  569. break;
  570. slot = lane_to_slot_fsm1[lane];
  571. debug("FM1@DTSEC%u expects SGMII in slot %u\n",
  572. idx + 1, slot);
  573. }
  574. if (QIXIS_READ(present2) & (1 << (slot - 1)))
  575. fm_disable_port(i);
  576. switch (slot) {
  577. case 1:
  578. mdio_mux[i] = EMI1_SLOT1;
  579. fm_info_set_mdio(i,
  580. mii_dev_for_muxval(mdio_mux[i]));
  581. break;
  582. case 2:
  583. mdio_mux[i] = EMI1_SLOT2;
  584. fm_info_set_mdio(i,
  585. mii_dev_for_muxval(mdio_mux[i]));
  586. break;
  587. };
  588. break;
  589. case PHY_INTERFACE_MODE_RGMII:
  590. /* FM1 DTSEC5 routes to RGMII with EC2 */
  591. debug("FM1@DTSEC%u is RGMII at address %u\n",
  592. idx + 1, 2);
  593. if (i == FM1_DTSEC5)
  594. fm_info_set_phy_address(i, 2);
  595. mdio_mux[i] = EMI1_RGMII;
  596. fm_info_set_mdio(i,
  597. mii_dev_for_muxval(mdio_mux[i]));
  598. break;
  599. default:
  600. break;
  601. }
  602. }
  603. for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
  604. idx = i - FM1_10GEC1;
  605. switch (fm_info_get_enet_if(i)) {
  606. case PHY_INTERFACE_MODE_XGMII:
  607. if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
  608. /* A fake PHY address to make U-Boot happy */
  609. fm_info_set_phy_address(i, i);
  610. } else {
  611. lane = serdes_get_first_lane(FSL_SRDS_1,
  612. XAUI_FM1_MAC9 + idx);
  613. if (lane < 0)
  614. break;
  615. slot = lane_to_slot_fsm1[lane];
  616. if (QIXIS_READ(present2) & (1 << (slot - 1)))
  617. fm_disable_port(i);
  618. }
  619. mdio_mux[i] = EMI2;
  620. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  621. break;
  622. default:
  623. break;
  624. }
  625. }
  626. #if (CONFIG_SYS_NUM_FMAN == 2)
  627. switch (srds_prtcl_s2) {
  628. case 1:
  629. case 2:
  630. case 4:
  631. /* XAUI/HiGig in Slot3 and Slot4 */
  632. fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
  633. fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
  634. break;
  635. case 6:
  636. case 7:
  637. case 12:
  638. case 13:
  639. case 14:
  640. case 15:
  641. case 16:
  642. case 21:
  643. case 22:
  644. case 23:
  645. case 24:
  646. case 25:
  647. case 26:
  648. /* XAUI/HiGig in Slot3, SGMII in Slot4 */
  649. fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
  650. fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
  651. fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
  652. fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
  653. fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
  654. break;
  655. case 27:
  656. case 28:
  657. case 35:
  658. case 36:
  659. /* SGMII in Slot3 and Slot4 */
  660. fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
  661. fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
  662. fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
  663. fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
  664. fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
  665. fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
  666. fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
  667. fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
  668. break;
  669. case 37:
  670. case 38:
  671. /* QSGMII in Slot3 and Slot4 */
  672. fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
  673. fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
  674. fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
  675. fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
  676. fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
  677. fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
  678. fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]);
  679. fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]);
  680. break;
  681. case 39:
  682. case 40:
  683. case 45:
  684. case 46:
  685. case 47:
  686. case 48:
  687. /* SGMII in Slot3 */
  688. fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
  689. fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
  690. fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
  691. fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
  692. /* QSGMII in Slot4 */
  693. fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
  694. fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
  695. fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
  696. fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
  697. break;
  698. case 49:
  699. case 50:
  700. case 51:
  701. case 52:
  702. case 53:
  703. case 54:
  704. fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
  705. fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
  706. fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
  707. fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
  708. fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
  709. break;
  710. case 55:
  711. case 57:
  712. /* XFI in Slot3, SGMII in Slot4 */
  713. fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
  714. fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
  715. fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
  716. fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
  717. break;
  718. default:
  719. puts("Invalid SerDes2 protocol for T4240QDS\n");
  720. break;
  721. }
  722. for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
  723. idx = i - FM2_DTSEC1;
  724. interface = fm_info_get_enet_if(i);
  725. switch (interface) {
  726. case PHY_INTERFACE_MODE_SGMII:
  727. case PHY_INTERFACE_MODE_QSGMII:
  728. if (interface == PHY_INTERFACE_MODE_QSGMII) {
  729. if (idx <= 3)
  730. lane = serdes_get_first_lane(FSL_SRDS_2,
  731. QSGMII_FM2_A);
  732. else
  733. lane = serdes_get_first_lane(FSL_SRDS_2,
  734. QSGMII_FM2_B);
  735. if (lane < 0)
  736. break;
  737. slot = lane_to_slot_fsm2[lane];
  738. debug("FM2@DTSEC%u expects QSGMII in slot %u\n",
  739. idx + 1, slot);
  740. } else {
  741. lane = serdes_get_first_lane(FSL_SRDS_2,
  742. SGMII_FM2_DTSEC1 + idx);
  743. if (lane < 0)
  744. break;
  745. slot = lane_to_slot_fsm2[lane];
  746. debug("FM2@DTSEC%u expects SGMII in slot %u\n",
  747. idx + 1, slot);
  748. }
  749. if (QIXIS_READ(present2) & (1 << (slot - 1)))
  750. fm_disable_port(i);
  751. switch (slot) {
  752. case 3:
  753. mdio_mux[i] = EMI1_SLOT3;
  754. fm_info_set_mdio(i,
  755. mii_dev_for_muxval(mdio_mux[i]));
  756. break;
  757. case 4:
  758. mdio_mux[i] = EMI1_SLOT4;
  759. fm_info_set_mdio(i,
  760. mii_dev_for_muxval(mdio_mux[i]));
  761. break;
  762. };
  763. break;
  764. case PHY_INTERFACE_MODE_RGMII:
  765. /*
  766. * If DTSEC5 is RGMII, then it's routed via via EC1 to
  767. * the first on-board RGMII port. If DTSEC6 is RGMII,
  768. * then it's routed via via EC2 to the second on-board
  769. * RGMII port.
  770. */
  771. debug("FM2@DTSEC%u is RGMII at address %u\n",
  772. idx + 1, i == FM2_DTSEC5 ? 1 : 2);
  773. fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2);
  774. mdio_mux[i] = EMI1_RGMII;
  775. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  776. break;
  777. default:
  778. break;
  779. }
  780. }
  781. for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
  782. idx = i - FM2_10GEC1;
  783. switch (fm_info_get_enet_if(i)) {
  784. case PHY_INTERFACE_MODE_XGMII:
  785. if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
  786. /* A fake PHY address to make U-Boot happy */
  787. fm_info_set_phy_address(i, i);
  788. } else {
  789. lane = serdes_get_first_lane(FSL_SRDS_2,
  790. XAUI_FM2_MAC9 + idx);
  791. if (lane < 0)
  792. break;
  793. slot = lane_to_slot_fsm2[lane];
  794. if (QIXIS_READ(present2) & (1 << (slot - 1)))
  795. fm_disable_port(i);
  796. }
  797. mdio_mux[i] = EMI2;
  798. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  799. break;
  800. default:
  801. break;
  802. }
  803. }
  804. #endif /* CONFIG_SYS_NUM_FMAN */
  805. cpu_eth_init(bis);
  806. #endif /* CONFIG_FMAN_ENET */
  807. return pci_eth_init(bis);
  808. }