t208xrdb.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2013 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <env.h>
  8. #include <fdt_support.h>
  9. #include <i2c.h>
  10. #include <image.h>
  11. #include <init.h>
  12. #include <netdev.h>
  13. #include <linux/compiler.h>
  14. #include <asm/mmu.h>
  15. #include <asm/processor.h>
  16. #include <asm/immap_85xx.h>
  17. #include <asm/fsl_law.h>
  18. #include <asm/fsl_serdes.h>
  19. #include <asm/fsl_liodn.h>
  20. #include <fm_eth.h>
  21. #include "t208xrdb.h"
  22. #include "cpld.h"
  23. #include "../common/vid.h"
  24. DECLARE_GLOBAL_DATA_PTR;
  25. int checkboard(void)
  26. {
  27. struct cpu_type *cpu = gd->arch.cpu;
  28. static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
  29. printf("Board: %sRDB, ", cpu->name);
  30. printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
  31. CPLD_READ(hw_ver), CPLD_READ(sw_ver));
  32. #ifdef CONFIG_SDCARD
  33. puts("SD/MMC\n");
  34. #elif CONFIG_SPIFLASH
  35. puts("SPI\n");
  36. #else
  37. u8 reg;
  38. reg = CPLD_READ(flash_csr);
  39. if (reg & CPLD_BOOT_SEL) {
  40. puts("NAND\n");
  41. } else {
  42. reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
  43. printf("NOR vBank%d\n", reg);
  44. }
  45. #endif
  46. puts("SERDES Reference Clocks:\n");
  47. printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
  48. printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[0], freq[0]);
  49. return 0;
  50. }
  51. int board_early_init_r(void)
  52. {
  53. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  54. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  55. /*
  56. * Remap Boot flash + PROMJET region to caching-inhibited
  57. * so that flash can be erased properly.
  58. */
  59. /* Flush d-cache and invalidate i-cache of any FLASH data */
  60. flush_dcache();
  61. invalidate_icache();
  62. if (flash_esel == -1) {
  63. /* very unlikely unless something is messed up */
  64. puts("Error: Could not find TLB for FLASH BASE\n");
  65. flash_esel = 2; /* give our best effort to continue */
  66. } else {
  67. /* invalidate existing TLB entry for flash + promjet */
  68. disable_tlb(flash_esel);
  69. }
  70. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  71. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  72. 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  73. /*
  74. * Adjust core voltage according to voltage ID
  75. * This function changes I2C mux to channel 2.
  76. */
  77. if (adjust_vdd(0))
  78. printf("Warning: Adjusting core voltage failed.\n");
  79. return 0;
  80. }
  81. unsigned long get_board_sys_clk(void)
  82. {
  83. return CONFIG_SYS_CLK_FREQ;
  84. }
  85. unsigned long get_board_ddr_clk(void)
  86. {
  87. return CONFIG_DDR_CLK_FREQ;
  88. }
  89. int misc_init_r(void)
  90. {
  91. u8 reg;
  92. /* Reset CS4315 PHY */
  93. reg = CPLD_READ(reset_ctl);
  94. reg |= CPLD_RSTCON_EDC_RST;
  95. CPLD_WRITE(reset_ctl, reg);
  96. return 0;
  97. }
  98. int ft_board_setup(void *blob, bd_t *bd)
  99. {
  100. phys_addr_t base;
  101. phys_size_t size;
  102. ft_cpu_setup(blob, bd);
  103. base = env_get_bootm_low();
  104. size = env_get_bootm_size();
  105. fdt_fixup_memory(blob, (u64)base, (u64)size);
  106. #ifdef CONFIG_PCI
  107. pci_of_setup(blob, bd);
  108. #endif
  109. fdt_fixup_liodn(blob);
  110. fsl_fdt_fixup_dr_usb(blob, bd);
  111. #ifdef CONFIG_SYS_DPAA_FMAN
  112. fdt_fixup_fman_ethernet(blob);
  113. fdt_fixup_board_enet(blob);
  114. #endif
  115. return 0;
  116. }